Mercurial > flash_v2
changeset 1424:5268028c09c4
2003-09-21 Jonathan Larmour <jifl@eCosCentric.com>
* src/var_misc.c (hal_variant_init): Set FPSCR on startup.
* src/sh4_scif.c (cyg_hal_plf_scif_set_baud): New function, taken
from init code, but with fix to wait for hardware to settle.
(cyg_hal_plf_scif_control): Add __COMMCTL_GETBAUD and _SETBAUD support
using above function.
* include/sh4_scif.h: Add baud_rate to channel data.
* include/mod_regs_ser.h (CYGARC_SCBRR_N): Don't tweak BRR for
values < 4800 or > 115200 as it gets the values wrong. Instead trust
the developer to DTRT.
(CYGARC_REG_SCIF_SCLSR_ORER): Add definition for overrun in line status
reg.
2003-09-19 John Dallaway <jld@ecoscentric.com>
* cdl/hal_sh_sh4.cdl: Specify default CDL values for sh4_202_md
target.
2003-09-11 Nick Garnett <nickg@ecoscentric.com>
* include/var_regs.h (CYG_FPSCR): Changed initial value of fpscr
to do round-to-nearest rather than round-to-zero.
2003-09-08 Nick Garnett <nickg@ecoscentric.com>
* include/mod_202.h: Added define for UBC. The 202 appears to have
one, although there is no documented info. It is also not clear
what version it is. Setting this to 1 seems to work.
* include/mod_regs_cac.h:
* include/variant.inc:
Updated cache dimensions and initialization to support larger, two
way cache in sh4-202.
2003-09-05 Nick Garnett <nickg@ecoscentric.com>
* include/variant.inc:
* include/var_reg.h:
* include/mod_202.h:
* include/mod_regs_cpg.h:
* include/mod_regs_emi.h:
* include/mod_regs_femi.h:
* include/mod_regs_intc.h:
* cdl/hal_sh_sh4.cdl: Added SH-202 sub-variant, extra
functional units, and modifications to existing units for this
variant.
line wrap: on
line diff
--- a/packages/hal/sh/sh4/current/ChangeLog +++ b/packages/hal/sh/sh4/current/ChangeLog @@ -1,3 +1,54 @@ +2003-09-21 Jonathan Larmour <jifl@eCosCentric.com> + + * src/var_misc.c (hal_variant_init): Set FPSCR on startup. + + * src/sh4_scif.c (cyg_hal_plf_scif_set_baud): New function, taken + from init code, but with fix to wait for hardware to settle. + (cyg_hal_plf_scif_control): Add __COMMCTL_GETBAUD and _SETBAUD support + using above function. + + * include/sh4_scif.h: Add baud_rate to channel data. + + * include/mod_regs_ser.h (CYGARC_SCBRR_N): Don't tweak BRR for + values < 4800 or > 115200 as it gets the values wrong. Instead trust + the developer to DTRT. + (CYGARC_REG_SCIF_SCLSR_ORER): Add definition for overrun in line status + reg. + +2003-09-19 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_sh_sh4.cdl: Specify default CDL values for sh4_202_md + target. + +2003-09-11 Nick Garnett <nickg@ecoscentric.com> + + * include/var_regs.h (CYG_FPSCR): Changed initial value of fpscr + to do round-to-nearest rather than round-to-zero. + +2003-09-08 Nick Garnett <nickg@ecoscentric.com> + + * include/mod_202.h: Added define for UBC. The 202 appears to have + one, although there is no documented info. It is also not clear + what version it is. Setting this to 1 seems to work. + + * include/mod_regs_cac.h: + * include/variant.inc: + Updated cache dimensions and initialization to support larger, two + way cache in sh4-202. + +2003-09-05 Nick Garnett <nickg@ecoscentric.com> + + * include/variant.inc: + * include/var_reg.h: + * include/mod_202.h: + * include/mod_regs_cpg.h: + * include/mod_regs_emi.h: + * include/mod_regs_femi.h: + * include/mod_regs_intc.h: + * cdl/hal_sh_sh4.cdl: Added SH-202 sub-variant, extra + functional units, and modifications to existing units for this + variant. + 2003-02-05 Nick Garnett <nickg@calivar.com> * include/var_cache.h: Added include for hal_io.h since this file
--- a/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl +++ b/packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl @@ -9,6 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -40,7 +41,7 @@ # ==================================================================== ######DESCRIPTIONBEGIN#### # -# Author(s): jskov +# Author(s): jskov, nickg # Original data: jskov # Contributors: # Date: 1999-10-29 @@ -91,7 +92,7 @@ cdl_package CYGPKG_HAL_SH_SH4 { implements CYGINT_HAL_SH_VARIANT implements CYGINT_HAL_SH_CPG_T1 requires ! CYGHWR_HAL_SH_CACHE_ENABLE - default_value 1 + default_value 0 no_define define -file=system.h CYGPKG_HAL_SH_7750 description " @@ -123,6 +124,26 @@ cdl_package CYGPKG_HAL_SH_SH4 { } } + cdl_component CYGPKG_HAL_SH_202 { + display "SH 202 microprocessor" + parent CYGPKG_HAL_SH_CPU + implements CYGINT_HAL_SH_VARIANT + implements CYGINT_HAL_SH_CPG_T1 + requires CYGHWR_HAL_SH_FPU + requires { CYGHWR_HAL_SH_FPU_REGS == 16 } + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_202 + description " + The SH4-202 microprocessor. This is an embedded part that in + addition to the SH4 processor core has built in peripherals + such as memory controllers, DMA controllers, serial ports and + timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_202.h>" + } + } + cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS { display "SH on-chip generic clock controls" description "
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_202.h @@ -0,0 +1,106 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_202.h +// +// List modules available on CPU +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2003-08-20 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_CPG 1 +#define CYGARC_SH_MOD_SCIF 1 +#define CYGARC_SH_MOD_UBC 1 +#define CYGARC_SH_MOD_INTC 2 + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +//============================================================================= +// Icache +// Cache dimenions +#define CYGARC_SH_MOD_CAC_I_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_I_LINE_SIZE 32 // Size of a cache line +#define CYGARC_SH_MOD_CAC_I_WAYS 2 // Associativity of the cache + +// Cache addressing information +// entry: bits 12 - 5 +#define CYGARC_SH_MOD_ICAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_ICAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_ICAC_ADDRESS_STEP 0x00000020 +// V : bit 0 +// Writing zero to V forces an invalidate of the line +#define CYGARC_SH_MOD_ICAC_ADDRESS_FLUSH 0x00000000 + + +//============================================================================= +// Dcache +// Cache dimenions +#define CYGARC_SH_MOD_CAC_D_SIZE 32768 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_D_LINE_SIZE 32 // Size of a cache line +#define CYGARC_SH_MOD_CAC_D_WAYS 2 // Associativity of the cache + +// Cache addressing information +// entry: bits 13 - 5 +#define CYGARC_SH_MOD_DCAC_ADDRESS_BASE 0xf4000000 +#define CYGARC_SH_MOD_DCAC_ADDRESS_TOP 0xf4008000 +#define CYGARC_SH_MOD_DCAC_ADDRESS_STEP 0x00000020 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_DCAC_ADDRESS_FLUSH 0x00000000 + +//----------------------------------------------------------------------------- +// Extra details for interrupt handling +#define CYGARC_SH_SOFTWARE_IP_UPDATE + +#endif // CYGONCE_HAL_MOD_202_H
--- a/packages/hal/sh/sh4/current/include/mod_regs_cac.h +++ b/packages/hal/sh/sh4/current/include/mod_regs_cac.h @@ -9,6 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -41,7 +42,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov +// Contributors:jskov, nickg // Date: 2000-10-30 // //####DESCRIPTIONEND#### @@ -65,6 +66,12 @@ #define CYGARC_REG_CCR_WT 0x00000002 // Write Through enable #define CYGARC_REG_CCR_OCE 0x00000001 // OC Enable +#ifdef CYGPKG_HAL_SH_202 +#define CYGARC_REG_CCR_EMODE 0x80000000 // Enhanced mode +#else +#define CYGARC_REG_CCR_EMODE 0x00000000 // No enhanced mode +#endif + #define CYGARC_REG_CCR_CE 0x00000101 // IC, OC Enable #define CYGARC_REG_CCR_CF 0x00000808 // IC, OC Invalidation
--- a/packages/hal/sh/sh4/current/include/mod_regs_cpg.h +++ b/packages/hal/sh/sh4/current/include/mod_regs_cpg.h @@ -9,6 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -41,7 +42,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov +// Contributors:jskov, nickg // Date: 2000-10-30 // //####DESCRIPTIONEND#### @@ -56,6 +57,10 @@ #define CYGARC_REG_WTCSR 0xFFC0000C // read 8bit, write 16bit #define CYGARC_REG_STBCR2 0xFFC00010 +#ifdef CYGPKG_HAL_SH_202 +#define CYGARC_REG_FRQCR3 0xFE0A0018 +#endif + #define CYGARC_REG_WTCNT_WRITE 0x5a00 // top 8bit value for write #define CYGARC_REG_WTCSR_WRITE 0xa500 // top 8bit value for write @@ -81,8 +86,12 @@ // PLL1 #if (CYGHWR_HAL_SH_OOC_PLL_1 == 0) # define CYGARC_REG_FRQCR_INIT_PLL1 0x0000 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 4) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400 #elif (CYGHWR_HAL_SH_OOC_PLL_1 == 6) # define CYGARC_REG_FRQCR_INIT_PLL1 0x0400 +#elif (CYGHWR_HAL_SH_OOC_PLL_1 == 8) +# define CYGARC_REG_FRQCR_INIT_PLL1 0x0400 #else # error "Unsupported PLL1 setting" #endif
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_emi.h @@ -0,0 +1,101 @@ +//============================================================================= +// +// mod_regs_emi.h +// +// EMI (External Memory Interface) Module register definitions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting the copyright +// holder. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 2003-08-20 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- + +#define CYGARC_REG_EMI_BASE 0xFEC00000 +#define CYGARC_REG_EMI_VCR_L (CYGARC_REG_EMI_BASE+0x00) +#define CYGARC_REG_EMI_VCR_H (CYGARC_REG_EMI_BASE+0x04) +#define CYGARC_REG_EMI_MIM (CYGARC_REG_EMI_BASE+0x0c) +#define CYGARC_REG_EMI_SCR (CYGARC_REG_EMI_BASE+0x14) +#define CYGARC_REG_EMI_STR (CYGARC_REG_EMI_BASE+0x1c) +#define CYGARC_REG_EMI_COC (CYGARC_REG_EMI_BASE+0x24) +#define CYGARC_REG_EMI_SDRA0 (CYGARC_REG_EMI_BASE+0x3c) +#define CYGARC_REG_EMI_SDRA1 (CYGARC_REG_EMI_BASE+0x34) +#define CYGARC_REG_EMI_SDMR0 (CYGARC_REG_EMI_BASE+0x100000) +#define CYGARC_REG_EMI_SDMR1 (CYGARC_REG_EMI_BASE+0x200000) + +#define CYGARC_REG_EMI_VCR_L_ID 0x0000FFFF +#define CYGARC_REG_EMI_VCR_L_BOT_MB 0x00FF0000 +#define CYGARC_REG_EMI_VCR_L_TOP_MB 0xFF000000 + +#define CYGARC_REG_EMI_VCR_H_PERR 0x000000FF +#define CYGARC_REG_EMI_VCR_H_MERR 0x0000FF00 +#define CYGARC_REG_EMI_VCR_H_VERS 0xFFFF0000 + +#define CYGARC_REG_EMI_MIM_DCR 0x00000001 +#define CYGARC_REG_EMI_MIM_DT 0x00000002 +#define CYGARC_REG_EMI_MIM_BW 0x000000c0 +#define CYGARC_REG_EMI_MIM_ENDIAN 0x00000100 +#define CYGARC_REG_EMI_MIM_DRE 0x00000200 +#define CYGARC_REG_EMI_MIM_DIMM 0x00000400 +#define CYGARC_REG_EMI_MIM_BY32AP 0x00000800 +#define CYGARC_REG_EMI_MIM_DRI 0x0fff0000 + +#define CYGARC_REG_EMI_SCR_SMS 0x00000007 +#define CYGARC_REG_EMI_SCR_BRFSH 0x00000070 + +#define CYGARC_REG_EMI_STR_SRP 0x00000001 +#define CYGARC_REG_EMI_STR_SRCD 0x00000002 +#define CYGARC_REG_EMI_STR_SCL 0x0000001c +#define CYGARC_REG_EMI_STR_SRC 0x000000e0 +#define CYGARC_REG_EMI_STR_SRAS 0x00000700 +#define CYGARC_REG_EMI_STR_SRRD 0x00000800 +#define CYGARC_REG_EMI_STR_SDPL 0x00001000 + +#define CYGARC_REG_EMI_COC_LOCK 0x00000001 + +#define CYGARC_REG_EMI_SDRA_SPLIT 0x00000f00 +#define CYGARC_REG_EMI_SDRA_BANK 0x00001000 +#define CYGARC_REG_EMI_SDRA_UBA 0xffe00000 + + +// end of mod_regs_emi.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4/current/include/mod_regs_femi.h @@ -0,0 +1,89 @@ +//============================================================================= +// +// mod_regs_femi.h +// +// FEMI (FLASH External Memory Interface) Module register definitions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting the copyright +// holder. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 2003-08-20 +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- + +#define CYGARC_REG_FEMI_BASE 0xFF800000 +#define CYGARC_REG_FEMI_VCR_L (CYGARC_REG_FEMI_BASE+0x00) +#define CYGARC_REG_FEMI_VCR_H (CYGARC_REG_FEMI_BASE+0x04) +#define CYGARC_REG_FEMI_MDCR (CYGARC_REG_FEMI_BASE+0x0c) +#define CYGARC_REG_FEMI_A0MCR (CYGARC_REG_FEMI_BASE+0x14) +#define CYGARC_REG_FEMI_A1MCR (CYGARC_REG_FEMI_BASE+0x1c) +#define CYGARC_REG_FEMI_A2MCR (CYGARC_REG_FEMI_BASE+0x24) +#define CYGARC_REG_FEMI_A3MCR (CYGARC_REG_FEMI_BASE+0x2c) +#define CYGARC_REG_FEMI_A4MCR (CYGARC_REG_FEMI_BASE+0x34) + +#define CYGARC_REG_FEMI_VCR_L_ID 0x0000FFFF +#define CYGARC_REG_FEMI_VCR_L_BOT_MB 0x00FF0000 +#define CYGARC_REG_FEMI_VCR_L_TOP_MB 0xFF000000 + +#define CYGARC_REG_FEMI_VCR_H_PERR 0x000000FF +#define CYGARC_REG_FEMI_VCR_H_MERR 0x0000FF00 +#define CYGARC_REG_FEMI_VCR_H_VERS 0xFFFF0000 + +#define CYGARC_REG_FEMI_MDCR_HIZMEM 0x00000001 +#define CYGARC_REG_FEMI_MDCR_BREQEN 0x00000002 +#define CYGARC_REG_FEMI_MDCR_ENDIAN 0x00000004 +#define CYGARC_REG_FEMI_MDCR_MERGE 0x00000008 + +#define CYGARC_REG_FEMI_ANMCR_TYPE 0x00000007 +#define CYGARC_REG_FEMI_ANMCR_SZ 0x00000018 +#define CYGARC_REG_FEMI_ANMCR_BST 0x000000e0 +#define CYGARC_REG_FEMI_ANMCR_FLMD 0x00000100 +#define CYGARC_REG_FEMI_ANMCR_FLWP 0x00000200 +#define CYGARC_REG_FEMI_ANMCR_MBC 0x00000400 +#define CYGARC_REG_FEMI_ANMCR_IW 0x00007000 +#define CYGARC_REG_FEMI_ANMCR_BP 0x00070000 +#define CYGARC_REG_FEMI_ANMCR_WS 0x00700000 +#define CYGARC_REG_FEMI_ANMCR_HLD 0x03000000 +#define CYGARC_REG_FEMI_ANMCR_STUP 0x08000000 + +// end of mod_regs_femi.h +
--- a/packages/hal/sh/sh4/current/include/mod_regs_intc.h +++ b/packages/hal/sh/sh4/current/include/mod_regs_intc.h @@ -9,6 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -41,7 +42,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov +// Contributors:jskov, nickg // Date: 2000-10-30 // //####DESCRIPTIONEND#### @@ -50,6 +51,8 @@ //-------------------------------------------------------------------------- // Interrupt registers, module type 1 + +#define CYGARC_REG_TRA 0xFF000020 #define CYGARC_REG_EXCEVT 0xFF000024 #define CYGARC_REG_INTEVT 0xFF000028
--- a/packages/hal/sh/sh4/current/include/mod_regs_ser.h +++ b/packages/hal/sh/sh4/current/include/mod_regs_ser.h @@ -127,9 +127,7 @@ (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \ (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3) #define CYGARC_SCBRR_N(_b_) \ - (((_b_) < 4800) ? 0 : \ - ((_b_) > 115200) ? 0 : \ - (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED+CYGARC_SCBRR_ROUNDING(_b_))/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1)) + (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED+CYGARC_SCBRR_ROUNDING(_b_))/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1) //++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++ #ifdef CYGARC_SH_MOD_SCIF @@ -225,4 +223,7 @@ #define CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK 0x1f00 // number of chars in t fifo #define CYGARC_REG_SCIF_SCFDR_TCOUNT_shift 8 +// Serial line status register +#define CYGARC_REG_SCIF_SCLSR_ORER 0x01 // overrun error + #endif // CYGARC_SH_MOD_SCIF
--- a/packages/hal/sh/sh4/current/include/sh4_scif.h +++ b/packages/hal/sh/sh4/current/include/sh4_scif.h @@ -85,6 +85,7 @@ typedef struct { cyg_uint8* base; cyg_int32 msec_timeout; int isr_vector; + cyg_uint32 baud_rate; } channel_data_t; //--------------------------------------------------------------------------
--- a/packages/hal/sh/sh4/current/include/var_regs.h +++ b/packages/hal/sh/sh4/current/include/var_regs.h @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:Ryozaburo Suzuki +// Contributors:Ryozaburo Suzuki, nickg // Date: 2000-04-18 // Purpose: Define CPU memory mapped registers etc. // Usage: Included via the acrhitecture register header: @@ -83,6 +84,11 @@ #define CYGARC_REG_SR_T 0x00000001 #define CYGARC_REG_SR_FD 0x00008000 +//-------------------------------------------------------------------------- +// FPSCR register initial value + +#define CYG_FPSCR 0x000C0000 + //========================================================================== // Module Definitions //========================================================================== @@ -97,6 +103,11 @@ #include <cyg/hal/mod_regs_tmu.h> #include <cyg/hal/mod_regs_ubc.h> +#ifdef CYGPKG_HAL_SH_202 +#include <cyg/hal/mod_regs_femi.h> +#include <cyg/hal/mod_regs_emi.h> +#endif + #ifdef CYGARC_SH_MOD_PCIC #include <cyg/hal/mod_regs_pcic.h> #endif
--- a/packages/hal/sh/sh4/current/include/variant.inc +++ b/packages/hal/sh/sh4/current/include/variant.inc @@ -11,6 +11,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ #######DESCRIPTIONBEGIN#### ## ## Author(s): jskov -## Contributors:jskov +## Contributors:jskov, nickg ## Date: 2000-10-30 ## Purpose: SH4 variant definitions and init code ## Description: This file contains various definitions and macros that are @@ -77,15 +78,33 @@ #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) ##----------------------------------------------------------------------------- +## Cache control register initialization +## +## If we are starting from ROM, or are a RAM resident monitor, disable the cache +## initially. Otherwise we are a RAM loaded application, so keep the cache +## enabled. + +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) +#define CYGARC_REG_CCR_INIT CYGARC_REG_CCR_EMODE +#else +#define CYGARC_REG_CCR_INIT (CYGARC_REG_CCR_CE|CYGARC_REG_CCR_EMODE) +#endif + +##----------------------------------------------------------------------------- ## Hardware init macros #ifndef CYGPKG_HAL_SH_POST_RESET_INIT .macro hal_post_reset_init # Initialize CPU mov.l $nCYG_SR,r1 ! Put CPU in a well-known state ldc r1,sr - mov #0,r0 + mov.l $nCYG_FPSCR,r1 + lds r1,fpscr + mov.l $nCYGARC_REG_CCR_INIT,r0 mov.l $nCYGARC_REG_CCR,r1 ! Disable cache mov.l r0,@r1 + mov #0,r0 mov.l $nCYGARC_REG_MMUCR,r1 ! Disable MMU mov.l r0,@r1 mov.l $nCYGARC_REG_BBRA,r1 ! Disable UBC Channel A @@ -129,8 +148,12 @@ .align 2 $nCYG_SR: .long CYG_SR +$nCYG_FPSCR: + .long CYG_FPSCR $nCYGARC_REG_CCR: .long CYGARC_REG_CCR +$nCYGARC_REG_CCR_INIT: + .long CYGARC_REG_CCR_INIT $nCYGARC_REG_MMUCR: .long CYGARC_REG_MMUCR $nCYGARC_REG_BBRA:
--- a/packages/hal/sh/sh4/current/src/sh4_scif.c +++ b/packages/hal/sh/sh4/current/src/sh4_scif.c @@ -70,11 +70,29 @@ //-------------------------------------------------------------------------- +static void +cyg_hal_plf_scif_set_baud(cyg_uint8 *base, cyg_uint32 baud) +{ + cyg_uint16 tmp; + + // Set desired baudrate + HAL_READ_UINT16(base+_REG_SCSMR, tmp); + tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK; + tmp |= CYGARC_SCBRR_CKSx(baud); + HAL_WRITE_UINT16(base+_REG_SCSMR, tmp); + HAL_WRITE_UINT8(base+_REG_SCBRR, + CYGARC_SCBRR_N(baud)); + + // Let things settle: Here we should wait the equivalent of + // one bit interval, i.e. 1/<baudrate> second, but we'll wait twice + // that to be sure. + CYGACC_CALL_IF_DELAY_US(2000000/baud); +} + void cyg_hal_plf_scif_init_channel(channel_data_t* chan) { cyg_uint8* base = chan->base; - cyg_uint16 tmp; cyg_uint16 sr; // Disable everything. @@ -87,19 +105,8 @@ cyg_hal_plf_scif_init_channel(channel_da // 8-1-no parity. HAL_WRITE_UINT16(base+_REG_SCSMR, 0); - // Set desired baudrate - HAL_READ_UINT16(base+_REG_SCSMR, tmp); - tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK; - tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE); - HAL_WRITE_UINT16(base+_REG_SCSMR, tmp); - HAL_WRITE_UINT8(base+_REG_SCBRR, - CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE)); - - // Let things settle: Here we should should wait the equivalent of - // one bit interval, i.e. 1/<baudrate> second, but until we have - // something like the Linux delay loop, it's hard to do reliably. So - // just move on and hope for the best (this is unlikely to cause - // problems since the CPU has just come out of reset anyway). + chan->baud_rate = CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE; + cyg_hal_plf_scif_set_baud(base, CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE); // Clear status register (read back first). HAL_READ_UINT16(base+_REG_SCFSR, sr); @@ -259,7 +266,24 @@ cyg_hal_plf_scif_control(void *__ch_data chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); - } + } + break; + case __COMMCTL_SETBAUD: + { + cyg_uint8* base = chan->base; + va_list ap; + + va_start(ap, __func); + chan->baud_rate = va_arg(ap, cyg_uint32); + va_end(ap); + + // Set desired baudrate + cyg_hal_plf_scif_set_baud(base, chan->baud_rate); + } + break; + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; default: break; }
--- a/packages/hal/sh/sh4/current/src/var_misc.c +++ b/packages/hal/sh/sh4/current/src/var_misc.c @@ -101,6 +101,12 @@ cyg_var_enable_caches(void) void hal_variant_init(void) { +#ifdef CYGHWR_HAL_SH_FPU + __externC void __set_fpscr(cyg_uint32 __fpscr); + // Call __set_fpscr to allow GCC (in libgcc) to update its internal + // state for the floating point mode. + __set_fpscr(CYG_FPSCR); +#endif } //---------------------------------------------------------------------------