Mercurial > flash_v2
changeset 1425:df8a81496fba
* New platform HAL for SuperH SH4-202 MicroDev CPU board.
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new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/ChangeLog @@ -0,0 +1,107 @@ +2003-10-16 John Dallaway <jld@ecoscentric.com> + + * misc/sh4_202_md.ld: Place .stack at 0x88200000 by default. + +2003-10-15 Nick Garnett <nickg@ecoscentric.com> + + * include/plf_intr.h: Moved address of FPGA_INTC_BASE from + 0x06110000 to 0xA6110000. This moves it from cached to uncached + space and fixes some networking problems. + +2003-09-21 John Dallaway <jld@ecoscentric.com> + + * doc/sh4_202_md.sgml: Minor tidy up. + +2003-09-21 Jonathan Larmour <jifl@eCosCentric.com> + + * doc/sh4_202_md.sgml: Document FPSCR change caveats. + +2003-09-18 John Dallaway <jld@ecoscentric.com> + + * doc/sh4_202_md.sgml: Fix typo and name of DIP bank 2 switch 2. + +2003-09-17 Jonathan Larmour <jifl@eCosCentric.com> + + * misc/redboot_EEPROM.ecm: New file to support building for the EEPROM + (same as ROM but no flash driver). + + * doc/sh4_202_md.sgml: Comment out mentions of -fomit-stack-pointer + as it doesn't apply any more. + Document use of EEPROM boot for RedBoot. + + * cdl/hal_sh_sh4_202_md.cdl (CYGBLD_BUILD_REDBOOT_BIN): don't + build redboot.eprom.srec - hangover from different target. + + * include/platform.inc (init_table): Rely on FPGA to set up FEMI + area 0. + +2003-09-16 Jonathan Larmour <jifl@ecoscentric.com> + + * include/plf_intr.h (CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF): + Recognise level specific interrupts. + * include/pkgconf/mlt_sh_sh4_202_md_rom.mlt: Delete. Invalid. + * include/pkgconf/mlt_sh_sh4_202_md_ram.mlt: Delete. Invalid. + * include/pkgconf/mlt_sh_sh4_202_md_rom.ldi: Add .eh_frame support. + * include/pkgconf/mlt_sh_sh4_202_md_ram.ldi: Ditto. + +2003-09-15 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_sh_sh4_202_md.cdl: Big-endian operation not supported. + +2003-09-12 John Dallaway <jld@ecoscentric.com> + + * doc/sh4_202_md.sgml: Minor tidy of platform documentation. + +2003-09-11 Nick Garnett <nickg@ecoscentric.com> + + * src/plf_misc.c (hal_platform_init): Removed intEnableReg to + quash build warning. + +2003-09-10 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_sh_sh4_202_md.cdl: Added definition of + HAL_PLATFORM_CPU. Cleaned up comments. + +2003-09-09 Nick Garnett <nickg@ecoscentric.com> + + * doc/sh4_202_md.sgml: Added initial version of platform + documentation. + +2003-09-05 Nick Garnett <nickg@ecoscentric.com> + + * New platform HAL for SuperH SH4-202 MicroDev CPU board. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/cdl/hal_sh_sh4_202_md.cdl @@ -0,0 +1,390 @@ +# ==================================================================== +# +# hal_sh_sh4_202_md.cdl +# +# SuperH SH4-202 MicroDev CPU board configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): nickg +# Original data: jskov +# Contributors: +# Date: 2003-08-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SH_SH4_202_MD { + display "SuperH SH4-202 MicroDev CPU Board" + parent CYGPKG_HAL_SH + requires CYGPKG_HAL_SH_202 + requires CYGHWR_HAL_SH_IRQ_USE_IRQLVL + requires ! CYGHWR_HAL_SH_BIGENDIAN + define_header hal_sh_sh4_202_md.h + include_dir cyg/hal + description " + The SH4-202-MD HAL package provides the support needed to run + eCos on a SuperH SH4-202 MicroDev CPU board." + + compile hal_diag.c plf_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh4_202_md.h>" + + puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1" + puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x88000000" + puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x88000100" + + puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH4-202\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MicroDev CPU Board\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The MicroDev board has one serial port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The MicroDev board has one serial port which is used as both + the diagnostic and console channel." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD { + display "Console/GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option controls the default baud rate used for the + Console/GDB connection." + } + + cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS { + display "SH on-chip platform clock controls" + description " + The various clocks used by the system are derived from + these options." + flavor none + no_define + + cdl_option CYGHWR_HAL_SH_OOC_XTAL { + display "SH clock crystal" + flavor data + legal_values 8000000 to 50000000 + default_value 33000000 + no_define + description " + This option specifies the frequency of the crystal all + other clocks are derived from." + } + + cdl_option CYGHWR_HAL_SH_OOC_CKIO { + display "SH clock CKIO output enable" + default_value 1 + description " + This selects whether CKIO output is enabled." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_1 { + display "SH clock PLL circuit 1" + flavor data + default_value 8 + legal_values { 0 4 6 8 } + description " + This selects the multiplication factor provided by + PLL1." + } + + cdl_option CYGHWR_HAL_SH_OOC_PLL_2 { + display "SH clock PLL circuit 2" + flavor data + default_value 1 + legal_values { 0 1 } + description " + This selects the multiplication factor provided by + PLL2. If PLL2 is disabled this option should + be set to zero." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 { + display "SH clock divider 1" + flavor data + default_value 1 + legal_values { 1 2 } + description " + This divider option affects all clocks." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC { + display "SH CPU clock divider" + flavor data + default_value 1 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the CPU clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC { + display "SH bus clock divider" + flavor data + default_value 2 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the bus clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC { + display "SH peripheral clock divider" + flavor data + default_value 4 + legal_values { 1 2 3 4 6 8 } + description " + This divider option affects the peripheral clock." + } + + cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE { + display "SH clock mode" + flavor data + default_value 3 + legal_values { 0 1 2 3 4 5 } + description " + This option must mirror the clock mode hardwired on + the MD0-MD2 pins of the CPU in order to correctly + initialize the FRQCR register." + } + } + + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" } + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the MicroDev board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. + RAM bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap typically + requires that the eCos application be blown into flash ROM or + equivalent technology." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "sh-elf" } +# default_value { "sh-superh-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m4 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m4 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh4_202_md_ram" : \ + "sh_sh4_202_md_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh4_202_md_ram.ldi>" : \ + "<pkgconf/mlt_sh_sh4_202_md_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh4_202_md_ram.h>" : \ + "<pkgconf/mlt_sh_sh4_202_md_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + parent CYGPKG_HAL_ROM_MONITOR + description " + Support can be enabled for boot ROMs or ROM monitors which contain + GDB stubs. This support changes various eCos semantics such as + the encoding of diagnostic output, and the overriding of hardware + interrupt vectors." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/doc/sh4_202_md.sgml @@ -0,0 +1,760 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- sh4_202_md.sgml --> +<!-- --> +<!-- MicroDev platform HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####COPYRIGHTBEGIN#### --> +<!-- --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003 Nick Garnett . --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- --> +<!-- ####COPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): nickg --> +<!-- Contact(s): nickg --> +<!-- Date: 2003/09/08 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-sh4-microdev-part"><title>SuperH SH4-202 MicroDev Board Support</title> + +<!-- {{{ Overview --> + +<refentry id="sh4-microdev"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>eCos Support for the SuperH SH4-202 MicroDev Board</refname> + <refpurpose>Overview</refpurpose> + </refnamediv> + + <refsect1 id="sh4-microdev-description"><title>Description</title> + <para> +The SuperH SH4-202 MicroDev board (henceforth just "MicroDev") has +an SH4-202 processor, 64MB of external SDRAM, 32MB of external flash +memory, an SMSC LAN91C111 ethernet controller and connectors plus +required support chips for all the on-chip peripherals. + </para> + <para> +For typical eCos development, a RedBoot image is programmed into the +flash memory, and the board will boot this image from reset. RedBoot +provides gdb stub functionality so it is then possible to download and +debug stand-alone and eCos applications via the gdb debugger. This can +happen over either a serial line or over ethernet. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-hardware"><title>Supported Hardware</title> + <para> +The flash memory consists of 128 blocks of 256k bytes each. +In a typical setup, the first +flash block is used for the ROM RedBoot image +and the second is used to store a version of RedBoot that can run out of +RAM. The topmost two blocks are used to manage the flash and hold RedBoot fconfig +values. The remaining 124 blocks between 0xA0080000 and 0xA1F7FFFF can be +used by application code. + </para> + <para> +The board is fitted with a PLCC socket suitable for an EEPROM (or PROM) such as +the 1Mbit ST M29WO10B. This is enabled by toggling two DIP switches, after which +the EEPROM is mapped into the same address as the flash memory. Therefore, +the flash is not accessible if booting from the EEPROM. + </para> + <para> +There is a serial driver <varname>CYGPKG_DEVS_SERIAL_SH_SCIF</varname> +which supports the on-chip serial device. This device +can be used by RedBoot for communication with the host. If this device +is needed by the application, either directly or via the serial +driver, then it cannot also be used for RedBoot communication. Another +communication channel such as ethernet should be used instead. The +serial driver package is loaded automatically when configuring for the +MicroDev target. + </para> + <para> +There is an ethernet driver <varname>CYGPKG_DEVS_ETH_SH_MICRODEV</varname> +for the on-chip ethernet device. This driver is also loaded +automatically when configuring for the MicroDev target. + </para> + <para> +eCos manages the on-chip interrupt controller. Timer 0 is used to +implement the eCos system clock, and timer 1 is used to implement a +microsecond delay function. Timer 2 is unused and +left for the application. Other on-chip devices (FEMI, EMI, INTC, TMU, +CAC, UBC) are initialized only as far as is necessary for eCos to +run. Other devices (eg RTC, DMAC, etc) are not touched. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-tools"><title>Tools</title> + <para> +The MicroDev port is intended to work with GNU tools configured for an +sh-elf target. The original port was done using sh-elf-gcc version +3.2.1, sh-elf-gdb version 5.3, and binutils version 2.13.1. + </para> +<!-- DOES THIS APPLY? + <para> +By default, eCos is built using the compiler flag +<option>-fomit-frame-pointer</option>. Omitting the frame pointer +eliminates some work on every function call and makes another register +available, so the code should be smaller and faster. However, without a +frame pointer, sh-elf-gdb is not always able to identify stack +frames, so it may be unable to provide accurate backtrace information. +Removing this compiler flag from the configuration option +<varname>CYGBLD_GLOBAL_CFLAGS</varname> avoids such debug problems. + </para> +--> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Hardware setup --> + +<refentry id="sh4-microdev-setup"> + <refmeta> + <refentrytitle>Setup</refentrytitle> + </refmeta> + <refnamediv> + <refname>Setup</refname> + <refpurpose>Preparing the MicroDev board for eCos Development</refpurpose> + </refnamediv> + + <refsect1 id="sh4-microdev-setup-overview"><title>Overview</title> + <para> +In a typical development environment, the MicroDev board boots from +flash into the RedBoot ROM monitor. eCos applications are configured +for RAM startup and then downloaded and run on the board via the +debugger sh-elf-gdb. Preparing the board therefore usually involves +programming a suitable RedBoot image into flash memory. Alternatively +RedBoot may be programmed into a PLCC EEPROM and inserted into socket U21, +although in that case, the flash memory is not accessible. + </para> + <para> +The following RedBoot configurations are supported: + </para> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Description</entry> + <entry>Use</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>RedBoot running from the board's flash</entry> + <entry>redboot_ROM.ecm</entry> + <entry>redboot_ROM.bin</entry> + </row> + <row> + <entry>EEPROM</entry> + <entry>RedBoot running from the board's socketed EEPROM</entry> + <entry>redboot_EEPROM.ecm</entry> + <entry>redboot_EEPROM.bin</entry> + </row> + <row> + <entry>RAM</entry> + <entry>Used for upgrading ROM version</entry> + <entry>redboot_RAM.ecm</entry> + <entry>redboot_RAM.bin</entry> + </row> + </tbody> + </tgroup> + </informaltable> + <para> +For serial communications, all versions run with 8 bits, no parity, and +1 stop bit at 38400 baud. This baud rate can be changed via the +configuration option +<varname>CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE</varname> and rebuilding +RedBoot. RedBoot also supports ethernet communication and flash +management. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-setup-first"><title>Initial Installation</title> + <refsect2 id="sh4-microdev-flash"><title>Flash Installation</title> + <para> +This process assumes that the board is connected to a SuperH Micro +Probe. The Micro Probe should be set up as described in Appendix A of +the "SH4 Development Tools User Guide". You should also have access to +the SuperH development tools since it is necessary to use the version +of GDB that comes with those tools to access the Micro Probe, +<command>sh-elf-gdb</command> will not work. + </para> + <para> +Programming the RedBoot ROM monitor into flash memory requires an +application that can manage flash blocks. RedBoot itself has this +capability. Rather than have a separate application that is used only +for flash management during the initial installation, a special +RAM-resident version of RedBoot is loaded into memory and run. This +version can then be used to load the normal flash-resident version of +RedBoot and program it into the flash. + </para> + <para> +The first step is to connect an RS232 null modem cable between the MicroDev +serial port and the host PC. Next start a terminal emulation application such as +HyperTerminal or minicom on the host PC and set the serial +communication parameters to 38400 baud, 8 data bits, no parity, 1 stop +bit (8N1) and no flow control (handshaking). + </para> + <para> +Now run the <command>sh4gdb</command> command, giving it the name of +the RAM redboot ELF file, connect to the Micro Probe, load the +executable and run it. The entire session should look like this: + </para> + <screen> +$ <userinput>sh4gdb redboot_RAM.elf</userinput> +GNU gdb 5.2.1 +Copyright 2002 Free Software Foundation, Inc. +GDB is free software, covered by the GNU General Public License, and you are +welcome to change it and/or distribute copies of it under certain conditions. +Type "show copying" to see the conditions. +There is absolutely no warranty for GDB. Type "show warranty" for details. +This GDB was configured as "--host=i686-pc-linux-gnu --target=sh-superh-elf"... +(gdb) <userinput>sh4si superh</userinput> +The target is assumed to be little endian +The target architecture is assumed to be sh4 +0xa0000000 in ?? () +(gdb) <userinput>load</userinput> +Loading section .vectors, size 0x9e0 lma 0x88010000 +Loading section .text, size 0x1ab20 lma 0x880109e0 +Loading section .rodata, size 0x3e6c lma 0x8802b500 +Loading section .data, size 0xf30 lma 0x8802f370 +Start address 0x88010000, load size 131740 +Transfer rate: 351306 bits/sec, 433 bytes/write. +(gdb) <userinput>cont</userinput> +Continuing. + </screen> + <para> +The required <filename>redboot_RAM.elf</filename> file is normally +supplied with the eCos release in the <filename +class="directory">loaders</filename> directory. If it needs to be +rebuilt then instructions for this are supplied <link +linkend="sh4-microdev-setup-rebuild">below</link>. + </para> + <para> +If this sequence fails in any way then check the setup and connections +of the Micro Probe. It if is successful then you should see the +following printed out on the serial line: + </para> + <screen> ++FLASH configuration checksum error or invalid key +... waiting for BOOTP information +Ethernet eth0: MAC address 00:08:ee:00:0b:37 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [RAM] +Non-certified release, version UNKNOWN - built 14:28:55, Sep 8 2003 + +Copyright (C) 2000, 2001, 2002, Red Hat, Inc. + +RAM: 0x88000000-0x8c000000, 0x8812cca0-0x8bfb1000 available +FLASH: 0xa0000000 - 0xa2000000, 128 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +If the ethernet cable is not plugged in there may be a fairly long +wait after the "... waiting for BOOTP information" message. +At this stage the RedBoot flash management initialization has not yet +happened so the warning about the configuration checksum error is +expected. To perform this initialization use the +<command>fis init -f</command> command: + </para> + <screen> +RedBoot> <userinput>fis init -f</userinput> +About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> +*** Initialize FLASH Image System +... Unlock from 0xa1fc0000-0xa2000000: . +... Erase from 0xa1fc0000-0xa2000000: . +... Program from 0x8bfbf000-0x8bfff000 at 0xa1fc0000: . +... Lock from 0xa1fc0000-0xa2000000: . +RedBoot> + </screen> + <para> +At the end, the block of flash at +location 0xA1FC0000 holds information about the various flash blocks, +allowing other flash management operations to be performed. The next +step is to set up RedBoot's non-volatile configuration values: + </para> + <screen> +RedBoot> <userinput>fconfig -i</userinput> +Initialize non-volatile configuration - continue (y/n)? <userinput>y</userinput> +Run script at boot: false +Use BOOTP for network configuration: true +Console baud rate: 38400 +DNS server IP address: +Set eth0 network hardware address [MAC]: false +GDB connection port: 9000 +Force console for special debug messages: false +Network debug at boot time: false +Update RedBoot non-volatile configuration - continue (y/n)? <userinput>y</userinput> +... Unlock from 0xa1f80000-0xa1f81000: . +... Erase from 0xa1f80000-0xa1f81000: . +... Program from 0x8bfb2000-0x8bfb3000 at 0xa1f80000: . +... Lock from 0xa1f80000-0xa1f81000: . +RedBoot> + </screen> + <para> +For most of these configuration variables, the default value is +correct. If there is no suitable BOOTP service running on the local +network then BOOTP should be disabled and, instead, RedBoot will prompt +for a fixed IP address, netmask, and addresses for the local gateway +and DNS server. + </para> + <para> +It is now possible to load the flash-resident version of RedBoot. +Because of the way that flash chips work, it is better to first load it +into RAM and then program it into flash. + </para> + <screen> +RedBoot> <userinput>load -r -m xmodem -b %{freememlo}</userinput> + </screen> + <para> +The file <filename>redboot_ROM.bin</filename> should now be uploaded +using the terminal emulator. The file is a raw binary and should be +transferred using the X-modem protocol. + </para> + <screen> +Raw file loaded 0x8812d000-0x8814e32f, assumed entry at 0x8812d000 +xyzModem - CRC mode, 1064(SOH)/0(STX)/0(CAN) packets, 2 retries +RedBoot> + </screen> + <para> +Once RedBoot has been loaded into RAM it can be programmed into flash: + </para> + <screen> +RedBoot> <userinput>fis create RedBoot -b %{freememlo}</userinput> +An image named 'RedBoot' exists - continue (y/n)? <userinput>y</userinput> +... Erase from 0xa0000000-0xa0040000: . +... Program from 0x8812d000-0x8816d000 at 0xa0000000: . +... Unlock from 0xa1fc0000-0xa2000000: . +... Erase from 0xa1fc0000-0xa2000000: . +... Program from 0x8bfbf000-0x8bfff000 at 0xa1fc0000: . +... Lock from 0xa1fc0000-0xa2000000: . +RedBoot> + </screen> + <para> +The flash-resident version of RedBoot has now been programmed at location +0xA0000000, and the flash info block at 0xA1FC0000 has been updated. +The initial setup is now complete. Power off the Micro Probe and reset +the MicroDev board using S6. You should see the following: + + </para> + <screen> ++... waiting for BOOTP information +Ethernet eth0: MAC address 00:08:ee:00:0b:37 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [ROM] +Non-certified release, version UNKNOWN - built 14:22:57, Sep 8 2003 + +Copyright (C) 2000, 2001, 2002, Red Hat, Inc. + +RAM: 0x88000000-0x8c000000, 0x8800db98-0x8bfb1000 available +FLASH: 0xa0000000 - 0xa2000000, 128 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +When RedBoot issues its prompt, it is also ready to accept connections +from sh-elf-gdb, allowing applications to be downloaded and +debugged. + </para> + <para> +Occasionally it may prove necessary to update the installed RedBoot +image. This can be done simply by repeating the above process, using +the Micro Probe. Alternatively, the existing +RedBoot install can be used to load the RAM-resident version. You can +even install the RAM resident RedBoot in the "RedBoot[backup]" flash +region. See the RedBoot documentation for instruction on how to do this. + </para> + </refsect2> + <refsect2 id="sh4-microdev-eeprom"><title>EEPROM Installation</title> + <para> +The board has a 32-pin PLCC socket suitable for an EEPROM, silk screened U21. +To use RedBoot running from EEPROM, you must first program the file +<filename>redboot_EEPROM.bin</filename> (normally supplied with the eCos release +in the <filename class="directory">loaders</filename> directory) into the +EEPROM using an appropriate programmer. No byte swapping is required. If RedBoot +needs to be rebuilt, then instructions for this are supplied <link +linkend="sh4-microdev-setup-rebuild">below</link>, and the import file +<filename>redboot_EEPROM.ecm</filename> should be used. + </para> + <para> +To configure the board to boot from the EEPROM instead of flash, you must +power off the board and change the following DIP switch settings, which may +both be found on DIP switch 2 (silk screened S2): switch 2 (silk +screened FEMI SIZ1) should be set to ON, which will change the access +width for FEMI area 0 from 32-bit to 8-bit; switch 6 (silk screened +FPGA SW3) should be set to OFF to configure the FPGA to map memory +accesses for FEMI area 0 to point at the EEPROM instead of flash. In +this mode, it is no longer possible to access flash memory as the EEPROM +is mapped into the same area in the address space. + </para> + <para> +Note that it is usually preferable to boot from flash instead of EEPROM as +flash is accessed 32-bits at a time, whereas the EEPROM is accessed 8-bits +at a time, which therefore affects performance as this requires 4 times as +many read cycles. + </para> + </refsect2> + </refsect1> + + <refsect1 id="sh4-microdev-setup-rebuild"><title>Rebuilding RedBoot</title> + <para> +Should it prove necessary to rebuild a RedBoot binary, this is done +most conveniently at the command line. The steps needed to rebuild the +RAM version of RedBoot are: + </para> + <screen> +$ mkdir redboot_ram +$ cd redboot_ram +$ ecosconfig new sh4_202_md redboot +$ ecosconfig import $ECOS_REPOSITORY/hal/sh/sh4_202_md/v2_0_2/misc/redboot_RAM.ecm +$ ecosconfig resolve +$ ecosconfig tree +$ make + </screen> + <para> +At the end of the build the <filename +class="directory">install/bin</filename> subdirectory should contain +the file <filename>redboot.bin</filename>. + </para> + <para> +Rebuilding the ROM versions involves basically the same +process. The ROM version uses the file +<filename>redboot_ROM.ecm</filename> and generates a file +<filename>redboot.bin</filename>. Make sure you don't mix up the +different redboot.bin files; rename them to something more memorable +such as <filename>redboot_RAM.bin</filename> and +<filename>redboot_ROM.bin</filename>. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Config --> + +<refentry id="sh4-microdev-config"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Configuration</refname> + <refpurpose>Platform-specific Configuration Options</refpurpose> + </refnamediv> + + <refsect1 id="sh4-microdev-config-overview"><title>Overview</title> + <para> +The MicroDev platform HAL package is loaded automatically when eCos is +configured for an <literal>sh4_202_md</literal> target. It should +never be necessary to load this package explicitly. Unloading the +package should only happen as a side effect of switching target +hardware. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-config-startup"><title>Startup</title> + <para> +The MicroDev platform HAL package supports two separate startup types: + </para> + <variablelist> + <varlistentry> + <term>RAM</term> + <listitem><para> +This is the startup type which is normally used during application +development. The board has RedBoot programmed into flash at location +0xA0000000 and boots from that location. +<application>sh-elf-gdb</application> is then used to load a RAM +startup application into memory and debug it. It is assumed that the +hardware has already been initialized by RedBoot. By default the +application will use the eCos virtual vectors mechanism to obtain certain +services from RedBoot, including diagnostic output. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROM</term> + <listitem><para> +This startup type can be used for finished applications which will +be programmed into flash at location 0xA0000000. The application will +be self-contained with no dependencies on services provided by other +software. eCos startup code will perform all necessary hardware +initialization. + </para></listitem> + </varlistentry> + </variablelist> + + </refsect1> + + <refsect1 id="sh4-microdev-config-redboot"><title>RedBoot and Virtual Vectors</title> + <para> +If the application is intended to act as a ROM monitor, providing +services for other applications, then the configuration option +<varname>CYGSEM_HAL_ROM_MONITOR</varname> should be set. Typically +this option is set only when building RedBoot. + </para> + <para> +If the application is supposed to make use of services provided by a +ROM monitor, via the eCos virtual vector mechanism, then the +configuration option <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> +should be set. By default this option is enabled when building for a +RAM startup, disabled otherwise. It can be manually disabled for a RAM +startup, making the application self-contained, as a testing step +before switching to ROM startup. + </para> + <para> +If the application does not rely on a ROM monitor for diagnostic +services then the serial port will be claimed for HAL +diagnostics. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-config-flash"><title>Flash Driver</title> + <para> +The MicroDev board contains 32Mb of Intel StrataFlash, specifically, +two E28F128 parts in parallel. The +<varname>CYGPKG_DEVS_FLASH_STRATA</varname> package contains all the +code necessary to support these parts and the +<varname>CYGPKG_DEVS_FLASH_SH_MICRODEV</varname> package contains +definitions that customize the driver to the MicroDev board. + </para> + <para> +Note that if booting from EEPROM instead of flash, the flash driver will +not be able to detect or use the flash parts. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-config-eth"><title>Ethernet Driver</title> + <para> +The MicroDev board contains an SMSC LAN91C111 ethernet device. +The +<varname>CYGPKG_DEVS_ETH_SMSC_LAN91CXX</varname> package contains all the +code necessary to support this part and the +<varname>CYGPKG_DEVS_ETH_SH_MICRODEV</varname> package contains +definitions that customize the driver to the MicroDev board. + </para> + </refsect1> + + + <refsect1 id="sh4-microdev-config-clock"><title>System Clock</title> + <para> +By default, the system clock interrupts once every 10ms, corresponding +to a 100Hz clock. This can be changed by the configuration option +<varname>CYGNUM_HAL_RTC_DENOMINATOR</varname> which corresponds to the +clock frequency. Other clock-related settings are recalculated +automatically if the denominator is changed. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-config-flags"><title>Compiler Flags</title> + <para> +The platform HAL defines the default compiler and linker flags for all +packages, although it is possible to override these on a per-package +basis. Most of the flags used are the same as for other architectures +supported by eCos. There are two flags specific to this port: + </para> + <variablelist> + <varlistentry> + <term><option>-m4</option></term> + <listitem><para> +The <application>sh-elf-gcc</application> compiler supports many +variants of the SH architecture, from the SH2 onwards. +A <option>-m</option> option should be used to select the specific +variant in use, and with current tools <option>-m4</option> is the +correct option for the SH4-202. + </para></listitem> + </varlistentry> +<!-- DOES THIS APPLY? + <varlistentry> + <term><option>-fomit-frame-pointer</option></term> + <listitem><para> +Traditionally the <varname>R14</varname> register was used as a +dedicated frame pointer, and the compiler was expected to keep it up +to date +on procedure entry and exit. These days +the compiler is perfectly capable of generating working code without a +frame pointer, so omitting the frame pointer often saves some work +during procedure entry and exit and makes another register available +for optimization. However without a frame pointer register the +<application>sh-elf-gdb</application> debugger is not always able to +interpret a thread stack, so it cannot reliably give a backtrace. +Removing <option>-fomit-frame-pointer</option> from the default flags +will make debugging easier, but the generated code may be worse. + </para></listitem> + </varlistentry> +--> + </variablelist> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Port --> + +<refentry id="sh4-microdev-port"> + <refmeta> + <refentrytitle>The HAL Port</refentrytitle> + </refmeta> + <refnamediv> + <refname>HAL Port</refname> + <refpurpose>Implementation Details</refpurpose> + </refnamediv> + + <refsect1 id="sh4-microdev-port-overview"><title>Overview</title> + <para> +This documentation explains how the eCos HAL specification has been +mapped onto the MicroDev hardware, and should be read in conjunction +with that specification. The MicroDev platform HAL package complements +the SH architectural HAL and the SH4 variant HAL. It provides +functionality which is specific to the target board. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-port-startup"><title>Startup</title> + <para> +Following a hard or soft reset the HAL will initialize or +reinitialize most of the on-chip peripherals. There is an exception +for RAM startup applications which depend on a ROM monitor for certain +services. + </para> + <para> +For ROM startup, the HAL will perform additional initialization, +setting up the external DRAM and programming the various internal +registers. The values used for most of these registers are assigned +fixed values from a table in the header <filename +class="headerfile">cyg/hal/platform.inc</filename>. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-port-linker"><title>Linker Scripts and Memory Maps</title> + <para> +The platform HAL package provides the memory layout information needed +to generate the linker script. The key memory locations are as follows: + </para> + <variablelist> + <varlistentry> + <term>off-chip Flash</term> + <listitem><para> +This is located at address 0x00000000 of the physical memory space and is +therefore accessible in the P1 region at location 0x80000000. An +uncached shadow of this memory is available in the P2 region at 0xA0000000. +The contents of the flash are organized as described earlier. + </para></listitem> + </varlistentry> + <varlistentry> + <term>off-chip EEPROM</term> + <listitem> + <para> +If selected by the DIP switches, this occupies the same addresses as the +off-chip flash, and the flash is no longer visible. + </para> + </listitem> + </varlistentry> + <varlistentry> + <term>external SDRAM</term> + <listitem> + <para> +This is located at address 0x08000000 of the physical memory space and is +therefore accessable in the P1 region at location 0x88000000. An +uncached shadow of this memory is available in the P2 region at 0xA8000000. The +first 256 bytes are used for hardware exception vectors. The next 256 +bytes are normally used for the eCos virtual vectors, allowing +RAM-based applications to use services provided by the ROM +monitor. For ROM startup, all remaining SDRAM is available. For RAM +startup, available SDRAM starts at location 0x80100000, with the bottom +1MB reserved for use by RedBoot. + </para> + </listitem> + </varlistentry> + <varlistentry> + <term>on-chip peripherals</term> + <listitem><para> +These are accessible via the P4 region at location 0xE0000000 onwards. + </para></listitem> + </varlistentry> + <varlistentry> + <term>off-chip peripherals</term> + <listitem><para> +The ethernet device is located at 0xA7500000. The FPGA interrupt +controller is located at 0x06110000. These are the only +off-chip peripherals accessed by eCos. All others are left +untouched. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="sh4-microdev-port-clock"><title>Clock Support</title> + <para> +The platform HAL provides configuration options for the eCos system +clock. This always uses the hardware timer 0, which should not be used +directly by application code. Timer 1 is used to implement a +microsecond resolution busy delay service. Timer 2 is not used by eCos +so application code is free to manipulate this as required. The +actual HAL macros for managing the clock are provided by the SH architecture +processor HAL. + </para> + <para> +There is a software model of the structure of the SH family clock +supply subsystem which performs the correct calculations to yield not +only the inputs for the CPU clock but also the peripheral clocks fed +to the serial device, memory controllers and other devices. The values +for the master crystal, the PLL multipliers and various dividers are +supplied by the platform HAL. Some care must be taken in defining +these since wrong values will cause the timers and the SCIF baud rate +to be miscalculated. If the OSCAR chip switches are changed from the +default then the value of <varname>CYGHWR_HAL_SH_OOC_XTAL</varname> +must be changed to match. + </para> + </refsect1> + + <refsect1 id="sh4-microdev-port-other-hal"><title>Other Issues</title> + <para> +The MicroDev platform HAL does not affect the implementation of other +parts of the eCos HAL specification. The +SH4 variant HAL, and the SH architectural HAL documentation +should be consulted for further details. + </para> + <para> +It should be noted that the floating point support in the SH HAL has a +caveat that, if the FPSCR register is changed, it may get reverted at a +later stage by certain operations performed by the GCC compiler. This +behaviour is intentional as the alternative would be to update the GCC +compiler's internal state about the FPSCR at every context switch which +would be expensive for a feature that is unlikely to be used frequently. +If the FPSCR is to be changed by the application, the developer +should call the function <function>__set_fpscr(int)</function>, passing it +the new FPSCR value. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> + +</part>
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/hal_diag.h @@ -0,0 +1,69 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-12 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/pkgconf/mlt_sh_sh4_202_md_ram.h @@ -0,0 +1,18 @@ +// eCos memory layout - Mon Jul 16 12:39:37 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x88000000) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x8c000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/pkgconf/mlt_sh_sh4_202_md_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Mon Jul 16 12:39:37 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x88000000, LENGTH = 0x04000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (ram, 0x88100000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x10); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/pkgconf/mlt_sh_sh4_202_md_rom.h @@ -0,0 +1,25 @@ +// eCos memory layout - Mon Jul 16 12:45:16 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_rom (0x80000000) +#define CYGMEM_REGION_rom_SIZE (0x02000000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#define CYGMEM_REGION_ram (0x88000000) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved) []; +#endif +#define CYGMEM_SECTION_reserved (CYG_LABEL_NAME (__reserved)) +#define CYGMEM_SECTION_reserved_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x8c000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/pkgconf/mlt_sh_sh4_202_md_rom.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Mon Jul 16 12:45:16 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + rom : ORIGIN = 0x80000000, LENGTH = 0x02000000 + ram : ORIGIN = 0x88000000, LENGTH = 0x04000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0x80000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_eh_frame (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved) = 0x88000000; . = CYG_LABEL_DEFN(__reserved) + 0x200; + SECTION_data (ram, ALIGN (0x1), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/platform.inc @@ -0,0 +1,257 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## SuperH SH4-202 MicroDev CPU board assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov, nickg +## Contributors:jskov, nickg +## Date: 2003-08-20 +## Purpose: SuperH SH4-202 MicroDev CPU platform startup +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the SuperH SH4-202 +## MicroDev CPU board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/sh_offsets.inc> +#include <cyg/hal/sh_regs.h> + + +#------------------------------------------------------------------------------ +# Hardware initialization. + +#define END 0 +#define INT8 1 +#define INT16 2 +#define INT32 3 +#define DELAY 4 +#define SPIN 5 + + .macro hal_hardware_init + mova init_table,r0 + mov r0,r3 +1: mov.l @r3+,r0 // Data type + cmp/eq #END,r0 // End of table + bf 0f + bra 9f + nop +0: cmp/eq #INT8,r0 + bf 2f + // 8 bit data + mov.l @r3+,r0 // addr + mov.l @r3+,r1 // data + bra 1b + mov.b r1,@r0 +2: cmp/eq #INT16,r0 + bf 3f + // 16 bit data + mov.l @r3+,r0 // addr + mov.l @r3+,r1 // data + bra 1b + mov.w r1,@r0 +3: cmp/eq #INT32,r0 + bf 4f + // 32 bit data + mov.l @r3+,r0 // addr + mov.l @r3+,r1 // data + bra 1b + mov.l r1,@r0 +4: cmp/eq #DELAY,r0 + bf 6f + // delay + mov.l @r3+,r0 // count +5: cmp/eq #0,r0 + bt 1b + bra 5b + add #-1,r0 +6: cmp/eq #SPIN,r0 + bf 8f + // delay + mov.l @r3+,r0 // ID + mov #0,r0 +7: cmp/eq #0,r0 + bt 1b + bra 7b + nop +8: bra 1b + nop + + .align 2 +init_table: + + # Clock setup + .long INT16, CYGARC_REG_WTCSR, 0xA567 + .long INT16, CYGARC_REG_WTCNT, 0x5A00 + .long INT16, CYGARC_REG_FRQCR, CYGARC_REG_FRQCR_INIT + .long INT32, CYGARC_REG_FRQCR3, 0x006a + + # FEMI setup +#if 0 + # We rely on the FPGA to set up FEMI area 0 + .long INT32, CYGARC_REG_FEMI_A0MCR, 0x0b777138 +#endif + .long INT32, CYGARC_REG_FEMI_A1MCR, 0x0b777108 + .long INT32, CYGARC_REG_FEMI_A2MCR, 0x03777510 + .long INT32, CYGARC_REG_FEMI_A3MCR, 0x0b777110 + .long INT32, CYGARC_REG_FEMI_A4MCR, 0x0b777108 + +#ifndef CYG_HAL_STARTUP_RAM + # EMI setup + .long SPIN, 0xA5A50000 + .long INT32, CYGARC_REG_EMI_COC, 0x00000010 + .long DELAY, 10000 + .long SPIN, 0xA5A50001 + .long INT32, CYGARC_REG_EMI_MIM, 0x00000021 + .long SPIN, 0xA5A50002 + .long INT32, CYGARC_REG_EMI_STR, 0x0000116b + .long SPIN, 0xA5A50003 + .long INT32, CYGARC_REG_EMI_SDRA0, 0x0a001900 + .long SPIN, 0xA5A50004 + .long INT32, CYGARC_REG_EMI_SDRA1, 0x0c001900 + .long SPIN, 0xA5A50005 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000003 + .long SPIN, 0xA5A50006 + .long DELAY, 10000 + .long SPIN, 0xA5A50007 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000002 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long INT32, CYGARC_REG_EMI_SCR, 0x00000004 + .long SPIN, 0xA5A50008 + .long INT32, CYGARC_REG_EMI_SDMR0+0x110, 0xffffffff + .long SPIN, 0xA5A50009 + .long INT32, CYGARC_REG_EMI_SDMR1+0x110, 0xffffffff + .long SPIN, 0xA5A5000a + .long INT32, CYGARC_REG_EMI_MIM, 0x00900281 + .long SPIN, 0xA5A5000b + .long INT32, CYGARC_REG_EMI_SCR, 0x00000000 + .long SPIN, 0xA5A5000c +#endif + + .long END +9: + .endm + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_SH_MON_DEFINED + +#if !defined(CYG_HAL_STARTUP_RAM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are not starting up from RAM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + mov.l $hal_vsr_table,r3 + # Write exception vectors + mov.l $cyg_hal_default_exception_vsr,r4 + mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5 +1: mov.l r4,@r3 + add #4,r3 + dt r5 + bf 1b + # Write interrupt vector + mov.l $cyg_hal_default_interrupt_vsr,r4 + mov.l $hal_vsr_table,r3 + add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3 + mov.l r4,@r3 + bra 2f + nop + .align 2 + + SYM_PTR_REF(cyg_hal_default_exception_vsr) + SYM_PTR_REF(cyg_hal_default_interrupt_vsr) + SYM_PTR_REF(hal_vsr_table) +2: + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + # Write interrupt vector + mov.l $hal_vsr_table,r3 + mov.l $cyg_hal_default_interrupt_vsr,r4 + add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3 + mov.l r4,@r3 + bra 2f + nop + .align 2 + + SYM_PTR_REF(cyg_hal_default_interrupt_vsr) + SYM_PTR_REF(hal_vsr_table) +2: + .endm + +#else + + .macro hal_mon_init + .endm + +#endif + + +#define CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGPKG_HAL_SH_MON_DEFINED + +#endif // CYGONCE_HAL_PLATFORM_INC
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/plf_cache.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform specific cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 2003-08-20 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Nothing here + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/plf_intr.h @@ -0,0 +1,119 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 2003-08-20 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the SuperH SH4-202 MicroDev +// CPU board. +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +//---------------------------------------------------------------------------- +// External interrupts. + +#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_LVL3 + +//---------------------------------------------------------------------------- +// FPGA Interrupt controller + + +#define FPGA_INTC_BASE 0xA6110000ul /* INTC base address on CPU-board FPGA */ +#define FPGA_INTENB_REG (FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ +#define FPGA_INTDSB_REG (FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ +#define FPGA_INTENB_MASK(n) (1ul<<(n)) /* Interupt mask to enable Ethernet on INTC in CPU-board FPGA */ +#define FPGA_INTPRI_REG(n) (FPGA_INTC_BASE+0x10+((n)/8)*8) /* Interrupt Priority Register on INTC on CPU-board FPGA */ +#define FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* FPGA_INTPRI_LEVEL(int_number, int_level) */ +#define FPGA_INTPRI_MASK(n) (FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ + +#define FPGA_ETHERNET_INT (18) /* Interrupt number for Ethernet in INTC on CPU-board FPGA */ +#define ETHERNET_INT_PRIORITY (0xc) /* Interrupt Priority of Ethenet IRQ */ + +//---------------------------------------------------------------------------- +// Interrupt configuration extension macros + +#define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \ + case CYGNUM_HAL_INTERRUPT_ETH: \ + { \ + volatile cyg_uint32* const intEnableReg = (cyg_uint32*)FPGA_INTENB_REG; \ + volatile cyg_uint32* const intDisableReg = (cyg_uint32*)FPGA_INTDSB_REG; \ + \ + if( level ) \ + *intEnableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT); \ + else \ + *intDisableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT); \ + } \ + break; \ + case CYGNUM_HAL_INTERRUPT_NMI: \ + /* fall through */ \ + case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL2: \ + /* fall through */ \ + case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL14: \ + /* Cannot change levels */ \ + break; + +//---------------------------------------------------------------------------- +// Reset. +// Block interrupts and cause an exception. This forces a reset. + +#define HAL_PLATFORM_RESET() \ + asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL)) + +#define HAL_PLATFORM_RESET_ENTRY 0x80000000 + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/plf_io.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 2003-08-20 +// Purpose: SuperH SH4-202 MicroDev CPU board IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/hal_intr.h> + +//----------------------------------------------------------------------------- + +// Nothing here. This is where things like PCI access macros should go. + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_SH_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-06-12 +// Purpose: Platform HAL stub support for SuperH SH4-202 MicroDev CPU board. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_IO_SERIAL +#include <pkgconf/io_serial.h> +#endif + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#include <cyg/hal/sh_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/misc/redboot_EEPROM.ecm @@ -0,0 +1,126 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware sh4_202_md ; + template redboot ; + package -hardware CYGPKG_HAL_SH current ; + package -hardware CYGPKG_HAL_SH_SH4 current ; + package -hardware CYGPKG_HAL_SH_SH4_202_MD current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_SH_MICRODEV current ; + package -hardware CYGPKG_IO_SERIAL_SH_SCIF current ; + package -hardware CYGPKG_DEVS_ETH_SH_MICRODEV current ; + package -hardware CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_SH_FPU { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_SH_BIGENDIAN { + inferred_value 0 +}; + +cdl_component CYGPKG_HAL_SH_7750 { + inferred_value 0 +}; + +cdl_component CYGPKG_HAL_SH_202 { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/misc/redboot_RAM.ecm @@ -0,0 +1,60 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGHWR_HAL_SH_BIGENDIAN { + inferred_value 0 +}; + +cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL { + inferred_value 1 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +#cdl_option CYGPKG_HAL_GDB_FILEIO { +# user_value 1 +#};
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/misc/redboot_ROM.ecm @@ -0,0 +1,70 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_SH_BIGENDIAN { + inferred_value 0 +}; + +cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +#cdl_option CYGPKG_HAL_GDB_FILEIO { +# user_value 1 +#}; + +
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new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/src/hal_diag.c @@ -0,0 +1,79 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, nickg +// Contributors: jskov, nickg +// Date: 2003-08-20 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_diag.h> // our header. + +#include <cyg/hal/hal_if.h> // Calling interface +#include <cyg/hal/hal_intr.h> // Interrupt macros +#include <cyg/hal/sh4_scif.h> // driver API + +//----------------------------------------------------------------------------- + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + // COM1 is SCIF2. + cyg_hal_plf_scif_init(0, 0, CYGNUM_HAL_INTERRUPT_SCIF_RXI, + (cyg_uint8*)CYGARC_REG_SCIF_SCSMR2); +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/sh4_202_md/current/src/plf_misc.c @@ -0,0 +1,83 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 2003-08-20 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_if.h> // interfacing API +#include <cyg/hal/plf_io.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/hal_intr.h> + +//-------------------------------------------------------------------------- + +void +hal_platform_init(void) +{ + /* Enable the Ethernet interrupt on the INTC on the CPU-board FPGA */ + + volatile cyg_uint32* const intDisableReg = (cyg_uint32*)FPGA_INTDSB_REG; + volatile cyg_uint32* const intPriorityReg = (cyg_uint32*)FPGA_INTPRI_REG(FPGA_ETHERNET_INT); + + *intDisableReg = 0; + + /* Set the interrupt priority level for the Ethenet chip on the FPGA */ + *intPriorityReg &= ~FPGA_INTPRI_MASK(FPGA_ETHERNET_INT); + *intPriorityReg |= FPGA_INTPRI_LEVEL(FPGA_ETHERNET_INT,ETHERNET_INT_PRIORITY); + + hal_if_init(); +} + +//-------------------------------------------------------------------------- +// eof plf_misc.c