view packages/hal/sh/sh4/current/include/mod_202.h @ 1424:5268028c09c4

2003-09-21 Jonathan Larmour <jifl@eCosCentric.com> * src/var_misc.c (hal_variant_init): Set FPSCR on startup. * src/sh4_scif.c (cyg_hal_plf_scif_set_baud): New function, taken from init code, but with fix to wait for hardware to settle. (cyg_hal_plf_scif_control): Add __COMMCTL_GETBAUD and _SETBAUD support using above function. * include/sh4_scif.h: Add baud_rate to channel data. * include/mod_regs_ser.h (CYGARC_SCBRR_N): Don't tweak BRR for values < 4800 or > 115200 as it gets the values wrong. Instead trust the developer to DTRT. (CYGARC_REG_SCIF_SCLSR_ORER): Add definition for overrun in line status reg. 2003-09-19 John Dallaway <jld@ecoscentric.com> * cdl/hal_sh_sh4.cdl: Specify default CDL values for sh4_202_md target. 2003-09-11 Nick Garnett <nickg@ecoscentric.com> * include/var_regs.h (CYG_FPSCR): Changed initial value of fpscr to do round-to-nearest rather than round-to-zero. 2003-09-08 Nick Garnett <nickg@ecoscentric.com> * include/mod_202.h: Added define for UBC. The 202 appears to have one, although there is no documented info. It is also not clear what version it is. Setting this to 1 seems to work. * include/mod_regs_cac.h: * include/variant.inc: Updated cache dimensions and initialization to support larger, two way cache in sh4-202. 2003-09-05 Nick Garnett <nickg@ecoscentric.com> * include/variant.inc: * include/var_reg.h: * include/mod_202.h: * include/mod_regs_cpg.h: * include/mod_regs_emi.h: * include/mod_regs_femi.h: * include/mod_regs_intc.h: * cdl/hal_sh_sh4.cdl: Added SH-202 sub-variant, extra functional units, and modifications to existing units for this variant.
author nickg
date Fri, 05 Dec 2003 17:07:29 +0000
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#ifndef CYGONCE_HAL_MOD_77xx_H
#define CYGONCE_HAL_MOD_77xx_H

//=============================================================================
//
//      mod_202.h
//
//      List modules available on CPU
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett 
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   nickg
// Date:        2003-08-20
// Purpose:     Define modules (and versions) available on this CPU.
// Usage:       Included from <cyg/hal/sh_regs.h>
//
//              
//####DESCRIPTIONEND####
//
//=============================================================================

//-----------------------------------------------------------------------------
// Modules provided by the CPU

#define CYGARC_SH_MOD_CPG  1
#define CYGARC_SH_MOD_SCIF 1
#define CYGARC_SH_MOD_UBC  1
#define CYGARC_SH_MOD_INTC 2

//-----------------------------------------------------------------------------
// Extra details for Cache Module (CAC)

//=============================================================================
// Icache
// Cache dimenions
#define CYGARC_SH_MOD_CAC_I_SIZE        16384 // Size of cache in bytes
#define CYGARC_SH_MOD_CAC_I_LINE_SIZE   32    // Size of a cache line
#define CYGARC_SH_MOD_CAC_I_WAYS        2     // Associativity of the cache

// Cache addressing information
// entry: bits 12 -  5
#define CYGARC_SH_MOD_ICAC_ADDRESS_BASE   0xf0000000
#define CYGARC_SH_MOD_ICAC_ADDRESS_TOP    0xf0004000
#define CYGARC_SH_MOD_ICAC_ADDRESS_STEP   0x00000020
// V : bit 0
// Writing zero to V forces an invalidate of the line
#define CYGARC_SH_MOD_ICAC_ADDRESS_FLUSH  0x00000000


//=============================================================================
// Dcache
// Cache dimenions
#define CYGARC_SH_MOD_CAC_D_SIZE        32768 // Size of cache in bytes
#define CYGARC_SH_MOD_CAC_D_LINE_SIZE   32    // Size of a cache line
#define CYGARC_SH_MOD_CAC_D_WAYS        2     // Associativity of the cache

// Cache addressing information
// entry: bits 13 -  5
#define CYGARC_SH_MOD_DCAC_ADDRESS_BASE   0xf4000000
#define CYGARC_SH_MOD_DCAC_ADDRESS_TOP    0xf4008000
#define CYGARC_SH_MOD_DCAC_ADDRESS_STEP   0x00000020
// U : bit 1
// V : bit 0
// Writing zero to both forces a flush of the line if it is dirty.
#define CYGARC_SH_MOD_DCAC_ADDRESS_FLUSH  0x00000000

//-----------------------------------------------------------------------------
// Extra details for interrupt handling
#define CYGARC_SH_SOFTWARE_IP_UPDATE

#endif // CYGONCE_HAL_MOD_202_H