view packages/hal/sh/sh4/current/include/mod_regs_cac.h @ 1424:5268028c09c4

2003-09-21 Jonathan Larmour <jifl@eCosCentric.com> * src/var_misc.c (hal_variant_init): Set FPSCR on startup. * src/sh4_scif.c (cyg_hal_plf_scif_set_baud): New function, taken from init code, but with fix to wait for hardware to settle. (cyg_hal_plf_scif_control): Add __COMMCTL_GETBAUD and _SETBAUD support using above function. * include/sh4_scif.h: Add baud_rate to channel data. * include/mod_regs_ser.h (CYGARC_SCBRR_N): Don't tweak BRR for values < 4800 or > 115200 as it gets the values wrong. Instead trust the developer to DTRT. (CYGARC_REG_SCIF_SCLSR_ORER): Add definition for overrun in line status reg. 2003-09-19 John Dallaway <jld@ecoscentric.com> * cdl/hal_sh_sh4.cdl: Specify default CDL values for sh4_202_md target. 2003-09-11 Nick Garnett <nickg@ecoscentric.com> * include/var_regs.h (CYG_FPSCR): Changed initial value of fpscr to do round-to-nearest rather than round-to-zero. 2003-09-08 Nick Garnett <nickg@ecoscentric.com> * include/mod_202.h: Added define for UBC. The 202 appears to have one, although there is no documented info. It is also not clear what version it is. Setting this to 1 seems to work. * include/mod_regs_cac.h: * include/variant.inc: Updated cache dimensions and initialization to support larger, two way cache in sh4-202. 2003-09-05 Nick Garnett <nickg@ecoscentric.com> * include/variant.inc: * include/var_reg.h: * include/mod_202.h: * include/mod_regs_cpg.h: * include/mod_regs_emi.h: * include/mod_regs_femi.h: * include/mod_regs_intc.h: * cdl/hal_sh_sh4.cdl: Added SH-202 sub-variant, extra functional units, and modifications to existing units for this variant.
author nickg
date Fri, 05 Dec 2003 17:07:29 +0000
parents d2c90368aeef
children
line wrap: on
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//=============================================================================
//
//      mod_regs_cac.h
//
//      CAC (cache) Module register definitions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett 
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
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// in accordance with section (3) of the GNU General Public License.
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//
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//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   jskov
// Contributors:jskov, nickg
// Date:        2000-10-30
//              
//####DESCRIPTIONEND####
//
//=============================================================================

// Besides the below, cache sizes are defined in the CPU variant module
// headers (mod_77xx.h).

//--------------------------------------------------------------------------
// Cache registers
#define CYGARC_REG_CCR                  0xFF00001C

#define CYGARC_REG_CCR_IIX              0x00008000  // IC index enable
#define CYGARC_REG_CCR_ICI              0x00000800  // IC invalidation
#define CYGARC_REG_CCR_ICE              0x00000100  // IC Enable
#define CYGARC_REG_CCR_OIX              0x00000080  // OC index enable
#define CYGARC_REG_CCR_ORA              0x00000020  // OC RAM enable
#define CYGARC_REG_CCR_OCI              0x00000008  // OC Invalidation
#define CYGARC_REG_CCR_CB               0x00000004  // Copy-Back enable
#define CYGARC_REG_CCR_WT               0x00000002  // Write Through enable
#define CYGARC_REG_CCR_OCE              0x00000001  // OC Enable

#ifdef CYGPKG_HAL_SH_202
#define CYGARC_REG_CCR_EMODE            0x80000000  // Enhanced mode
#else
#define CYGARC_REG_CCR_EMODE            0x00000000  // No enhanced mode
#endif

#define CYGARC_REG_CCR_CE               0x00000101  // IC, OC Enable
#define CYGARC_REG_CCR_CF               0x00000808  // IC, OC Invalidation