Mercurial > flash_v2
diff packages/hal/mips/tx39/current/include/var_cache.h @ 18:7253dcc42a09 ecos-sw-1999-06-25
Merge from eCos master repository on 1999-06-25-15:31:50-BST
| author | jlarmour |
|---|---|
| date | Fri, 25 Jun 1999 08:28:05 +0000 |
| parents | d376b777e2ce |
| children | 29bc183297e1 |
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--- a/packages/hal/mips/tx39/current/include/var_cache.h +++ b/packages/hal/mips/tx39/current/include/var_cache.h @@ -255,6 +255,25 @@ //----------------------------------------------------------------------------- // Instruction cache line control +// On the TX39, the instruction cache must be disabled to use the index-invalidate +// cache operation. + +// Invalidate the entire cache +// This uses the index-invalidate cache operation. +#define HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ + HAL_ICACHE_DISABLE(); \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { \ + asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \ + } \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ +} // Invalidate cache lines in the given range without writing to memory. // This uses the index-invalidate cache operation since the TX39 does not @@ -264,15 +283,17 @@ { \ register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED(_state_); \ HAL_ICACHE_DISABLE(); \ for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ { \ asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \ } \ - HAL_ICACHE_ENABLE(); \ + if( _state_ ) HAL_ICACHE_ENABLE(); \ } -#endif +#endif // CYGPKG_HAL_MIPS_TX3904 //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_IMP_CACHE_H