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annotate packages/hal/mips/tx39/current/include/var_cache.h @ 18:7253dcc42a09 ecos-sw-1999-06-25

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Merge from eCos master repository on 1999-06-25-15:31:50-BST
author jlarmour
date Fri, 25 Jun 1999 08:28:05 +0000
parents d376b777e2ce
children 29bc183297e1
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1 #ifndef CYGONCE_IMP_CACHE_H
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2 #define CYGONCE_IMP_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // imp_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/imp_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal.h>
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51 #include <cyg/infra/cyg_type.h>
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52
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53 #include <cyg/hal/plf_cache.h>
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54
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55 //=============================================================================
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56 // Toshiba TX3904
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57
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58 #ifdef CYGPKG_HAL_MIPS_TX3904
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59
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60 //-----------------------------------------------------------------------------
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61 // Cache dimensions
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62
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63 // Data cache
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64 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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65 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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66 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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67
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68 // Instruction cache
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69 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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70 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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71 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
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72
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73 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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74 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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75
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76 //-----------------------------------------------------------------------------
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77 // Global control of data cache
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78
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79 // Enable the data cache
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80 // This uses a bit in the config register, which is TX39 specific.
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81 #define HAL_DCACHE_ENABLE_DEFINED
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82 #define HAL_DCACHE_ENABLE() \
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83 { \
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84 asm volatile ("mfc0 $2,$3;" \
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85 "ori $2,$2,0x0010;" \
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86 "mtc0 $2,$3;" \
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87 : \
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88 : \
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89 : "$2" \
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90 ); \
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91 \
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92 }
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93
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94 // Disable the data cache
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95 #define HAL_DCACHE_DISABLE_DEFINED
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96 #define HAL_DCACHE_DISABLE() \
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97 { \
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98 asm volatile ("mfc0 $2,$3;" \
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99 "la $3,0xFFFFFFEF;" \
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100 "and $2,$2,$3;" \
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101 "mtc0 $2,$3;" \
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102 : \
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103 : \
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104 : "$2", "$3" \
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105 ); \
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106 \
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107 }
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108
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109
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110 // Invalidate the entire cache
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111 // The TX39 only has hit-invalidate on the DCACHE, not
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112 // index-invalidate, so we cannot just empty the cache out without
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113 // knowing what is in it. This is annoying. So, the best we can do is
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114 // fill the cache with data that is unlikely to be there
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115 // otherwise. Hence we read bytes from the ROM space since this is
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116 // most likely to be code, and will not get out of sync even if it is not.
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117 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
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118 #define HAL_DCACHE_INVALIDATE_ALL() \
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119 { \
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120 CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000); \
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121 CYG_BYTE volatile tmp = 0; \
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122 int i; \
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123 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
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124 { \
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125 tmp = addr[i]; \
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126 } \
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127 }
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128
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129 // Synchronize the contents of the cache with memory.
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130 #define HAL_DCACHE_SYNC_DEFINED
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131 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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132
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133 // Set the data cache refill burst size
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134 //#define HAL_DCACHE_BURST_SIZE(_size_)
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135
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136 // Set the data cache write mode
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137 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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138
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139 //#define HAL_DCACHE_WRITETHRU_MODE 0
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140 //#define HAL_DCACHE_WRITEBACK_MODE 1
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141
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142 // Load the contents of the given address range into the data cache
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143 // and then lock the cache so that it stays there.
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144 #define HAL_DCACHE_LOCK_DEFINED
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145 #define HAL_DCACHE_LOCK(_base_, _size_) \
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146 { \
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147 asm volatile ("mfc0 $2,$7;" \
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148 "ori $2,$2,0x0100;" \
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149 "mtc0 $2,$7;" \
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150 : \
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151 : \
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152 : "$2" \
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153 ); \
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154 }
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155
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156 // Undo a previous lock operation
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157 #define HAL_DCACHE_UNLOCK_DEFINED
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158 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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159 { \
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160 asm volatile ("mfc0 $2,$7;" \
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161 "la $3,0xFFFFFEFF;" \
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162 "and $2,$2,$3;" \
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163 "mtc0 $2,$7;" \
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164 : \
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165 : \
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166 : "$2", "$3" \
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167 ); \
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168 }
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169
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170 // Unlock entire cache
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171 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
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172 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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173
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174
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175 //-----------------------------------------------------------------------------
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176 // Data cache line control
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177
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178 // Allocate cache lines for the given address range without reading its
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179 // contents from memory.
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180 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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181
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182 // Write dirty cache lines to memory and invalidate the cache entries
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183 // for the given address range.
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184 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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185 #define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
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186
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187 // Write dirty cache lines to memory for the given address range.
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188 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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189 #define HAL_DCACHE_STORE_DEFINED // Disable default definition
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190
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191 //-----------------------------------------------------------------------------
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192 // Global control of Instruction cache
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193
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194 // Enable the instruction cache
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195 // This uses a bit in the config register, which is TX39 specific.
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196 #define HAL_ICACHE_ENABLE_DEFINED
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197 #define HAL_ICACHE_ENABLE() \
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198 { \
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199 asm volatile ("mfc0 $2,$3;" \
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200 "ori $2,$2,0x0020;" \
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201 "mtc0 $2,$3;" \
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202 : \
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203 : \
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204 : "$2" \
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205 ); \
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206 \
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207 }
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208
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209 // Disable the instruction cache
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210 #define HAL_ICACHE_DISABLE_DEFINED
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211 #define HAL_ICACHE_DISABLE() \
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212 { \
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213 asm volatile ("mfc0 $2,$3;" \
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214 "la $3,0xFFFFFFDF;" \
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215 "and $2,$2,$3;" \
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216 "mtc0 $2,$3;" \
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217 : \
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218 : \
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219 : "$2", "$3" \
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220 ); \
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221 \
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222 }
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223
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224 // Load the contents of the given address range into the instruction cache
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225 // and then lock the cache so that it stays there.
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226 #define HAL_ICACHE_LOCK_DEFINED
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227 #define HAL_ICACHE_LOCK(_base_, _size_) \
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228 { \
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229 asm volatile ("mfc0 $2,$7;" \
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230 "ori $2,$2,0x0200;" \
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231 "mtc0 $2,$7;" \
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232 : \
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233 : \
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234 : "$2" \
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235 ); \
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236 }
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237
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238 // Undo a previous lock operation
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239 #define HAL_ICACHE_UNLOCK_DEFINED
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240 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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241 { \
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242 asm volatile ("mfc0 $2,$7;" \
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243 "la $3,0xFFFFFDFF;" \
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244 "and $2,$2,$3;" \
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245 "mtc0 $2,$7;" \
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246 : \
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247 : \
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248 : "$2", "$3" \
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249 ); \
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250 }
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251
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252 // Unlock entire cache
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253 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
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254 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
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255
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256 //-----------------------------------------------------------------------------
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257 // Instruction cache line control
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258 // On the TX39, the instruction cache must be disabled to use the index-invalidate
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259 // cache operation.
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260
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261 // Invalidate the entire cache
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262 // This uses the index-invalidate cache operation.
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263 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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264 #define HAL_ICACHE_INVALIDATE_ALL() \
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265 { \
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266 register CYG_ADDRESS _baddr_ = 0x80000000; \
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267 register CYG_ADDRESS _addr_ = 0x80000000; \
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268 register CYG_WORD _state_; \
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269 HAL_ICACHE_IS_ENABLED(_state_); \
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270 HAL_ICACHE_DISABLE(); \
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271 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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272 { \
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273 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
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274 } \
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275 if( _state_ ) HAL_ICACHE_ENABLE(); \
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276 }
6
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277
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278 // Invalidate cache lines in the given range without writing to memory.
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279 // This uses the index-invalidate cache operation since the TX39 does not
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280 // have hit-invalidate on the instruction cache.
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281 #define HAL_ICACHE_INVALIDATE_DEFINED
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282 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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283 { \
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284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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285 register CYG_WORD _size_ = (_asize_); \
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286 register CYG_WORD _state_; \
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287 HAL_ICACHE_IS_ENABLED(_state_); \
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288 HAL_ICACHE_DISABLE(); \
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289 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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290 { \
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291 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
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292 } \
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293 if( _state_ ) HAL_ICACHE_ENABLE(); \
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294 }
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295
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296 #endif // CYGPKG_HAL_MIPS_TX3904
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297
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298 //-----------------------------------------------------------------------------
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299 #endif // ifndef CYGONCE_IMP_CACHE_H
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300 // End of imp_cache.h