--- a/packages/hal/arm/pid/current/src/hal_diag.c
+++ b/packages/hal/arm/pid/current/src/hal_diag.c
@@ -32,7 +32,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   nickg, gthomas
-// Contributors:        nickg, gthomas
+// Contributors:nickg, gthomas
 // Date:        1998-03-02
 // Purpose:     HAL diagnostic output
 // Description: Implementations of HAL diagnostic output support.
@@ -52,91 +52,51 @@
 #include <cyg/hal/hal_intr.h>           // interrupt macros
 #include <cyg/hal/hal_io.h>             // IO macros
 #include <cyg/hal/hal_diag.h>
-#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 #include <cyg/hal/drv_api.h>
-#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
-#endif
-
-// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
-// totally stand-alone) system.
-
-#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
-#define HAL_DIAG_USES_HARDWARE
-#endif
-
-#ifndef HAL_DIAG_USES_HARDWARE
-#if (CYGHWR_HAL_ARM_PID_DIAG_PORT != CYGHWR_HAL_ARM_PID_GDB_PORT)
-#define HAL_DIAG_USES_HARDWARE
-#endif
-#endif
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_misc.h>           // Helper functions
 
 /*---------------------------------------------------------------------------*/
 /* From serial_16550.h */
-#if CYGHWR_HAL_ARM_PID_DIAG_PORT==0
-// This is the base address of the A-channel
-#define CYG_DEVICE_SERIAL_RS232_16550_BASE      0x0D800000
-#define CYG_DEVICE_SERIAL_INT                   CYGNUM_HAL_INTERRUPT_SERIALA
-#else
-// This is the base address of the B-channel
-#define CYG_DEVICE_SERIAL_RS232_16550_BASE      0x0D800020
-#define CYG_DEVICE_SERIAL_INT                   CYGNUM_HAL_INTERRUPT_SERIALB
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==9600
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x0C
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==19200
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x06
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==38400
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x03
+#endif
+#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==115200
+#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
+#define CYG_DEVICE_SERIAL_BAUD_LSB        0x01
 #endif
 
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==9600
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x0C
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==19200
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x06
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==38400
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x03
-#endif
-#if CYGHWR_HAL_ARM_PID_DIAG_BAUD==115200
-#define CYG_DEVICE_SERIAL_RS232_BAUD_MSB        0x00
-#define CYG_DEVICE_SERIAL_RS232_BAUD_LSB        0x01
-#endif
-
-#ifndef CYG_DEVICE_SERIAL_RS232_BAUD_MSB
+#ifndef CYG_DEVICE_SERIAL_BAUD_MSB
 #error Missing/incorrect serial baud rate defined - CDL error?
 #endif
 
 // Define the serial registers.
-#define CYG_DEVICE_SERIAL_RS232_16550_RBR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // receiver buffer register, read, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_THR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // transmitter holding register, write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_DLL \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00)
-    // divisor latch (LS), read/write, dlab = 1
-#define CYG_DEVICE_SERIAL_RS232_16550_IER \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04)
-    // interrupt enable register, read/write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_DLM \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04)
-    // divisor latch (MS), read/write, dlab = 1
-#define CYG_DEVICE_SERIAL_RS232_16550_IIR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08)
-    // interrupt identification register, read, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_FCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08)
-    // fifo control register, write, dlab = 0
-#define CYG_DEVICE_SERIAL_RS232_16550_LCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x0C)
-    // line control register, read/write
-#define CYG_DEVICE_SERIAL_RS232_16550_MCR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10)
-    // modem control register, read/write
-#define CYG_DEVICE_SERIAL_RS232_16550_LSR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x14)
-    // line status register, read
-#define CYG_DEVICE_SERIAL_RS232_16550_MSR \
-    ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x18)
-    // modem status register, read
+#define CYG_DEV_RBR 0x00   // receiver buffer register, read, dlab = 0
+#define CYG_DEV_THR 0x00   // transmitter holding register, write, dlab = 0
+#define CYG_DEV_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_IER 0x04   // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_DLM 0x04   // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_IIR 0x08   // interrupt identification register, read, dlab = 0
+#define CYG_DEV_FCR 0x08   // fifo control register, write, dlab = 0
+#define CYG_DEV_LCR 0x0C   // line control register, read/write
+#define CYG_DEV_MCR 0x10   // modem control register, read/write
+#define CYG_DEV_LSR 0x14   // line status register, read
+#define CYG_DEV_MSR 0x18   // modem status register, read
+
+// Interrupt Enable Register
+#define SIO_IER_RCV 0x01
+#define SIO_IER_XMT 0x02
+#define SIO_IER_LS  0x04
+#define SIO_IER_MS  0x08
 
 // The line status register bits.
 #define SIO_LSR_DR      0x01            // data ready
@@ -168,6 +128,318 @@
 #define SIO_LCR_SB     0x40             // set break
 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 
+// Modem Control Register
+#define SIO_MCR_DTR 0x01
+#define SIO_MCR_RTS 0x02
+#define SIO_MCR_INT 0x08   // Enable interrupts
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint8* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lcr;
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+    HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
+    lcr |= SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
+    HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
+    lcr &= ~SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
+    HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);  // Enable & clear FIFO
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+
+    HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
+    if ((lsr & SIO_LSR_DR) == 0)
+        return false;
+
+    HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
+    || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
+
+static channel_data_t pid_ser_channels[2] = {
+    { (cyg_uint8*)0x0D800000, 1000, CYGNUM_HAL_INTERRUPT_SERIALA },
+    { (cyg_uint8*)0x0D800020, 1000, CYGNUM_HAL_INTERRUPT_SERIALB }
+};
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    int ret = 0;
+    CYGARC_HAL_SAVE_GP();
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
+
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
+
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int res = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    char c;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+    *__ctrlc = 0;
+    HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
+    if ( (lsr & SIO_LSR_DR) != 0 ) {
+
+        HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
+        if( cyg_hal_is_break( &c , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Disable interrupts.
+    HAL_INTERRUPT_MASK(pid_ser_channels[0].isr_vector);
+    HAL_INTERRUPT_MASK(pid_ser_channels[1].isr_vector);
+
+    // Init channels
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[0]);
+    cyg_hal_plf_serial_init_channel(&pid_ser_channels[1]);
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[0]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[1]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CYGHWR_HAL_ARM_PID_DIAG_LEDS
+// Control the LEDs PP0-PP3. This requires the jumpers on pins 9-16 to
+// be set on LK11, thus preventing the use of the parallel port.
+
+#define CYG_DEVICE_PARALLEL_DATA 0x0d800040
+
+void
+hal_diag_led(int n)
+{
+    HAL_WRITE_UINT8(CYG_DEVICE_PARALLEL_DATA, (n & 0xf) << 4);
+}
+#endif // CYGHWR_HAL_ARM_PID_DIAG_LEDS
+
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
+#endif
+
+#if CYGHWR_HAL_ARM_PID_DIAG_PORT==0
+// This is the base address of the A-channel
+#define CYG_DEV_SERIAL_BASE      0x0D800000
+#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALA
+#else
+// This is the base address of the B-channel
+#define CYG_DEV_SERIAL_BASE      0x0D800020
+#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALB
+#endif
+
+static channel_data_t pid_ser_channel = {
+    (cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0 
+};
+
+// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
+// totally stand-alone) system.
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+#ifndef HAL_DIAG_USES_HARDWARE
+#if (CYGHWR_HAL_ARM_PID_DIAG_PORT != CYGHWR_HAL_ARM_PID_GDB_PORT)
+#define HAL_DIAG_USES_HARDWARE
+#endif
+#endif
 
 #ifdef HAL_DIAG_USES_HARDWARE
 
@@ -175,24 +447,12 @@ void hal_diag_init(void)
 {
     static int init = 0;
     char *msg = "\n\rARM eCos\n\r";
-    cyg_uint8 lcr;
 
     if (init++) return;
-    // 8-1-no parity.
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR,
-                     SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    lcr |= SIO_LCR_DLAB;
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLL,
-                     CYG_DEVICE_SERIAL_RS232_BAUD_LSB);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLM,
-                     CYG_DEVICE_SERIAL_RS232_BAUD_MSB);
-    lcr &= ~SIO_LCR_DLAB;
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_FCR, 0x07);  // Enable & clear FIFO
-    while (*msg) hal_diag_write_char(*msg++);
+    cyg_hal_plf_serial_init_channel(&pid_ser_channel);
+
+    while (*msg) cyg_hal_plf_serial_putc(&pid_ser_channel, *msg++);
 }
 
 #ifdef DEBUG_DIAG
@@ -207,14 +467,10 @@ static int diag_bp = 0;
 
 void hal_diag_write_char(char c)
 {
-    cyg_uint8 lsr;
+    hal_diag_init();
 
-    hal_diag_init();
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_THRE) == 0);
+    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
 
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
 #ifdef DEBUG_DIAG
     diag_buffer[diag_bp++] = c;
     if (diag_bp == DIAG_BUFSIZE) diag_bp = 0;
@@ -223,13 +479,7 @@ void hal_diag_write_char(char c)
 
 void hal_diag_read_char(char *c)
 {
-    cyg_uint8 lsr;
-
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_DR) == 0);
-
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
+    *c = cyg_hal_plf_serial_getc(&pid_ser_channel);
 }
 
 #else // HAL_DIAG relies on GDB
@@ -237,37 +487,25 @@ void hal_diag_read_char(char *c)
 // Initialize diag port - assume GDB channel is already set up
 void hal_diag_init(void)
 {
+    if (0) cyg_hal_plf_serial_init_channel(&pid_ser_channel); // avoid warning
 }
 
 // Actually send character down the wire
 static void
 hal_diag_write_char_serial(char c)
 {
-    cyg_uint8 lsr;
+    hal_diag_init();
 
-    hal_diag_init();
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-    } while ((lsr & SIO_LSR_THRE) == 0);
-
-    HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
-    HAL_IO_BARRIER ();
+    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
 }
 
 static bool
 hal_diag_read_serial(char *c)
 {
     long timeout = 1000000000;  // A long time...
-    cyg_uint8 lsr;
+    while (!cyg_hal_plf_serial_getc_nonblock(&pid_ser_channel, c))
+        if (0 == --timeout) return false;
 
-    do {
-        HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
-        if (--timeout == 0) return false;
-    } while ((lsr & SIO_LSR_DR) == 0);
-    HAL_IO_BARRIER ();                  // Prevent RBR preload.
-
-    HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
-    HAL_IO_BARRIER ();
     return true;
 }
 
@@ -360,19 +598,7 @@ hal_diag_write_char(char c)
 }
 #endif
 
-/*---------------------------------------------------------------------------*/
-
-#ifdef CYGHWR_HAL_ARM_PID_DIAG_LEDS
-// Control the LEDs PP0-PP3. This requires the jumpers on pins 9-16 to
-// be set on LK11, thus preventing the use of the parallel port.
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
-#define CYG_DEVICE_PARALLEL_DATA 0x0d800040
-
-void
-hal_diag_led(int n)
-{
-    HAL_WRITE_UINT8(CYG_DEVICE_PARALLEL_DATA, (n & 0xf) << 4);
-}
-#endif // CYGHWR_HAL_ARM_PID_DIAG_LEDS
 /*---------------------------------------------------------------------------*/
 /* End of hal_diag.c */