--- a/packages/devs/eth/powerpc/quicc2/current/ChangeLog
+++ b/packages/devs/eth/powerpc/quicc2/current/ChangeLog
@@ -1,3 +1,11 @@
+2003-03-04  Paul Fine <pfine@delcomsys.com>
+
+	* src/EnetPHY.c : Added PHY reset function for the ts6 platform.
+	Changed delay to use HAL_DELAY_US instead of a nop for loop.
+	* src/if_fec.c : Invoke PHY reset function for ts6 platform, as
+	well as VADS platform.  Remove unneeded and incorrect invocation
+	data cache macros.
+	
 2002-12-12  Gary Thomas  <gthomas@ecoscentric.com>
 2002-12-12  Patrick Doyle <wpd@delcomsys.com>
 

--- a/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.c
+++ b/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.c
@@ -41,6 +41,7 @@
 * Modified for the mpc8260 VADS board
 *--------------------------------------------------------------------*/
 #include "types.h"
+#include <cyg/hal/hal_intr.h> /* HAL_DELAY_US */
 #include "EnetPHY.h"
 
 /* Internal functions */
@@ -69,11 +70,34 @@ VUINT32 * pPortData;
 void 
 EnableResetPHY(volatile t_BCSR *pBCSR)
 {
+#ifdef CYGPKG_HAL_POWERPC_TS6
+#define ETH_RST_MASK 0x20
+  /* The FPGA control register on the TS6 board uses the same memory
+   * location as the BCSR register on the VADS board.
+   */
+  volatile cyg_uint32 *fpga_ctrl = (cyg_uint32 *) pBCSR;
+  volatile cyg_uint32 *fpga_vers;
+  cyg_uint32 value;
+  fpga_vers = fpga_ctrl + 1;
+  value = *fpga_vers;
+  if(value >= 6){ /* version 06 of the FPGA added PHY reset control */
+    value = *fpga_ctrl;
+    /* Set the PHY reset bit */
+    value |= ETH_RST_MASK;
+    *fpga_vers = value;
+
+    /* Give the PHY time to reset */
+    HAL_DELAY_US(10000);
+
+    /* Clear the reset bit */
+    *fpga_vers = value & ~ETH_RST_MASK;
+  }
+#else
   // active low FETHIEN on BSCR1, assert reset low
   pBCSR->bcsr1 &= ~(FETHIEN_ | FETHRST_);  
   // de-assert reset
   pBCSR->bcsr1 |= FETHRST_;  
-  
+#endif
 }
 
 
@@ -173,18 +197,12 @@ EthernetPHYInterruptHandler()
 UINT16 
 LinkTestPHY()
 {
-  UINT32 j, cnt;
-  UINT16 FrameValue;
-
-  //for (j = 0; j < 10; j++) {
-  for (j = 0; j < 5; j++) {
+  UINT32 j;
+  UINT16 FrameValue = 0;
 
-    for (cnt = 0; cnt < 1000000; cnt ++) {
-    
-      asm("nop");
-      asm("nop");
-      asm("nop");
-    }
+  for (j = 0; j < 50; j++) {
+
+    HAL_DELAY_US(100000);
   
     FrameValue = MdioFrame(READ,0,CHIP_STAT_REG,0);  
   

--- a/packages/devs/eth/powerpc/quicc2/current/src/if_fec.c
+++ b/packages/devs/eth/powerpc/quicc2/current/src/if_fec.c
@@ -184,24 +184,16 @@ fec_eth_init(struct cyg_netdevtab_entry 
     volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
     volatile t_Fcc_Pram  *fcc =  (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
     volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
-#ifdef CYGPKG_HAL_POWERPC_VADS
+#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
     volatile t_BCSR *CSR   = (t_BCSR *) 0x04500000;
 #endif
 
-    int cache_state;
     int i;
     bool esa_ok;
     bool fec_100;
     unsigned char *c_ptr;
     UINT16 link_speed;
 
-    // Ensure consistent state between cache and what the FEC sees
-    HAL_DCACHE_IS_ENABLED(cache_state);
-    if (cache_state) {
-      HAL_DCACHE_DISABLE();
-      HAL_DCACHE_INVALIDATE_ALL();
-    }
-
     // Link the memory to the driver control memory
     qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
 
@@ -209,7 +201,7 @@ fec_eth_init(struct cyg_netdevtab_entry 
     qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
     
     // Via BCSR, (re)start LXT970
-#ifdef CYGPKG_HAL_POWERPC_VADS 
+#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
     EnableResetPHY(CSR);
 #endif
 
@@ -409,9 +401,6 @@ fec_eth_init(struct cyg_netdevtab_entry 
     
     while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); 
 
-    if (cache_state)
-      HAL_DCACHE_ENABLE();
-
     // Initialize upper level driver for ecos
     (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);