--- a/packages/hal/h8300/aki3068net/current/ChangeLog
+++ b/packages/hal/h8300/aki3068net/current/ChangeLog
@@ -1,3 +1,34 @@
+2004-03-17  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* include/hal_diag.h
+	fix warning.
+
+2004-03-02  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* include/platform.inc
+	add h8300_save_vectors macro.
+	
+2004-02-24  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* cdl/hal_h8300_h8300h_aki3068net.cdl
+	add Linker flags "-mrelax"
+	move CYGSEM_HAL_H8300_VECTOR_HOOK to hal_h8300.cdl
+
+2004-01-16  Yoichi Koyanagi <yk@tinywillow.com>,Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* src/plf_ide.c  
+	HAL_IDE_INIT return to enumerate controlers.
+	aki3068net_read_command fix 16bit mode access.
+
+2003-12-26  Yoichi Koyanagi <yk@tinywillow.com>,Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* src/plf_ide.c  
+	16bit bus mode fix.
+
+2003-12-04  Yoshinori Sato  <ysato@users.sourceforge.jp>
+	* include/pkgconf/mlt_h8300_h8300h_aki3068net_rom.ldi
+	fix vector location from CYGSEM_HAL_H8300_VECTOR_HOOK == 0
+	
 2003-07-18  Nick Garnett  <nickg@balti.calivar.com>
 
 	* cdl/hal_h8300_h8300h_aki3068net.cdl:

--- a/packages/hal/h8300/aki3068net/current/cdl/hal_h8300_h8300h_aki3068net.cdl
+++ b/packages/hal/h8300/aki3068net/current/cdl/hal_h8300_h8300h_aki3068net.cdl
@@ -81,7 +81,7 @@ cdl_package CYGPKG_HAL_H8300_H8300H_AKI3
         display       "Startup type"
         flavor        data
         legal_values  {"ROM" "RAM"}
-        default_value {"RAM"}
+        default_value {"ROM"}
 	no_define
 	define -file system.h CYG_HAL_STARTUP
         description   "
@@ -204,7 +204,7 @@ cdl_package CYGPKG_HAL_H8300_H8300H_AKI3
             display "Global linker flags"
             flavor  data
             no_define
-            default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mh -mint32" }
+            default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mrelax -mh -mint32" }
             description   "
                 This option controls the global linker flags. Individual
                 packages may define options which override these global flags."
@@ -300,20 +300,12 @@ cdl_package CYGPKG_HAL_H8300_H8300H_AKI3
             application. This enables features such as utilizing a separate
             interrupt stack when exceptions are generated."
     }
-    cdl_option CYGSEM_HAL_H8300_VECTOR_HOOK {
-        display       "Interrupt Vector Hook"
-        flavor        bool
-        default_value 1
-        parent        CYGPKG_HAL_ROM_MONITOR
-        description   "
-            Interrupt Vector Table Hooking Support"
-    }
     cdl_option CYGHWR_HAL_H8300_VECTOR_ADDRESS {
         display       "Hook Vector Address"
         flavor        data
-        default_value 0xffbf20
+        default_value 0xfffd20
+	active_if CYGSEM_HAL_H8300_VECTOR_HOOK
         parent        CYGPKG_HAL_ROM_MONITOR
-        requires      { CYGSEM_HAL_H8300_VECTOR_HOOK == 1 }
         description   "
             Hooking Vector Table Address"
     }
@@ -324,4 +316,19 @@ cdl_package CYGPKG_HAL_H8300_H8300H_AKI3
         description   "
             Used SCI Channel base address."
     }
+    cdl_option CYGDAT_REDBOOT_H8300_LINUX_COMMAND_START {
+        display        "Default kernel command line start address"
+        flavor         data
+        default_value  0x5ffe00
+        description    "
+           This option uClinux kernel command line start address of default."
+    }
+
+    cdl_option CYGDAT_REDBOOT_H8300_LINUX_BOOT_COMMAND_LINE {
+        display        "Default command line"
+        flavor         data
+        default_value  { "console=/dev/ttySC1" }
+        description    "
+           This option uClinux kernel startup command line of default."
+    }
 }

--- a/packages/hal/h8300/aki3068net/current/include/pkgconf/mlt_h8300_h8300h_aki3068net_rom.ldi
+++ b/packages/hal/h8300/aki3068net/current/include/pkgconf/mlt_h8300_h8300h_aki3068net_rom.ldi
@@ -30,13 +30,18 @@ SECTIONS
     SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA)
     SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA)
     SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA)
+#if !defined(CYGSEM_HAL_H8300_VECTOR_HOOK)
+    SECTION_int_hook_table (rom, ALIGN (0x2), LMA_EQ_VMA)
+#endif
     SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
     SECTION_data (ram, WORK, FOLLOWING (.gcc_except_table))
     SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+#if defined(CYGSEM_HAL_H8300_VECTOR_HOOK)
 #if !defined(CYGPKG_IO_ETH_DRIVERS)
-    SECTION_int_hook_table (ram, CYGHWR_HAL_H8300_VECTOR_ADDRESS,FOLLOWING (.data))
+    SECTION_int_hook_table (ram, CYGHWR_HAL_H8300_VECTOR_ADDRESS, LMA_EQ_VMA)
 #else
-    SECTION_int_hook_table (iram, CYGHWR_HAL_H8300_VECTOR_ADDRESS,FOLLOWING (.data))
+    SECTION_int_hook_table (iram, CYGHWR_HAL_H8300_VECTOR_ADDRESS, LMA_EQ_VMA)
+#endif
 #endif
     SECTIONS_END
 }

--- a/packages/hal/h8300/aki3068net/current/include/platform.inc
+++ b/packages/hal/h8300/aki3068net/current/include/platform.inc
@@ -65,12 +65,16 @@
 
 ##-----------------------------------------------------------------------------
 
-#if CYGINT_HAL_PLF_IF_IDE != 0
-#define ABWCR_VAL ~((1 << ((CYGHWR_HAL_IDE_REGISTER >> 25) & 7)) |\
-                    (1 << ((CYGHWR_HAL_IDE_ALT_REGS >> 25) & 7))) 
+#if (CYGINT_HAL_PLF_IF_IDE != 0 && (CYGHWR_HAL_IDE_BUSWIDTH == 16))
+#define ABWCR_VAL ~((1 << ((CYGHWR_HAL_IDE_REGISTER >> 21) & 7)) |\
+                    (1 << ((CYGHWR_HAL_IDE_ALT_REGS >> 21) & 7))) 
 #else
 #define ABWCR_VAL 0xff
 #endif
+#if (CYGINT_HAL_PLF_IF_IDE != 0)
+#define CSCR_VAL ((1 << ((CYGHWR_HAL_IDE_REGISTER >> 21) & 7)) |\
+                  (1 << ((CYGHWR_HAL_IDE_ALT_REGS >> 21) & 7))) 
+#endif
 
 #define CYGPKG_HAL_H8300_MEMC_DEFINED
 	.macro	hal_memc_init
@@ -79,13 +83,11 @@
 1:
 	mov.w	@er0+,r2
 	beq	1f
+	mov.w	#0x00ff,e2	; internal I/O regs (2) high address
 	cmp.w	#0xf000,r2
 	bhi	2f
-	mov.w	#0x00fe,e2
-	bra	3f
+	dec.w	#1,e2		; internal I/O regs (1) high address
 2:
-	mov.w	#0x00ff,e2
-3:
 	mov.w	@er0+,r1
 	mov.b	r1l,@er2
 	bra	1b
@@ -97,29 +99,28 @@ init_regs:
 INIT_REGS_DATA(CYGARC_RTCOR,9)
 INIT_REGS_DATA(CYGARC_RTMCSR,0x30)
 INIT_REGS_DATA(CYGARC_DRCRB,0x98)
-INIT_REGS_DATA(CYGARC_DRCRA,0x3c)
+INIT_REGS_DATA(CYGARC_DRCRA,0x38)
 INIT_REGS_DATA(CYGARC_ASTCR,0xfb)
 INIT_REGS_DATA(CYGARC_ABWCR,ABWCR_VAL)
+#if defined(CSCR_VAL)
+INIT_REGS_DATA(CYGARC_CSCR,((CSCR_VAL) & 0xf0) | 0x0f)
+#endif
+INIT_REGS_DATA(CYGARC_WCRH ,0xff)
+INIT_REGS_DATA(CYGARC_WCRL ,0xc8)
 INIT_REGS_DATA(CYGARC_P1DDR,0xff)
 INIT_REGS_DATA(CYGARC_P2DDR,0xff)
 INIT_REGS_DATA(CYGARC_P5DDR,0x01)
-INIT_REGS_DATA(CYGARC_P8DDR,0x0c)
+INIT_REGS_DATA(CYGARC_P8DDR,0x0e)
 	.word	0
 init_regs_end:
-;; Thanks Hiroyuki Senshu
+;; Thanks Hiroyuki Senshu & Hiroki Minematsu
 
-;; DRAM Setup delay
+;; External peripheral setup delay
 1:
-	mov.b	#8,r0h
+	mov.l	#420000,er0	;wait 50ms
 2:
-	mov.b	#0,r0l
-3:
-	dec.b	r0l
-	bne	3b
-	mov.b	@CYGARC_RTMCSR,r0l
+	dec.l	#1,er0
 	bpl	2b
-	dec	r0h
-	bne	2b
 #endif
 	.endm
 
@@ -144,6 +145,13 @@ 3:
 	.macro	hal_diag_data
 	.endm
 
+#if defined(CYGPKG_IO_ETH_DRIVERS)
+#define CYGPKG_HAL_H8300_SAVED_VECTORS
+	.macro	h8300_save_vectors
+	.byte	15
+	.endm
+#endif
+
 #------------------------------------------------------------------------------
 #endif // ifndef CYGONCE_HAL_PLATFORM_INC
 # end of platform.inc

--- a/packages/hal/h8300/aki3068net/current/include/plf_io.h
+++ b/packages/hal/h8300/aki3068net/current/include/plf_io.h
@@ -65,11 +65,11 @@
 #define HAL_IDE_INIT() aki3068net_ide_setup()
 
 #define HAL_IDE_READ_UINT8( __ctlr, __regno, __val )  \
-    aki3068net_read_command(__regno, __val)
+    aki3068net_read_command(__regno, &(__val))
 #define HAL_IDE_READ_UINT16( __ctlr, __regno, __val )  \
-    aki3068net_read_data(__regno, __val)
+    aki3068net_read_data(__regno, &(__val))
 #define HAL_IDE_READ_ALTSTATUS( __ctlr, __val )  \
-    aki3068net_read_control( __val)
+    aki3068net_read_control( &(__val))
 
 #define HAL_IDE_WRITE_UINT8( __ctlr, __regno, __val )  \
     aki3068net_write_command(__regno, __val)

--- a/packages/hal/h8300/aki3068net/current/src/hal_diag.c
+++ b/packages/hal/h8300/aki3068net/current/src/hal_diag.c
@@ -60,7 +60,7 @@
 
 #define SCI_BASE ((cyg_uint8*)CYGHAL_PLF_SCI_BASE)
 
-const static channel_data_t channel = { (cyg_uint8*)SCI_BASE, 0, 0};
+static channel_data_t channel = { (cyg_uint8*)SCI_BASE, 0, 0};
 
 void
 cyg_hal_plf_comms_init(void)

--- a/packages/hal/h8300/aki3068net/current/src/plf_ide.c
+++ b/packages/hal/h8300/aki3068net/current/src/plf_ide.c
@@ -58,6 +58,7 @@
 #include <cyg/hal/hal_arch.h>           // architectural definitions
 #include <cyg/hal/hal_io.h>
 #include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_endian.h>
 #include <cyg/hal/plf_intr.h>
 #include <cyg/hal/var_arch.h>
 
@@ -68,12 +69,13 @@
 #define IDE_REG_FEATUERS 1
 #define IDE_REG_COMMAND  7
 
-void aki3068net_ide_setup(void)
+int aki3068net_ide_setup(void)
 {
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     aki3068net_write_command(IDE_REG_FEATUERS,0x01); /* 8bit transfer mode */
     aki3068net_write_command(IDE_REG_COMMAND, 0xef); /* set featuers */
 #endif
+    return HAL_IDE_NUM_CONTROLLERS;
 }
 
 void aki3068net_read_command(cyg_uint16 r, cyg_uint8 *d)
@@ -81,7 +83,7 @@ void aki3068net_read_command(cyg_uint16 
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     *d = *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_REGISTER + r);
 #else
-    *d = *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1)) & 0xff;
+    *d = *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1) + 1);
 #endif
 }
 
@@ -90,7 +92,9 @@ void aki3068net_read_data   (cyg_uint16 
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     *d = *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + r);
 #else
-    *d = *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1));
+    cyg_uint16 dt;
+    dt = *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1));
+    *d = CYG_LE16_TO_CPU(dt);
 #endif
 }
 
@@ -99,7 +103,7 @@ void aki3068net_read_control(cyg_uint8 *
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     *d = *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_ALT_REGS + 6);
 #else
-    *d = *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_ALT_REGS + 12) & 0xff;
+    *d = *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_ALT_REGS + 12 + 1);
 #endif
 }
 
@@ -108,7 +112,7 @@ void aki3068net_write_command(cyg_uint16
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_REGISTER + r) = d;
 #else
-    *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1) +1) = d;
+    *(volatile cyg_uint16 *)(CYGHWR_HAL_IDE_REGISTER + (r << 1)) = d;
 #endif
 }
 
@@ -117,7 +121,7 @@ void aki3068net_write_data   (cyg_uint16
 #if CYGHWR_HAL_IDE_BUSWIDTH == 8
     *(volatile cyg_uint8 *)(CYGHWR_HAL_IDE_REGISTER + r) = d;
 #else
-    *(volatile CYG_WORD16 *)(CYGHWR_HAL_IDE_REGISTER + (__regno <<1)) = (__val >> 8) | (__val << 8);
+    *(volatile CYG_WORD16 *)(CYGHWR_HAL_IDE_REGISTER + (r <<1)) = CYG_CPU_TO_LE16(d);
 #endif
 }