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changeset 859:463629669ddd

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New CPM support for baud rate generator allocation
author gthomas
date Sun, 23 Mar 2003 16:21:40 +0000
parents a23fa9968a6f
children 8e23fe1ac05e
files packages/devs/serial/powerpc/quicc/current/ChangeLog packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
diffstat 4 files changed, 25 insertions(+), 164 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog
+++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,12 @@
+2003-03-23  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc_serial.h: Move common definitions to common
+	include file (in HAL).
+
+	* src/quicc_smc_serial.c: 
+	* cdl/ser_quicc_smc.cdl: Remove options for baud rate generator
+	assignment - use more generic [automatic] support.
+
 2003-03-17  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/quicc_smc_serial.h: 
--- a/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl
+++ b/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl
@@ -113,16 +113,6 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
             for the PowerPC QUICC/SMC port 1."
     }
 
-    cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG {
-        display       "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 1"
-        flavor        data
-        legal_values  1 to 4
-        default_value 1
-        description   "
-            This option specifies which of the four baud rate generators
-            to use for the PowerPC QUICC/SMC port 1."
-    }
-
     cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE {
         display       "Output buffer size for the PowerPC QUICC/SMC serial port 1"
         flavor        data
@@ -204,16 +194,6 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
             for the PowerPC QUICC/SMC port 2."
     }
 
-    cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG {
-        display       "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 2"
-        flavor        data
-        legal_values  1 to 4
-        default_value 2
-        description   "
-            This option specifies which of the four baud rate generators
-            to use for the PowerPC QUICC/SMC port 2."
-    }
-
     cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE {
         display       "Output buffer size for the PowerPC QUICC/SMC serial port 2"
         flavor        data
@@ -328,16 +308,6 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
             for the PowerPC QUICC/SCC port 1."
     }
 
-    cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BRG {
-        display       "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 1"
-        flavor        data
-        legal_values  1 to 4
-        default_value 2
-        description   "
-            This option specifies which of the four baud rate generators
-            to use for the PowerPC QUICC/SCC port 1."
-    }
-
     cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE {
         display       "Output buffer size for the PowerPC QUICC/SCC serial port 1"
         flavor        data
@@ -419,16 +389,6 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
             for the PowerPC QUICC/SCC port 2."
     }
 
-    cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BRG {
-        display       "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 2"
-        flavor        data
-        legal_values  1 to 4
-        default_value 3
-        description   "
-            This option specifies which of the four baud rate generators
-            to use for the PowerPC QUICC/SCC port 2."
-    }
-
     cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE {
         display       "Output buffer size for the PowerPC QUICC/SCC serial port 2"
         flavor        data
@@ -510,16 +470,6 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q
             for the PowerPC QUICC/SCC port 3."
     }
 
-    cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BRG {
-        display       "Which baud rate generator to use for the PowerPC QUICC/SCC serial port 3"
-        flavor        data
-        legal_values  1 to 4
-        default_value 4
-        description   "
-            This option specifies which of the four baud rate generators
-            to use for the PowerPC QUICC/SCC port 3."
-    }
-
     cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE {
         display       "Output buffer size for the PowerPC QUICC/SCC serial port 3"
         flavor        data
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
+++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
@@ -74,7 +74,7 @@ typedef struct quicc_sxx_serial_info {
     CYG_ADDRWORD          channel;                   // Which channel SMCx/SCCx
     short                 int_num;                   // Interrupt number
     short                 type;                      // Channel type - SCC or SMC
-    cyg_uint32            *brg;                      // Which baud rate generator
+    unsigned long         *brg;                      // Which baud rate generator
     void                  *pram;                     // Parameter RAM pointer
     void                  *ctl;                      // SMC/SCC control registers
     volatile struct cp_bufdesc     *txbd, *rxbd;     // Next Tx,Rx descriptor to use
@@ -374,42 +374,20 @@ quicc_smc_serial_init_info(quicc_sxx_ser
                            int RxBD, int RxNUM, int RxSIZE,
                            cyg_uint8 *RxBUF,
                            int portBmask,
-                           int BRG, int SIpos)
+                           int port)
 {
     EPPC *eppc = eppc_base();
     struct cp_bufdesc *txbd, *rxbd;
-    cyg_uint32 simode = 0;
     int i;
 
     // Disable channel during setup
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
     smc_chan->pram = (void *)uart_pram;
     smc_chan->ctl = (void *)ctl;
-    /*
-     *  SDMA & LCD bus request level 5
-     *  (Section 16.10.2.1)
-     */
-    eppc->dma_sdcr = 1;
-    switch (BRG) {
-    case 1:
-        smc_chan->brg = (cyg_uint32 *)&eppc->brgc1;
-        simode = 0;
-        break;
-    case 2:
-        smc_chan->brg = (cyg_uint32 *)&eppc->brgc2;
-        simode = 1;
-        break;
-    case 3:
-        smc_chan->brg = (cyg_uint32 *)&eppc->brgc3;
-        simode = 2;
-        break;
-    case 4:
-        smc_chan->brg = (cyg_uint32 *)&eppc->brgc4;
-        simode = 3;
-        break;
-    }
-    // NMSI mode, BRGn to SMCm  (Section 16.12.5.2)
-    eppc->si_simode = (eppc->si_simode & ~(0xF<<SIpos)) | (simode<<SIpos);
+
+    // Set up baud rate generator
+    smc_chan->brg = _mpc8xx_allocate_brg(port);
+
     /*
      *  Set up the PortB pins for UART operation.
      *  Set PAR and DIR to allow SMCTXDx and SMRXDx
@@ -528,42 +506,20 @@ quicc_scc_serial_init_info(quicc_sxx_ser
                            int RxBD, int RxNUM, int RxSIZE,
                            cyg_uint8 *RxBUF,
                            int portAmask, int portBmask, int portCmask,
-                           int BRG, int SIpos)
+                           int port)
 {
     EPPC *eppc = eppc_base();
     struct cp_bufdesc *txbd, *rxbd;
-    cyg_uint32 simode = 0;
     int i;
 
     // Disable channel during setup
     ctl->scc_gsmr_l = 0;
     scc_chan->pram = (void *)uart_pram;
     scc_chan->ctl = (void *)ctl;
-    /*
-     *  SDMA & LCD bus request level 5
-     *  (Section 16.10.2.1)
-     */
-    eppc->dma_sdcr = 1;
-    switch (BRG) {
-    case 1:
-        scc_chan->brg = (cyg_uint32 *)&eppc->brgc1;
-        simode = 0;
-        break;
-    case 2:
-        scc_chan->brg = (cyg_uint32 *)&eppc->brgc2;
-        simode = 1;
-        break;
-    case 3:
-        scc_chan->brg = (cyg_uint32 *)&eppc->brgc3;
-        simode = 2;
-        break;
-    case 4:
-        scc_chan->brg = (cyg_uint32 *)&eppc->brgc4;
-        simode = 3;
-        break;
-    }
-    // Route baud rate generators
-    eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<SIpos)) | (((simode<<3)|(simode<<0))<<SIpos);
+
+    // Set up baud rate generator
+    scc_chan->brg = _mpc8xx_allocate_brg(port);
+
     /*
      *  Set up the PortA/B/C pins for UART operation.
      */
@@ -682,8 +638,7 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
                                    ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0]),
                                    0xC0, // PortB mask
-                                   CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
-                                   12  // SI mask position
+                                   QUICC_CPM_SMC1
             );
     }
 #endif
@@ -703,8 +658,7 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
                                    ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0]),
                                    0xC00, // PortB mask
-                                   CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
-                                   28  // SI mask position
+                                   QUICC_CPM_SMC2
             );
     }
 #endif
@@ -726,8 +680,7 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    0x0003, // PortA mask
                                    0x1000, // PortB mask
                                    0x0800, // PortC mask
-                                   CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_BRG,
-                                   0  // SI mask position
+                                   QUICC_CPM_SCC1
             );
     }
 #endif
@@ -749,8 +702,7 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    0x000C, // PortA mask
                                    0x2000, // PortB mask
                                    0x0C00, // PortC mask
-                                   CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_BRG,
-                                   8  // SI mask position
+                                   QUICC_CPM_SCC2
             );
     }
 #endif
@@ -772,8 +724,7 @@ quicc_sxx_serial_init(struct cyg_devtab_
                                    0x0000, // PortA mask
                                    0x00C0, // PortB mask
                                    0x0000, // PortC mask
-                                   CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_BRG,
-                                   16  // SI mask position
+                                   QUICC_CPM_SCC3
             );
     }
 #endif
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
+++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
@@ -58,31 +58,6 @@
 
 #include <cyg/hal/quicc/ppc8xx.h>                  // QUICC structure definitions
 
-// SMC Mode Register
-#define QUICC_SMCMR_CLEN(n)   ((n+1)<<11)   // Character length
-#define QUICC_SMCMR_SB(n)     ((n-1)<<10)   // Stop bits (1 or 2)
-#define QUICC_SMCMR_PE(n)     (n<<9)        // Parity enable (0=disable, 1=enable)
-#define QUICC_SMCMR_PM(n)     (n<<8)        // Parity mode (0=odd, 1=even)
-#define QUICC_SMCMR_UART      (2<<4)        // UART mode
-#define QUICC_SMCMR_TEN       (1<<1)        // Enable transmitter
-#define QUICC_SMCMR_REN       (1<<0)        // Enable receiver
-
-// SMC Events (interrupts)
-#define QUICC_SMCE_BRK 0x10  // Break received
-#define QUICC_SMCE_BSY 0x04  // Busy - receive buffer overrun
-#define QUICC_SMCE_TX  0x02  // Tx interrupt
-#define QUICC_SMCE_RX  0x01  // Rx interrupt
-
-// SMC Commands
-#define QUICC_SMC_CMD_InitTxRx  (0<<8)
-#define QUICC_SMC_CMD_InitTx    (1<<8)
-#define QUICC_SMC_CMD_InitRx    (2<<8)
-#define QUICC_SMC_CMD_StopTx    (4<<8)
-#define QUICC_SMC_CMD_RestartTx (6<<8)
-#define QUICC_SMC_CMD_Reset     0x8000
-#define QUICC_SMC_CMD_Go        0x0001
-
-
 static unsigned int smc_select_word_length[] = {
     QUICC_SMCMR_CLEN(5),  // 5 bits / word (char)
     QUICC_SMCMR_CLEN(6),
@@ -105,30 +80,6 @@ static unsigned int smc_select_parity[] 
     0,                                     // Space parity
 };
 
-// SCC PSMR masks ....
-#define QUICC_SCC_PSMR_ASYNC   0x8000
-#define QUICC_SCC_PSMR_SB(n)   ((n-1)<<14)  // Stop bits (1=1sb, 2=2sb)
-#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12)  // Character Length (5-8)
-#define QUICC_SCC_PSMR_PE(n)   (n<<4)       // Parity enable(0=disabled, 1=enabled)
-#define QUICC_SCC_PSMR_RPM(n)  (n<<2)       // Rx Parity mode (0=odd,  1=low, 2=even, 3=high)
-#define QUICC_SCC_PSMR_TPM(n)  (n)          // Tx Parity mode (0=odd,  1=low, 2=even, 3=high)
-
-// SCC DSR masks
-#define QUICC_SCC_DSR_FULL     0x7e7e
-#define QUICC_SCC_DSR_HALF     0x467e
-
-// SCC GSMR masks ...
-#define QUICC_SCC_GSMR_H_INIT  0x00000060 
-#define QUICC_SCC_GSMR_L_INIT  0x00028004 
-#define QUICC_SCC_GSMR_L_Tx    0x00000010
-#define QUICC_SCC_GSMR_L_Rx    0x00000020
-
-// SCC Events (interrupts)
-#define QUICC_SCCE_BRK         0x0040
-#define QUICC_SCCE_BSY         0x0004
-#define QUICC_SCCE_TX          0x0002
-#define QUICC_SCCE_RX          0x0001
-
 static unsigned int scc_select_word_length[] = {
   QUICC_SCC_PSMR_CLEN(5),  // 5 bits / word (char)
   QUICC_SCC_PSMR_CLEN(6),