Mercurial > flash_v2
changeset 1398:4f98ee8c6707
Add support for GPS-4020 (ARM7) platform
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--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,4 @@ +* Add support for GPS-4020 (embedded ARM7 GPS receiver/controller) * Basic IPSEC and libipsec support. * Flash driver for SST 39VFXXX devices * Wall clock driver for Synthetic target.
--- a/packages/devs/flash/atmel/at49xxxx/current/ChangeLog +++ b/packages/devs/flash/atmel/at49xxxx/current/ChangeLog @@ -1,3 +1,7 @@ +2003-11-10 Gary Thomas <gary@mlbassoc.com> + + * include/flash_at49xxxx_parts.inl: Add AT29LV200BB + 2003-09-19 Gary Thomas <gary@mlbassoc.com> * include/flash_at49xxxx_parts.inl: Add support for AT49LV040
--- a/packages/devs/flash/atmel/at49xxxx/current/include/flash_at49xxxx_parts.inl +++ b/packages/devs/flash/atmel/at49xxxx/current/include/flash_at49xxxx_parts.inl @@ -171,6 +171,23 @@ } }, #endif +#if defined(CYGHWR_DEVS_FLASH_ATMEL_AT29LV200BB) + { // AT29LV200BB + device_id : FLASHWORD(0x22BF), + block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE, + block_count: 4, + device_size: 0x40000 * CYGNUM_FLASH_INTERLEAVE, + base_mask : ~(0x40000 * CYGNUM_FLASH_INTERLEAVE - 1), + bootblock : true, + bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE, // 0x00000..0x03FFF + 0x004000 * CYGNUM_FLASH_INTERLEAVE, // 0x04000..0x05FFF + 0x002000 * CYGNUM_FLASH_INTERLEAVE, // 0x06000..0x07FFF + 0x002000 * CYGNUM_FLASH_INTERLEAVE, // 0x08000..0x0FFFF + 0x008000 * CYGNUM_FLASH_INTERLEAVE, + _LAST_BOOTBLOCK + } + }, +#endif #endif // ifndef CYGONCE_DEVS_FLASH_ATMEL_AT49XXXX_PARTS_INL
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/arm/gps4020/current/ChangeLog @@ -0,0 +1,40 @@ +2003-11-10 Gary Thomas <gary@mlbassoc.com> + + * src/gps4020_serial.c: + + * cdl/ser_arm_gps4020.cdl: New package - serial driver for GPS4020 + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/arm/gps4020/current/cdl/ser_arm_gps4020.cdl @@ -0,0 +1,210 @@ +# ==================================================================== +# +# ser_arm_gps4020.cdl +# +# eCos GPS4020 serial driver configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_ARM_GPS4020 { + display "GPS4020 serial device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_ARM_GPS4020 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + GPS-4020 board." + + compile -library=libextras.a gps4020_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_gps4020.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 { + display "GPS4020 serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the GPS4020 + port 1." + + + cdl_option CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME { + display "Device name for the GPS4020 serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the ARM + GPS4020 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD { + display "Baud rate for the GPS4020 serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 57600 + description " + This option specifies the default baud rate (speed) for the ARM + GPS4020 port 1." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE { + display "Buffer size for the GPS4020 serial port 1 driver" + flavor data + default_value 128 + legal_values 0 to 8192 + description " + This option specifies the size of the internal buffers used + for the GPS4020 port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 { + display "GPS4020 serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the ARM + GPS4020 port 2." + + cdl_option CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL2_NAME { + display "Device name for the GPS4020 serial port 2 driver" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the name of serial device for the ARM + GPS4020 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD { + display "Baud rate for the GPS4020 serial port 2 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 57600 + description " + This option specifies the default baud rate (speed) for the + GPS4020 port 2." + } + + cdl_option CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE { + display "Buffer size for the GPS4020 serial port 2 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the GPS4020 port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_ARM_GPS4020_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_ARM_GPS4020_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_ARM_GPS4020_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 + + implements CYGINT_IO_SERIAL_TEST_SKIP_115200 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"gps4020\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\"" + } + } +} + +# EOF ser_arm_gps4020.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/arm/gps4020/current/src/gps4020_serial.c @@ -0,0 +1,465 @@ +//========================================================================== +// +// io/serial/arm/gps4020_serial.c +// +// GPS4020 Serial I/O Interface Module +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: GPS4020 Serial I/O module +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_if.h> + +#include <cyg/hal/gps4020.h> // Hardware definitions + +static short select_word_length[] = { + -1, // 5 bits / word (char) + -1, // 6 bits / word + SMR_LENGTH_7, // 7 bits/word + SMR_LENGTH_8 // 8 bits/word +}; + +static short select_stop_bits[] = { + -1, + SMR_STOP_1, // 1 stop bit + -1, // 1.5 stop bit + SMR_STOP_2 // 2 stop bits +}; + +static short select_parity[] = { + SMR_PARITY_OFF, // No parity + SMR_PARITY_ON|SMR_PARITY_EVEN, // Even parity + SMR_PARITY_ON|SMR_PARITY_ODD, // Odd parity + -1, // Mark parity + -1, // Space parity +}; + +// Baud rate values, based on internal system (20MHz) clock +// Note: the extra *10 stuff is for rounding. Since these values +// are so small, a little error here can make/break the calculation +#define BAUD_DIVISOR(baud) (((((20000000*10)/(16*baud))+5)/10)-1) +static cyg_int32 select_baud[] = { + 0, // Unused + BAUD_DIVISOR(50), // 50 + BAUD_DIVISOR(75), // 75 + BAUD_DIVISOR(110), // 110 + 0, // 134.5 + BAUD_DIVISOR(150), // 150 + BAUD_DIVISOR(200), // 200 + BAUD_DIVISOR(300), // 300 + BAUD_DIVISOR(600), // 600 + BAUD_DIVISOR(1200), // 1200 + BAUD_DIVISOR(1800), // 1800 + BAUD_DIVISOR(2400), // 2400 + BAUD_DIVISOR(3600), // 3600 + BAUD_DIVISOR(4800), // 4800 + BAUD_DIVISOR(7200), // 7200 + BAUD_DIVISOR(9600), // 9600 + BAUD_DIVISOR(14400), // 14400 + BAUD_DIVISOR(19200), // 19200 + BAUD_DIVISOR(38400), // 38400 + BAUD_DIVISOR(57600), // 57600 + BAUD_DIVISOR(115200), // 115200 + BAUD_DIVISOR(230400), // 230400 +}; + +typedef struct gps4020_serial_info { + CYG_ADDRWORD regs; // Pointer to UART registers + CYG_WORD tx_int_num, // Transmit interrupt number + rx_int_num, // Receive interrupt number + ms_int_num; // Modem Status Change interrupt number + cyg_interrupt serial_tx_interrupt, + serial_rx_interrupt, + serial_ms_interrupt; + cyg_handle_t serial_tx_interrupt_handle, + serial_rx_interrupt_handle, + serial_ms_interrupt_handle; + bool tx_enabled; +} gps4020_serial_info; + +static bool gps4020_serial_init(struct cyg_devtab_entry *tab); +static bool gps4020_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo gps4020_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char gps4020_serial_getc(serial_channel *chan); +static Cyg_ErrNo gps4020_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void gps4020_serial_start_xmit(serial_channel *chan); +static void gps4020_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 gps4020_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 gps4020_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#if 0 // FIXME - handle modem & errors +static cyg_uint32 gps4020_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void gps4020_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +#endif + +static SERIAL_FUNS(gps4020_serial_funs, + gps4020_serial_putc, + gps4020_serial_getc, + gps4020_serial_set_config, + gps4020_serial_start_xmit, + gps4020_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL1 +static gps4020_serial_info gps4020_serial_info1 = {GPS4020_UART1, // Data register + CYGNUM_HAL_INTERRUPT_UART1_TX, // Tx interrupt + CYGNUM_HAL_INTERRUPT_UART1_RX, // Rx interrupt + CYGNUM_HAL_INTERRUPT_UART1_ERR, // Modem & Error interrupt + }; +#if CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE > 0 +static unsigned char gps4020_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE]; +static unsigned char gps4020_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(gps4020_serial_channel1, + gps4020_serial_funs, + gps4020_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &gps4020_serial_out_buf1[0], sizeof(gps4020_serial_out_buf1), + &gps4020_serial_in_buf1[0], sizeof(gps4020_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(gps4020_serial_channel1, + gps4020_serial_funs, + gps4020_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(gps4020_serial_io1, + CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + gps4020_serial_init, + gps4020_serial_lookup, // Serial driver may need initializing + &gps4020_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 + +#ifdef CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 +static gps4020_serial_info gps4020_serial_info2 = {GPS4020_UART2, // Data register + CYGNUM_HAL_INTERRUPT_UART2_TX, // Tx interrupt + CYGNUM_HAL_INTERRUPT_UART2_RX, // Rx interrupt + CYGNUM_HAL_INTERRUPT_UART2_ERR, // Modem & Error interrupt + }; +#if CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE > 0 +static unsigned char gps4020_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE]; +static unsigned char gps4020_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(gps4020_serial_channel2, + gps4020_serial_funs, + gps4020_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &gps4020_serial_out_buf2[0], sizeof(gps4020_serial_out_buf2), + &gps4020_serial_in_buf2[0], sizeof(gps4020_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(gps4020_serial_channel2, + gps4020_serial_funs, + gps4020_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_GPS4020_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(gps4020_serial_io2, + CYGDAT_IO_SERIAL_ARM_GPS4020_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + gps4020_serial_init, + gps4020_serial_lookup, // Serial driver may need initializing + &gps4020_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_GPS4020_SERIAL2 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +gps4020_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + unsigned int baud_divisor = select_baud[new_config->baud]; + short word_len = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + short stop_bits = select_stop_bits[new_config->stop]; + short parity = select_parity[new_config->parity]; + short mode = word_len | stop_bits | parity; + int prescale = 0; + + if (mode >= 0) { + while (baud_divisor > 0xFF) { + prescale++; + baud_divisor >>= 1; + } +#ifdef CYGDBG_IO_INIT + diag_printf("I/O MODE: %x, BAUD: %x\n", mode, baud_divisor); + CYGACC_CALL_IF_DELAY_US((cyg_int32)2*100000); +#endif + regs->mode = mode | SMR_DIV(prescale); + regs->baud = baud_divisor; + regs->modem_control = SMR_DTR | SMR_RTS; + regs->control = SCR_TEN | SCR_REN | SCR_TIE | SCR_RIE; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; + } else { + return false; + } +} + +// Function to initialize the device. Called at bootstrap time. +static bool +gps4020_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("GPS4020 SERIAL init - dev: %x.%d\n", gps4020_chan->regs, gps4020_chan->tx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(gps4020_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + gps4020_serial_tx_ISR, + gps4020_serial_tx_DSR, + &gps4020_chan->serial_tx_interrupt_handle, + &gps4020_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(gps4020_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + gps4020_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + cyg_drv_interrupt_create(gps4020_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + gps4020_serial_rx_ISR, + gps4020_serial_rx_DSR, + &gps4020_chan->serial_rx_interrupt_handle, + &gps4020_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(gps4020_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(gps4020_chan->rx_int_num); + } + gps4020_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +gps4020_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +gps4020_serial_putc(serial_channel *chan, unsigned char c) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + if ((regs->status & SSR_TxEmpty) != 0) { + // Transmit buffer/FIFO is not full + regs->TxRx = c; + return true; + } else { + // No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +gps4020_serial_getc(serial_channel *chan) +{ + unsigned char c; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + while ((regs->status & SSR_RxFull) == 0) ; // Wait for character + c = regs->TxRx; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +gps4020_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != gps4020_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +gps4020_serial_start_xmit(serial_channel *chan) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + gps4020_chan->tx_enabled = true; + cyg_drv_interrupt_unmask(gps4020_chan->tx_int_num); +} + +// Disable the transmitter on the device +static void +gps4020_serial_stop_xmit(serial_channel *chan) +{ + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + gps4020_chan->tx_enabled = false; +} + +// Serial I/O - low level Tx interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Tx interrupt handler (DSR) +static void +gps4020_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (gps4020_chan->tx_enabled) { + cyg_drv_interrupt_unmask(gps4020_chan->tx_int_num); + } +} + +// Serial I/O - low level Rx interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Rx interrupt handler (DSR) +static void +gps4020_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + volatile struct _gps4020_uart *regs = (volatile struct _gps4020_uart *)gps4020_chan->regs; + + while ((regs->status & SSR_RxFull) != 0) + (chan->callbacks->rcv_char)(chan, regs->TxRx); + cyg_drv_interrupt_unmask(gps4020_chan->rx_int_num); +} + +#if 0 // FIXME - handle modem & errors +// Serial I/O - low level Ms interrupt handler (ISR) +static cyg_uint32 +gps4020_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + gps4020_serial_info *gps4020_chan = (gps4020_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(gps4020_chan->ms_int_num); + cyg_drv_interrupt_acknowledge(gps4020_chan->ms_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Ms interrupt handler (DSR) +static void +gps4020_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ +} +#endif +
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -5324,6 +5324,50 @@ target pc_rltk8139 { # -------------------------------------------------------------------------- +package CYGPKG_HAL_ARM_GPS4020 { + alias { "GPS4020" hal_gps4020 } + directory hal/arm/gps4020 + script hal_arm_gps4020.cdl + hardware + description " + The GPS4020 HAL package provides the support needed to run + eCos on a GPS 4020 board using the Firefly MF1 (ARM) processor." +} + +package CYGPKG_DEVS_FLASH_GPS4020 { + alias { "FLASH memory support for GPS4020" flash_gps4020 } + directory devs/flash/arm/gps4020 + script flash_gps4020.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the GPS4020 platform." +} + +package CYGPKG_IO_SERIAL_ARM_GPS4020 { + alias { "GPS4020 serial device drivers" + devs_serial_arm_gps4020 gps4020_serial_driver } + hardware + directory devs/serial/arm/gps4020 + script ser_arm_gps4020.cdl + description "GPS4020 serial device drivers" +} + +target gps4020 { + alias { "GPS 4020" gps_4020 gps} + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_GPS4020 + CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX + CYGPKG_DEVS_FLASH_GPS4020 + CYGPKG_IO_SERIAL_ARM_GPS4020 + } + description " + The gps4020 target provides the packages needed to run + eCos on a GPS-4020 board." +} + +# -------------------------------------------------------------------------- + package CYGPKG_VNC_SERVER { alias { "VNC server" vnc_server } directory net/vnc_server
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/ChangeLog @@ -0,0 +1,60 @@ +2003-11-10 Gary Thomas <gary@mlbassoc.com> + + * support/download/tty.c: + * support/download/gps4020_start.S: + * support/download/gps4020_download.c: + * support/download/download_bin.py: + * support/download/download.py: + * support/download/arm.ld: + * support/download/Makefile: + * src/hal_diag.c: + * src/gps4020_misc.c: + * misc/redboot_ROM.ecm: + * misc/redboot_RAM.ecm: + * include/pkgconf/mlt_arm_gps4020_rom.ldi: + * include/pkgconf/mlt_arm_gps4020_rom.h: + * include/pkgconf/mlt_arm_gps4020_ram.ldi: + * include/pkgconf/mlt_arm_gps4020_ram.h: + * include/plf_stub.h: + * include/plf_io.h: + * include/hal_platform_setup.h: + * include/hal_platform_ints.h: + * include/hal_diag.h: + * include/hal_cache.h: + * include/gps4020.h: + * cdl/hal_arm_gps4020.cdl: New package - support for GPS-4020 + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/cdl/hal_arm_gps4020.cdl @@ -0,0 +1,332 @@ +# ==================================================================== +# +# hal_arm_gps4020.cdl +# +# GPS4020 board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Original data: gthomas +# Contributors: +# Date: 1999-06-13 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_GPS4020 { + display "GPS4020 evaluation board" + parent CYGPKG_HAL_ARM + define_header hal_arm_gps4020.h + include_dir cyg/hal + hardware + description " + The gps4020 HAL package provides the support needed to run + eCos on a ARM GPS4020-1 eval board." + + compile hal_diag.c gps4020_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_ARM_ARCH_ARM7 + implements CYGINT_HAL_TESTS_NO_CACHES + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_gps4020.h>" + puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 100000" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"GPS-4020\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the GPS4020-1 eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The GPS4020 board has only one serial port. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The GPS4020 board has only one serial port. This option + chooses which port will be used for diagnostic output." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value ((CYGNUM_HAL_RTC_NUMERATOR/1000)/CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=arm7tdmi -Wl,--gc-sections -Wl,-static -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. This is a bit convoluted as it involves prepending + the image with a special header used by the GPS4020 firmware + to keep track of multiple ROM images. This header includes + a checksum making it necessary to build twice." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PACKAGE>/src/gdb_module.c + @sh -c "mkdir -p src $(dir $@)" + # First build version with no checksum. + $(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o src/gdb_module_ncs.o $< + $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/gdb_module_ncs.tmp src/gdb_module_ncs.o + $(OBJCOPY) --strip-debug --change-addresses=0xFBFF4000 src/gdb_module_ncs.tmp src/gdb_module_ncs.img + $(OBJCOPY) -O binary src/gdb_module_ncs.img src/gdb_module_ncs.bin + @rm src/gdb_module_ncs.tmp src/gdb_module_ncs.img + # Prepare dependency file + @echo $@ ": \\" > $(notdir $@).deps + @echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps + @tail +2 deps.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm deps.tmp + # Then build version with checksum from previously built image. + @cp $(dir $<)flash_cksum.tcl src/ + $(CC) -c -DCHECKSUM=`src/flash_cksum.tcl src/gdb_module_ncs.bin` $(INCLUDE_PATH) -I$(dir $<) $(CFLAGS) -o src/gdb_module.o $< + $(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/gdb_module.tmp src/gdb_module.o + $(OBJCOPY) --strip-debug --change-addresses=0xFBFF4000 src/gdb_module.tmp $(@:.bin=.img) + $(OBJCOPY) -O binary $(@:.bin=.img) src/gdb_module.bin + uuencode src/gdb_module.bin gdb_module.bin | tr '`' ' ' > $(@:.bin=.img.UU) + @rm src/gdb_module.tmp src/gdb_module_ncs.bin + @mv src/gdb_module.bin $@ + } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_gps4020_ram" : \ + CYG_HAL_STARTUP == "ROM" ? "arm_gps4020_rom" : \ + "??" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_gps4020_ram.ldi>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_gps4020_rom.ldi>" : \ + "<pkgconf/BAD>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_gps4020_ram.h>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_gps4020_rom.h>" : \ + "<pkxgconf/BAD>" } + } + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + # The backup image is not needed, since ROMRAM is the normal + # RedBoot startup type. + requires {!CYGPKG_REDBOOT_FLASH || CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP == 0} + + # RedBoot details + requires { !CYGBLD_BUILD_REDBOOT_WITH_EXEC } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to the various relocated SREC images needed + for flash updating." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/gps4020.h @@ -0,0 +1,176 @@ +//========================================================================== +// +// gps4020.h +// +// GPS-4020 Platform specific registers, etc +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2003-10-01 +// Purpose: Platform specific registers, etc +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#ifndef _GPS4020_H_ +#define _GPS4020_H_ + +#define GPS4020_WATCHDOG 0xE0004000 +#define GPS4020_INTC 0xE0006000 +#define GPS4020_TC1 0xE000E000 +#define GPS4020_TC2 0xE000F000 +#define GPS4020_UART1 0xE0018000 +#define GPS4020_UART2 0xE0019000 + +#ifndef __ASSEMBLER__ +struct _gps4020_watchdog { + unsigned long control; + unsigned long period; + unsigned long current; // Only accessible in TEST mode + unsigned long reset; +}; +#endif +#define GPS4020_WATCHDOG_RESET 0xECD9F7BD + +#ifndef __ASSEMBLER__ +struct _gps4020_uart { + unsigned char control; + unsigned char _fill0[3]; + unsigned char mode; + unsigned char _fill1[3]; + unsigned char baud; + unsigned char _fill2[3]; + unsigned char status; + unsigned char _fill3[3]; + unsigned char TxRx; + unsigned char _fill4[3]; + unsigned char modem_control; + unsigned char _fill5[3+8]; + unsigned char modem_status; + unsigned char _fill6[3]; +}; +#endif + +// Serial control +#define SCR_MIE 0x80 // Modem interrupt enable +#define SCR_EIE 0x40 // Error interrupt enable +#define SCR_TIE 0x20 // Transmit interrupt enable +#define SCR_RIE 0x10 // Receive interrupt enable +#define SCR_FCT 0x08 // Flow type 0=>software, 1=>hardware +#define SCR_CLK 0x04 // Clock source 0=internal, 1=external +#define SCR_TEN 0x02 // Transmitter enabled +#define SCR_REN 0x01 // Receiver enabled +// Serial mode +#define SMR_DIV(x) ((x)<<4) // Clock divisor +#define SMR_STOP 0x08 // Stop bits 0=>one, 1=>two +#define SMR_STOP_1 0x00 +#define SMR_STOP_2 0x08 +#define SMR_PARITY 0x04 // Parity mode 0=>even, 1=odd +#define SMR_PARITY_EVEN 0x00 +#define SMR_PARITY_ODD 0x04 +#define SMR_PARITY_ON 0x02 // Parity checked +#define SMR_PARITY_OFF 0x00 +#define SMR_LENGTH 0x01 // Character length +#define SMR_LENGTH_8 0x00 +#define SMR_LENGTH_7 0x01 +// Serial status +#define SSR_MSS 0x80 // Modem status has changed +#define SSR_OE 0x40 // Overrun error +#define SSR_FE 0x20 // Framing error +#define SSR_PE 0x10 // Parity error +#define SSR_TxActive 0x08 // Transmitter is active +#define SSR_RxActive 0x04 // Receiver is active +#define SSR_TxEmpty 0x02 // Tx buffer is empty +#define SSR_RxFull 0x01 // Rx buffer contains data +// Modem control +#define SMR_CFG 0x08 // Configuration 0=>normal, 1=>null +#define SMR_MSU 0x04 // Modem status update 1=>enable +#define SMR_DTR 0x02 // Assert DTR +#define SMR_RTS 0x01 // Assert RTS + +#ifndef __ASSEMBLER__ +struct _gps4020_timer { + struct { + unsigned long control; + unsigned long reload; + unsigned long current; + unsigned long _reserved[5]; + } tc[2]; +}; +#endif + +// Timer/counter control +#define TC_CTL_IE (1<<22) // Interrupt enable +#define TC_CTL_OS (1<<21) // Overflow (count through 0) +#define TC_CTL_MODE (3<<19) // Timer/counter mode +#define TC_CTL_MODE_HALT (0<<19) +#define TC_CTL_MODE_FREE (1<<19) +#define TC_CTL_MODE_RELOAD (2<<19) +#define TC_CTL_MODE_PWM (3<<19) +#define TC_CTL_SCR (1<<18) // Software control request +#define TC_CTL_SCR_HALT (0<<18) +#define TC_CTL_SCR_COUNT (1<<18) +#define TC_CTL_HEP (1<<17) // Hardware enable polarity +#define TC_CTL_STAT (1<<16) // Current status + +#define TC_CLOCK_BASE 20 // Assumes 20MHz system clock + +#ifndef __ASSEMBLER__ +struct _gps4020_intc { + unsigned long sources; // Active interrupt sources + unsigned long polarity; // 0=>active low + unsigned long active; + unsigned long trigger; // 0=>level, 1=>edge + unsigned long reset; // reset edge triggers + unsigned long enable; // 1=>enable + unsigned long status; // masked (active and enabled) + unsigned long type; // 0=>IRQ, 1=>FIQ + unsigned long FIQ_status; + unsigned long IRQ_status; + unsigned long FIQ_encoded; + unsigned long IRQ_encoded; +}; +#endif + +#ifndef __ASSEMBLER__ +externC void _gps4020_watchdog(bool is_idle); +#endif +#endif // _GPS4020_H_
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/hal_cache.h @@ -0,0 +1,193 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/hal_diag.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +// Not the best place for this, but ... +extern void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(n) hal_delay_us(n); + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/hal_platform_ints.h @@ -0,0 +1,95 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for AEB-1 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-20 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the GPS4020 board/platform are +// defined here. +// +// Usage: #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_WATCHDOG 0 +#define CYGNUM_HAL_INTERRUPT_CORR_ACCUM 1 +#define CYGNUM_HAL_INTERRUPT_CORR_MEAS 2 +#define CYGNUM_HAL_INTERRUPT_DMAC 3 +#define CYGNUM_HAL_INTERRUPT_PCL 4 +#define CYGNUM_HAL_INTERRUPT_TIC1A 6 +#define CYGNUM_HAL_INTERRUPT_TIC1B 7 +#define CYGNUM_HAL_INTERRUPT_RF_PLL_LOCK 8 +#define CYGNUM_HAL_INTERRUPT_BSIO 13 +#define CYGNUM_HAL_INTERRUPT_UART1_ERR 14 +#define CYGNUM_HAL_INTERRUPT_UART1_RX 15 +#define CYGNUM_HAL_INTERRUPT_UART1_TX 16 +#define CYGNUM_HAL_INTERRUPT_TIC2A 18 +#define CYGNUM_HAL_INTERRUPT_TIC2B 19 +#define CYGNUM_HAL_INTERRUPT_EXT 20 +#define CYGNUM_HAL_INTERRUPT_UART2_ERR 26 +#define CYGNUM_HAL_INTERRUPT_UART2_RX 27 +#define CYGNUM_HAL_INTERRUPT_UART2_TX 28 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 28 +#define CYGNUM_HAL_ISR_COUNT 29 + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIC1A + + +//---------------------------------------------------------------------------- +// Reset. +extern void hal_gps4020_reset(void); +#define HAL_PLATFORM_RESET() hal_gps4020_reset() + +#define HAL_PLATFORM_RESET_ENTRY 0x60000000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/hal_platform_setup.h @@ -0,0 +1,123 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-13 +// Purpose: GPS4020 platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#define CYGSEM_HAL_ROM_RESET_USES_JUMP + + .equ MPC_BASE_ADDRESS, 0xE0008000 + .equ MPC_AREA1_CONFIG, 0x00000000 + .equ MPC_AREA2_CONFIG, 0x00000004 + .equ MPC_AREA3_CONFIG, 0x00000008 + .equ MPC_AREA4_CONFIG, 0x0000000C + + .equ GPIO_BASE_ADDRESS, 0xE0005000 + .equ GPIO_DIRECTION_REG_OFFSET,0x00000000 + .equ GPIO_READ_REG_OFFSET, 0x00000004 + .equ GPIO_WRITE_REG_OFFSET, 0x00000008 + + .equ SYSTEM_CONFIG, 0xE0002004 + + .macro gps4020_setup + +// make GPIO[0..7] outputs - note: GPIO4 is used for Rx on UART1! + ldr r3,=GPIO_BASE_ADDRESS + ldr r0, [r3,#GPIO_DIRECTION_REG_OFFSET] + and r0, r0, #0b00010000 @ 0 = output, 1 = input + str r0, [r3,#GPIO_DIRECTION_REG_OFFSET] + mov r0,#0 + str r0,[r3,#GPIO_WRITE_REG_OFFSET] + + ldr r1,=MPC_BASE_ADDRESS + ldr r2,=0x4400002D // 0x6xxxxxxx, 16bit R/W RAM + str r2,[r1,#MPC_AREA1_CONFIG] + + ldr r1,=MPC_BASE_ADDRESS + ldr r2,=0x00000069 // 0x2xxxxxxx, 16bit R/W RAM + str r2,[r1,#MPC_AREA2_CONFIG] + + ldr r2,[r1,#MPC_AREA3_CONFIG] + ldr r2,=0x00000021 // 0x4xxxxxxx, 16bit peripheral + str r2,[r1,#MPC_AREA3_CONFIG] + + ldr r2,[r1,#MPC_AREA4_CONFIG] + ldr r2,=0x0000006E // 0x0xxxxxxx, 32bit memory + str r2,[r1,#MPC_AREA4_CONFIG] + + ldr r1,=SYSTEM_CONFIG // Swap memory regions 0x0XXXXXXX, 0x6XXXXXXX + ldr r2,[r1] + orr r2,r2,#1 + mov r0,#1 + str r0,[r3,#GPIO_WRITE_REG_OFFSET] + ldr r4,=10f // Change address space + str r2,[r1] + + mov pc,r4 + mov pc,r4 + mov pc,r4 +10: + mov r0,#2 + str r0,[r3,#GPIO_WRITE_REG_OFFSET] + .endm + +#ifdef CYG_HAL_STARTUP_ROM +#define PLATFORM_SETUP1 gps4020_setup +#else +#define PLATFORM_SETUP1 +#endif + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/pkgconf/mlt_arm_gps4020_ram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0) +#define CYGMEM_REGION_sram_SIZE (0x2000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x40000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x20040000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/pkgconf/mlt_arm_gps4020_ram.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0, LENGTH = 0x2000 + ram : ORIGIN = 0x20000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x20008000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/pkgconf/mlt_arm_gps4020_rom.h @@ -0,0 +1,23 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0) +#define CYGMEM_REGION_sram_SIZE (0x2000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x40000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x60000000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x20040000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/pkgconf/mlt_arm_gps4020_rom.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0, LENGTH = 0x2000 + ram : ORIGIN = 0x20000000, LENGTH = 0x40000 + rom : ORIGIN = 0x60000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (rom, 0x60000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/plf_io.h @@ -0,0 +1,59 @@ +#ifndef CYGONCE_HAL_ARM_AEB_PLF_IO_H +#define CYGONCE_HAL_ARM_AEB_PLF_IO_H + +/*============================================================================= +// +// plf_io.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2002-01-28 +// Purpose: Platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_io.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#endif // CYGONCE_HAL_ARM_AEB_PLF_IO_H +// EOF plf_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/include/plf_stub.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas +// Date: 1999-02-15 +// Purpose: Platform HAL stub support for ARM/AEB boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM +#include <cyg/hal/arm_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/misc/redboot_RAM.ecm @@ -0,0 +1,96 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware gps4020 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_GPS4020 current ; + package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ; + package -hardware CYGPKG_DEVS_FLASH_GPS4020 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + inferred_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/misc/redboot_ROM.ecm @@ -0,0 +1,104 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware gps4020 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_GPS4020 current ; + package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ; + package -hardware CYGPKG_DEVS_FLASH_GPS4020 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + inferred_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/src/gps4020_misc.c @@ -0,0 +1,211 @@ +//========================================================================== +// +// gps4020_misc.c +// +// HAL misc board support code for ARM GPS4020-1 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-20 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // necessary? +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_if.h> // calling interface +#include <cyg/hal/hal_misc.h> // helper functions +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/drv_api.h> // HAL ISR support +#endif + +#include <cyg/hal/gps4020.h> + +static cyg_uint32 _period; + +void hal_clock_initialize(cyg_uint32 period) +{ + volatile struct _gps4020_timer *tc = (volatile struct _gps4020_timer *)GPS4020_TC1; + + // Start timer in "reload" mode to set counter value + tc->tc[0].control = TC_CTL_SCR_HALT; // Disable timer + tc->tc[0].reload = period; + tc->tc[0].control = TC_CTL_IE | TC_CTL_SCR_COUNT | TC_CTL_MODE_RELOAD | TC_CTL_HEP | TC_CLOCK_BASE; + _period = period; +} + +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + hal_clock_initialize(period); + _gps4020_watchdog(false); +} + +void hal_clock_read(cyg_uint32 *pvalue) +{ + volatile struct _gps4020_timer *tc = (volatile struct _gps4020_timer *)GPS4020_TC1; + *pvalue = _period - tc->tc[0].current; +} + +// +// Delay for some number of micro-seconds +// Use timer #2 of TC2 +// +void hal_delay_us(cyg_int32 usecs) +{ + volatile struct _gps4020_timer *tc = (volatile struct _gps4020_timer *)GPS4020_TC2; + unsigned long val1, val2; + int timeout; + + // Start timer in "reload" mode to set counter value + tc->tc[1].control = TC_CTL_SCR_HALT; // Disable timer + tc->tc[1].reload = usecs; + tc->tc[1].control = TC_CTL_SCR_COUNT | TC_CTL_MODE_RELOAD | TC_CTL_HEP | TC_CLOCK_BASE; + timeout = 10; + val1 = tc->tc[1].current; + while ((tc->tc[1].control & TC_CTL_OS) == 0) { + if (--timeout == 0) { + val2 = tc->tc[1].current; + if (val1 == val2) { + // Timer is stuck - use a cruder method! + while (--usecs > 0) ; + return; + } + } + } +} + +void hal_hardware_init(void) +{ + volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC; + + // Clear and reset all interrupt sources + intc->enable = 0; + // 3322 2222 2222 1111 1111 1100 0000 0000 + // 1098 7654 3210 9876 5432 1098 7654 3210 + intc->polarity = 0x1C01E01F; // 0001 1100 0000 0001 1110 0000 0001 1111; + intc->trigger = 0x000C00C0; // 0000 0000 0000 1100 0000 0000 1100 0000; + // Set up eCos/ROM interfaces + hal_if_init(); +} + +// +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. + +int hal_IRQ_handler(void) +{ + volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC; + int vec = (intc->IRQ_encoded >> 2); + return vec; +} + +// +// Interrupt control +// + +void hal_interrupt_mask(int vector) +{ + volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC; + intc->enable &= ~(1<<vector); +} + +void hal_interrupt_unmask(int vector) +{ + volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC; + intc->enable |= (1<<vector); +} + +void hal_interrupt_acknowledge(int vector) +{ + volatile struct _gps4020_intc *intc = (volatile struct _gps4020_intc *)GPS4020_INTC; + intc->reset = (1<<vector); +} + +void hal_interrupt_configure(int vector, int level, int up) +{ +// diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up); +} + +void hal_interrupt_set_level(int vector, int level) +{ +// diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level); +} + +//----------------------------------------------------------------------------- +// Reset board + +void +hal_gps4020_reset(void) +{ + volatile struct _gps4020_watchdog *wdg = (volatile struct _gps4020_watchdog *)GPS4020_WATCHDOG; + + wdg->period = 1; // Almost as fast as possible + wdg->reset = GPS4020_WATCHDOG_RESET; + // Wait for it... + for(;;); +} + +// Watchdog support +void +_gps4020_watchdog(bool is_idle) +{ + volatile struct _gps4020_watchdog *wdg = (volatile struct _gps4020_watchdog *)GPS4020_WATCHDOG; + wdg->reset = GPS4020_WATCHDOG_RESET; +} + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +RedBoot_idle(_gps4020_watchdog, RedBoot_AFTER_NETIO); +#endif + +/*------------------------------------------------------------------------*/ +// EOF hal_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/src/hal_diag.c @@ -0,0 +1,255 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors:nickg, gthomas +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/gps4020.h> + +//----------------------------------------------------------------------------- +typedef struct { + volatile struct _gps4020_uart *base; + cyg_int32 msec_timeout; + int isr_vector; + int int_state; +} channel_data_t; + +static channel_data_t serial_channels[] = { + { (volatile struct _gps4020_uart *)GPS4020_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, 0 }, +}; + +//----------------------------------------------------------------------------- + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + volatile struct _gps4020_uart *uart = ((channel_data_t*)__ch_data)->base; + uart->mode = SMR_STOP_1 | SMR_PARITY_OFF | SMR_LENGTH_8; + uart->baud = 0x15; // FIXME - Magic for 57600 + uart->modem_control = SMR_DTR | SMR_RTS; + uart->control = SCR_TEN | SCR_REN; +} + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c) +{ + volatile struct _gps4020_uart *uart = ((channel_data_t*)__ch_data)->base; + // Wait for space for character + do { + } while ((uart->status & SSR_TxEmpty) == 0); + uart->TxRx = c; +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch) +{ + volatile struct _gps4020_uart *uart = ((channel_data_t*)__ch_data)->base; + if ((uart->status & SSR_RxFull) == 0) { + return false; + } + *ch = uart->TxRx; + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + CYGACC_CALL_IF_DELAY_US(100); + } + + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + volatile struct _gps4020_uart *uart = ((channel_data_t*)__ch_data)->base; + int ret = 0; + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->int_state = 1; + uart->control |= SCR_RIE; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->int_state; + chan->int_state = 0; + uart->control &= ~SCR_RIE; + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + volatile struct _gps4020_uart *uart = ((channel_data_t*)__ch_data)->base; + char c; + + cyg_drv_interrupt_acknowledge(chan->isr_vector); + *__ctrlc = 0; + if ((uart->status & SSR_RxFull) != 0) { + c = uart->TxRx; + if (cyg_hal_is_break(&c, 1)) + *__ctrlc = 1; + res = CYG_ISR_HANDLED; + } + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channel + cyg_hal_plf_serial_init_channel(&serial_channels[0]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &serial_channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/Makefile @@ -0,0 +1,77 @@ +######################################################################### +# # +# Template Makefile for Assembly Language Programs # +# # +######################################################################### + +# Author: John Zaitseff <J.Zaitseff@unsw.edu.au>, Modified by +# Andrew Greenberg (andrew@uad.com) +# Date: 18th August, 2003 +# Version: 1.0 + +# Please note that every line that is indented (or, in the language of +# Makefiles, the command part of the rules) is done so with TAB +# characters, NOT with spaces. This is important and a subtle trap for +# the unwary! + +ALL = gps4020_download +all: $(ALL) + +GPS4020_DOWNLOAD_FILES = gps4020_start.o gps4020_download.o tty.o +gps4020_download: $(GPS4020_DOWNLOAD_FILES) + $(CC) $(LDFLAGS) -Tarm.ld -o $@ $(GPS4020_DOWNLOAD_FILES) + $(OC) $(OCFLAGS) $@ $@.bin + $(SIZE) $@ + +clean: + rm -f $(ALL) *.o *~ + +# The following variables and implicit rules are required for the GNU +# Assembler for ARM. You probably do not need to modify anything here. + +AS = arm-elf-as +SIZE = arm-elf-size +LD = arm-elf-ld +CC = arm-elf-gcc +OC = arm-elf-objcopy + +# ADG: we don't need debugging info: removed "ASFLAGS = --gdwarf2" +ASFLAGS = +LDFLAGS = -nostdlib -Wl,-static -Wl,-Map,$@.map +OCFLAGS = --output-target binary +LOADLIBES = +LDLIBS = +CFLAGS = -O2 -msoft-float + +.SUFFIXES: + +# Assemble ARM assembly language source (.s) to an object file (.o) using as. +# eg: "arm-elf-as -marm7tdmi gps4020_download.s -o gps4020_download.o" + +%.o: %.s + $(AS) -marm7tdmi $(ASFLAGS) $< -o $@ + +%.o: %.S + $(CC) -c -marm7tdmi $(ASFLAGS) $< -o $@ + +# Link object file (.0) into an ARM executable (.elf), using ld. +# eg: "arm-elf-ld -o gps4020_download.o gps4020_download.elf" + +%.elf: %.o + $(LD) $(LDFLAGS) $< $(LOADLIBES) $(LDLIBS) -o $@ + +# "Copy" ELF file (.elf) into a binary file for execution using objcopy. +# eg: "arm-elf-objcopy --output-target binary gps4020_download.elf gps4020_download.bin" + +%.bin: %.elf + $(OC) $(OCFLAGS) $< $@ + +# Compile "C" code +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +# Miscellaneous rules + +.PHONY: all clean +.DEFAULT: +.SUFFIXES:
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/arm.ld @@ -0,0 +1,21 @@ +ENTRY(start) + +MEMORY +{ + ram : ORIGIN = 0x0, LENGTH = 0x2000 +} + +SECTIONS +{ + .text 0x00000000 : { _stext = .; *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) *(.glue_7) *(.glue_7t) } > ram _etext = .; PROVIDE (etext = .); + .fini ALIGN (0x4) : { . = .; *(.fini) } > ram + .rodata1 ALIGN (0x8) : { . = .; *(.rodata1*) } > ram + .rodata ALIGN (0x8) : { . = .; *(.rodata*) } > ram + .fixup ALIGN (0x4) : { __FIXUP_START__ = ABSOLUTE(.); *(.fixup) __FIXUP_END__ = ABSOLUTE(.);} > ram + .gcc_except_table ALIGN (0x1) : { __EXCEPT_START__ = ABSOLUTE(.); *(.gcc_except_table) __EXCEPT_END__ = ABSOLUTE(.);} > ram + .data ALIGN (0x8) : { __ram_data_start = ABSOLUTE(.); *(.data*) __GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.); . = ALIGN(8); __CTOR_LIST__ = ABSOLUTE(.); KEEP(*(SORT(.ctors*))) __CTOR_END__ = ABSOLUTE(.); __DTOR_LIST__ = ABSOLUTE(.); KEEP(*(SORT(.dtors*))) __DTOR_END__ = ABSOLUTE(.); . = ALIGN(8); KEEP(*( SORT (.ecos.table.*))) ; . = ALIGN(4); *( .2ram.*) ; __GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.); __GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); _SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got) __GOT_END__ = ABSOLUTE(.); *(.dynamic) *(.eh_frame) __SDATA_START__ = ABSOLUTE(.); *(.sdata) *(.sdata.*) __SDATA2_START__ = ABSOLUTE(.); *(.sdata2*) } > ram __rom_data_start = LOADADDR(.data); __ram_data_end = .; PROVIDE(__ram_data_end = .); _edata = .; PROVIDE (edata = .); + .sbss ALIGN (0x4) : { __sbss_start = ABSOLUTE (.); __SBSS_START__ = ABSOLUTE(.); *(.sbss.*) __SBSS_END__ = ABSOLUTE(.); __SBSSx_START__ = ABSOLUTE(.); *(.sbss*) __SBSSx_END__ = ABSOLUTE(.); *(.scommon*) __sbss_end = ABSOLUTE (.); } > ram + .bss ALIGN (0x10) : { __bss_start = ABSOLUTE (.); . = .; *(.dynbss*) *(.bss*) *(COMMON) __bss_end = ABSOLUTE (.); } > ram + __heap1 = ALIGN (0x8); + . = ALIGN(4); _end = .; PROVIDE (end = .); +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/download.py @@ -0,0 +1,126 @@ +#! /usr/bin/env python + +# +# Copyright (C) 2003, MLB Associates +# + +# This program is used to read a Motorola S-record file and +# download it using the GDB protocol. + +import os, string, sys, time + +trace = open("/tmp/download.trace", "w") + +# +# Use up some time +# +def spin(): + j = 0 + for i in range(0,200): + j = j + 1 + +# +# Compute the checksum for a string +# +def cksum(str): +# sys.stderr.write("cksum %s\n" % str) + sum = 0 + cs = str[1:] + while cs: + sum = sum + ord(cs[:1]) + cs = cs[1:] + return sum & 0xFF + +# +# Send a string via the GDB protocol. Note: this routine +# computes and adds the checksum before starting. +# +def send(str): + str = str + "#%02x" % cksum(str) +# trace.write("ready to send: %s\n" % str) +# trace.flush() + while 1: + s = str + while s: + os.write(1, s[:1]) + spin() + # time.sleep(0.001) + s = s[1:] + c = os.read(0, 1) + if c <> '+': + trace.write("~ACK: %c\n" % c) + trace.write("sent: %s\n" % str) + trace.flush() + continue + res = '' + while 1: + c = os.read(0, 1) + if c == '#': break + res = res + c + # trace.write("ACK: %c, res: %s\n" % (c, res)) + # trace.flush() + # trace.write("res = %s\n" % res) + # trace.flush() + csum = cksum(res) + cs = os.read(0, 1) + cs = cs + os.read(0, 1) + sum = string.atoi(cs, 16) + if csum <> sum: + os.write(1, '-') + trace.write("RES = %s, sum: %x/%x\n" % (res, csum, sum)) + trace.write("sent: %s\n" % str) + trace.flush() + continue + os.write(1, '+') + trace.flush() + return + +# +# Process a stream of S-records, supplied by 'readline()' +# +def download(readline): + # send("$Hc-1") + # send("$Hg0") + last_addr = 0 + while 1: + line = readline() + if not line: break + if line[0] <> 'S': + raise ("Invalid input:" + line) + if line[1] in "123": + len = string.atoi(line[2:4],16) + an = ord(line[1]) - ord('1') + 2 + ae = 4 + (an*2) + addr = string.atoi(line[4:ae],16) + #print "len = %d, addr = 0x%x " % (len, addr) + len = len - (an+1) + line = line[ae:] + out = "$M%x,%x:" % (addr, len) + for i in range(0,len): + val = string.atoi(line[:2],16) + #print "val = 0x%x" % val + line = line[2:] + out = out + "%02x" % val + if (addr - last_addr) >= 0x400: + last_addr = addr + sys.stderr.write("0x%x\n" % addr) + send(out) + elif line[1] in "789": + len = string.atoi(line[2:4],16) + eos = 10 + if line[1] == '7': + eos = 12 + addr = string.atoi(line[4:12],16) + #print "len = %d, addr = 0x%x " % (len, addr) + len = len - 4 + line = line[eos:] + out = "$P40=%08x" % addr + sys.stderr.write("Set PC = 0x%x\n" % addr) + send(out) + # This command starts the program + send("$c#63") + +if __name__ == '__main__': # testing + import sys + if len(sys.argv) > 1: download(open(sys.argv[1]).readline) + else: download(sys.stdin.readline)
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/download_bin.py @@ -0,0 +1,50 @@ +#! /usr/bin/env python + +# +# Copyright (C) 2003, MLB Associates +# + +# This program is used to download a binary file, using the +# raw [minimal] protocol used by the hardware bootstrap on +# the GPS-4020 + +import os, string, sys, time + +# +# Use up some time +# +def spin(): + j = 0 + for i in range(0,2000): + j = j + 1 + +# +# Send a string via the RAW protocol. +# +def send(str): + while 1: + s = str + while s: + c = s[:1] + os.write(1, c) + spin() + # time.sleep(0.001) + s = s[1:] + return + +# +# Process a stream of S-records, supplied by 'read()' +# +def download(read): + line = read(16384) + if not line: return + length = len(line) + # Build up a length descriptor, in big-endian layout + data_length = chr(length >> 16) + chr((length >> 8) & 0xFF) + chr(length & 0xFF) + send(data_length) + send(line) + +if __name__ == '__main__': # testing + import sys + if len(sys.argv) > 1: download(open(sys.argv[1],'rb').read) + else: download(sys.stdin.read)
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/gps4020_download.c @@ -0,0 +1,184 @@ +//------------------------------------------------------------------- +// +// gps4020_download.c +// +//------------------------------------------------------------------- +// +// Copyright (C) 2003, MLB Associates. +// +// Routine to download code into main [external] SRAM and then +// execute it. +// +//------------------------------------------------------------------- + +//#define DEBUG_DOWNLOAD + +extern void tty_init(void); +extern unsigned char tty_getc(int chan); +extern void tty_putc(int chan, char c); +extern void tty_puts(int chan, char *c); +extern void tty_puthex(int chan, unsigned long val, int width); + +typedef int bool; +#define false 0 +#define true 1 + +// Validate a hex character +__inline__ static bool +_is_hex(char c) +{ + return (((c >= '0') && (c <= '9')) || + ((c >= 'A') && (c <= 'F')) || + ((c >= 'a') && (c <= 'f'))); +} + +// Convert a single hex nibble +__inline__ static int +_from_hex(char c) +{ + int ret = 0; + + if ((c >= '0') && (c <= '9')) { + ret = (c - '0'); + } else if ((c >= 'a') && (c <= 'f')) { + ret = (c - 'a' + 0x0a); + } else if ((c >= 'A') && (c <= 'F')) { + ret = (c - 'A' + 0x0A); + } + return ret; +} + + +// +// Process the next hex value from a string +// +unsigned long +_hex(char **_cp) +{ + unsigned long val; + unsigned char *cp = *_cp; + + val = 0; + while (_is_hex(*cp)) { + val = (val << 4) | _from_hex(*cp++); + } + *_cp = cp; + return val; +} + +// +// Simple GDB protocol handler +// Only three commands are handled: +// $M<loc>,<len>:<data...>#<cksum> +// $M20000000,10:0e0000ea18f09fe518f09fe518f09fe5#59 +// $P<reg>=<val>#<cksum> +// $c#<cksum> +// <cksum> is a simple accumulation of all of the ASCII +// characters following the "$" + +static char +_getc(void) +{ + char c; + c = tty_getc(0); +#ifdef DEBUG_DOWNLOAD + tty_putc(1, c); +#endif + return c; +} + +void +GDB_protocol(void) +{ + char c; + unsigned char cksum, _cksum; + unsigned char line[64]; + char *cp; + bool eol, ok; + unsigned char *loc; + unsigned long len; + unsigned char val; + void (*entry_address)(void); + + while (true) { + // Wait for a '$' + do { + c = _getc(); + // HACK - '>>' indicates to jump to FLASH/ROM + if (c == '>') { + c = _getc(); + if (c == '>') { + entry_address = (void *)0x60000000; + (*entry_address)(); + } + } + } while (c != '$'); + cksum = 0; + eol = false; + cp = line; + while (!eol) { + c = _getc(); + if (c != '#') { + cksum += c; + *cp++ = c; + *cp = '\0'; + } else { + c = _getc(); + _cksum = _from_hex(c) << 4; + c = _getc(); + _cksum |= _from_hex(c); + ok = (cksum == _cksum); + tty_putc(0, ok ? '+' : '-'); + eol = true; + } + } +#ifdef DEBUG_DOWNLOAD + tty_puts(1, ok ? " = OK\n" : " = BAD\n"); +#endif + if (ok) { + // Empty "OK" message + tty_puts(0, "#00"); + // Process command + cp = line; + switch (*cp++) { + case 'M': + loc = (unsigned char *)_hex(&cp); + if (*cp++ != ',') continue; + len = _hex(&cp); + if (*cp++ != ':') continue; + while (len-- > 0) { + val = _from_hex(*cp++) << 4; + val |= _from_hex(*cp++); + *loc++ = val; + } + break; + case 'P': + // Ignore register # + cp += 2; + if (*cp++ != '=') continue; + entry_address = (void *)_hex(&cp); + break; + case 'c': + (*entry_address)(); + break; + default: + tty_puts(0, "** unknown command: $"); + tty_puts(0, line); + } + } + } +} + +int +main(void) +{ + tty_init(); + // Change 0x6XXXXXXX to use external ROM + *(volatile short *)0x4010100C |= (1<<9); + tty_puts(0, "Ready to download >>"); +#ifdef DEBUG_DOWNLOAD + tty_puts(1, "... GDB data:\n"); +#endif + GDB_protocol(); + return 0; // Never happens! +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/gps4020_start.S @@ -0,0 +1,216 @@ +//------------------------------------------------------------------- +// +// gp4020_start.S +// +//------------------------------------------------------------------- +// +// Copyright (C) 2003, MLB Associates. +// +// This file contains basic startup code for the GPS4020 platform. +// After initialization, it will call a single "C" function 'main()' +// +// Note: this program assumes that it has been downloaded into the +// on-chip SRAM via the BOOTSTRAP mechanism, so on-chip SRAM is +// located at address 0x00000000 and external ROM/FLASH is at +// address 0x60000000 +// + + .macro lab,lbl +.\lbl: .long \lbl + .endm + + .macro blr + mov pc,lr + .endm + + .equ MPC_BASE_ADDRESS, 0xE0008000 + .equ MPC_AREA1_CONFIG, 0x00000000 + .equ MPC_AREA2_CONFIG, 0x00000004 + .equ MPC_AREA3_CONFIG, 0x00000008 + .equ MPC_AREA4_CONFIG, 0x0000000C + .equ GPIO_BASE_ADDRESS, 0xE0005000 + .equ GPIO_DIRECTION_REG_OFFSET,0x00000000 + .equ GPIO_READ_REG_OFFSET, 0x00000004 + .equ GPIO_WRITE_REG_OFFSET, 0x00000008 + .equ UART1_BASE_ADDRESS, 0xE0018000 + .equ UART_TXBUF, 0x00000010 + .equ UART_STATUS, 0x0000000C + .equ UART_STATUS_TXEMPTY, 0x00000002 + + .text + .global __exception_handlers +__exception_handlers: + b reset // 0x00 + ldr pc,.undefined_instruction // 0x04 + ldr pc,.software_interrupt // 0x08 start && software int + ldr pc,.abort_prefetch // 0x0C + ldr pc,.abort_data // 0x10 + .word 0 // unused + ldr pc,.IRQ // 0x18 + ldr pc,.FIQ // 0x1C + + .global vectors +vectors: + .long reset // 0x20 + lab undefined_instruction // 0x24 + lab software_interrupt // 0x28 + lab abort_prefetch // 0x2C + lab abort_data // 0x30 + .word 0 // 0x34 + lab IRQ // 0x38 + lab FIQ // 0x3C + + .arm @ AKA ".code32" + .align 2 @ Align code on 2^2 = 4 byte intervals + + .global start +start: +reset: + +/*--------------------------------------------------------------------------*/ +// Setup the GPIO and the ARM registers + +// make GPIO[0..7] outputs - note: GPIO4 is used for Rx on UART1! + + ldr r1,=GPIO_BASE_ADDRESS + ldr r0, [r1,#GPIO_DIRECTION_REG_OFFSET] + and r0, r0, #0b00010000 @ 0 = output, 1 = input + str r0, [r1,#GPIO_DIRECTION_REG_OFFSET] @ Store value (DON'T use strb) + + ldr r1,=MPC_BASE_ADDRESS + ldr r2,=0xFF00002D // 0x6xxxxxxx, 16bit R/W RAM + str r2,[r1,#MPC_AREA1_CONFIG] + + ldr r1,=MPC_BASE_ADDRESS + ldr r2,=0x00000069 // 0x2xxxxxxx, 16bit R/W RAM + str r2,[r1,#MPC_AREA2_CONFIG] + + ldr r2,[r1,#MPC_AREA3_CONFIG] + ldr r2,=0x00000021 // 0x4xxxxxxx, 16bit peripheral + str r2,[r1,#MPC_AREA3_CONFIG] + + ldr r2,[r1,#MPC_AREA4_CONFIG] + ldr r2,=0x0000006E // 0x0xxxxxxx, 32bit memory + str r2,[r1,#MPC_AREA4_CONFIG] + + ldr sp,=_stack + bl main + +10: ldr r1,=GPIO_BASE_ADDRESS + mov r0,#0 + str r0, [r1,#GPIO_WRITE_REG_OFFSET] + b 10b + +// +// Exception handlers +// +undefined_instruction: // 0x24 + mov r0,#0x24 + b exception +software_interrupt: // 0x28 + mov r0,#0x28 + b exception +abort_prefetch: // 0x2C + mov r0,#0x2C + b exception +abort_data: // 0x30 + mov r0,#0x30 + b exception +IRQ: // 0x38 + mov r0,#0x38 + b exception +FIQ: // 0x3C + mov r0,#0x3C + b exception + +exception: + mov r8,lr // Location of failure + mov r9,r0 +00: + ldr r1,=GPIO_BASE_ADDRESS + str r9, [r1,#GPIO_WRITE_REG_OFFSET] + ldr r3,=0x100000 +10: nop + sub r3,r3,#1 + cmp r3,#0 + bne 10b + str r3,[r1,#GPIO_WRITE_REG_OFFSET] + ldr r3,=0x80000 +20: nop + sub r3,r3,#1 + cmp r3,#0 + bne 20b + + ldr r1,=msg + bl _puts + mov r1,r8,lsr #24 + bl _puthex + mov r1,r8,lsr #16 + bl _puthex + mov r1,r8,lsr #8 + bl _puthex + mov r1,r8 + bl _puthex + mov r0,#'\n' + bl _putc + mov r0,#'\r' + bl _putc + b 00b + +// +// Write the character in r0 +// +_putc: + ldr r2,=UART1_BASE_ADDRESS +10: ldrb r3,[r2,#UART_STATUS] + and r3,r3,#UART_STATUS_TXEMPTY + cmp r3,#0 + beq 10b + strb r0,[r2,#UART_TXBUF] + blr + +// +// Write the string pointed to by r1 +// +_puts: + mov r7,lr +10: ldrb r0,[r1],#1 + cmp r0,#0 + moveq pc,r7 + bl _putc + b 10b + +// +// Print the byte in r1 in hex +// +_puthex: + mov r7,lr + mov r2,r1,lsr #4 + and r2,r2,#0x0F + cmp r2,#0x0A + addge r2,r2,#'A'-'0'-0x0A + add r0,r2,#'0' + bl _putc + and r2,r1,#0x0F + cmp r2,#0x0A + addge r2,r2,#'A'-'0'-0x0A + add r0,r2,#'0' + bl _putc + mov lr,r7 + blr + +msg: .string "PC=0x" + + .section ".data" + .align 2 +_leds: .long 0x77 + + .section ".bss" +_stack_base: + .rept 512 + .byte 0 + .endr + .balign 16 +_stack: + + .end
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/gps4020/current/support/download/tty.c @@ -0,0 +1,204 @@ +// +// TTY support code +// + +struct uart { + unsigned char control; + unsigned char _fill0[3]; + unsigned char mode; + unsigned char _fill1[3]; + unsigned char baud; + unsigned char _fill2[3]; + unsigned char status; + unsigned char _fill3[3]; + unsigned char TxRx; + unsigned char _fill4[3]; + unsigned char modem_control; + unsigned char _fill5[3+8]; + unsigned char modem_status; + unsigned char _fill6[3]; +}; + +// Serial control +#define SCR_MIE 0x80 // Modem interrupt enable +#define SCR_EIE 0x40 // Error interrupt enable +#define SCR_TIE 0x20 // Transmit interrupt enable +#define SCR_RIE 0x10 // Receive interrupt enable +#define SCR_FCT 0x08 // Flow type 0=>software, 1=>hardware +#define SCR_CLK 0x04 // Clock source 0=internal, 1=external +#define SCR_TEN 0x02 // Transmitter enabled +#define SCR_REN 0x01 // Receiver enabled +// Serial mode +#define SMR_DIV(x) ((x)<<4) // Clock divisor +#define SMR_STOP 0x08 // Stop bits 0=>one, 1=>two +#define SMR_STOP_1 0x00 +#define SMR_STOP_2 0x08 +#define SMR_PARITY 0x04 // Parity mode 0=>even, 1=odd +#define SMR_PARITY_EVEN 0x00 +#define SMR_PARITY_ODD 0x04 +#define SMR_PARITY_ON 0x02 // Parity checked +#define SMR_PARITY_OFF 0x00 +#define SMR_LENGTH 0x01 // Character length +#define SMR_LENGTH_8 0x00 +#define SMR_LENGTH_7 0x01 +// Serial status +#define SSR_MSS 0x80 // Modem status has changed +#define SSR_OE 0x40 // Overrun error +#define SSR_FE 0x20 // Framing error +#define SSR_PE 0x10 // Parity error +#define SSR_TxActive 0x08 // Transmitter is active +#define SSR_RxActive 0x04 // Receiver is active +#define SSR_TxEmpty 0x02 // Tx buffer is empty +#define SSR_RxFull 0x01 // Rx buffer contains data +// Modem control +#define SMR_CFG 0x08 // Configuration 0=>normal, 1=>null +#define SMR_MSU 0x04 // Modem status update 1=>enable +#define SMR_DTR 0x02 // Assert DTR +#define SMR_RTS 0x01 // Assert RTS + +#define GP4020_UART1 0xE0018000 +#define GP4020_UART2 0xE0019000 + +// +// Initialize a TTY port +// +static void +_tty_init(volatile struct uart *uart) +{ + uart->mode = SMR_STOP_1 | SMR_PARITY_OFF | SMR_LENGTH_8; + uart->baud = 0x15; // Magic for 57600 + uart->modem_control = SMR_DTR | SMR_RTS; + uart->control = SCR_TEN | SCR_REN; +} + +// +// Output a character to a TTY port +// +static void +_tty_putc(volatile struct uart *uart, char c) +{ + // Wait for space for character + do { + } while ((uart->status & SSR_TxEmpty) == 0); + uart->TxRx = c; +} + +// +// Read a character from a TTY port +// +static char +_tty_getc(volatile struct uart *uart) +{ + do { +#if 0 + if ((uart->status & 0xF0) != 0) { + tty_puts("\nErr = "); + tty_puthex(uart->TxRx, 2); + } +#endif + } while ((uart->status & SSR_RxFull) == 0); + return uart->TxRx; +} + +// +// Initialize the TTY ports +// +volatile struct uart *uarts[] = { + (volatile struct uart *)GP4020_UART1, + (volatile struct uart *)GP4020_UART2 +}; + +void +tty_init(void) +{ + +#if 0 + tty_puts("\nUart: "); + tty_puthex(uart->control, 2); + tty_puts(", "); + tty_puthex(uart->mode, 2); + tty_puts(", "); + tty_puthex(uart->baud, 2); + tty_puts(", "); + tty_puthex(uart->TxRx, 2); + tty_puts("\n"); + tty_puts("\nStat at "); tty_puthex(&uart->status, 8); tty_puts("\n"); +#endif + _tty_init(uarts[0]); + _tty_init(uarts[1]); +} + +// +// Write a character to the selected TTY +// +void +tty_putc(int chan, char c) +{ + _tty_putc(uarts[chan], c); +} + +// +// Read a character from the selected TTY +// +char +tty_getc(int chan) +{ + return _tty_getc(uarts[chan]); +} + +// +// Display a string on the selected TTY +// +void +tty_puts(int chan, char *s) +{ + char c; + + while ((c = *s++) != '\0') { + if (c == '\n') { + tty_putc(chan, '\r'); + } + tty_putc(chan, c); + } +} + +// +// Read characters into a buffer, terminated by a '\n' character +// Note: the '\n' character is not stored +// +int +tty_getline(int chan, char *buf) +{ + char c; + int len = 0; + + while (((c = tty_getc(chan)) != '\n') && (c != '\r')) { + tty_putc(chan, c); + *buf++ = c; + len++; + } + *buf = '\0'; + return len; +} + +// +// Display a number in hex +// +void +tty_puthex(int chan, unsigned long val, int length) +{ + char hex[] = "0123456789ABCDEF"; + char str[16]; + char *s = &str[length+3]; + int i; + + *--s = '\0'; + for (i = 0; i < length; i++) { + *--s = hex[(val & 0x0F)]; + val >>= 4; + } + *--s = 'x'; + *--s = '0'; + tty_puts(chan, s); +} +