Mercurial > flash_v2
changeset 30:641b639be825 ecos-sw-1999-08-16
Merge from eCos master repository on 1999-08-16-22:01:37-BST
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,9 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * packages: + * targets: + Rename all mentions of am32 to am31 + 1999-06-09 Gary Thomas <gthomas@cygnus.co.uk> * pkgconf.tcl (pkgconf::produce_misc_files): MLT files need
--- a/packages/hal/arm/arch/current/include/hal_io.h +++ b/packages/hal/arm/arch/current/include/hal_io.h @@ -48,6 +48,7 @@ // //============================================================================= +#include <pkgconf/system.h> #include <cyg/infra/cyg_type.h> //----------------------------------------------------------------------------- @@ -132,7 +133,8 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG // Enforce a flow "barrier" to prevent optimizing compiler from reordering // operations. #define HAL_IO_BARRIER() - + + //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_IO_H // End of hal_io.h
--- a/packages/hal/arm/pid/current/ChangeLog +++ b/packages/hal/arm/pid/current/ChangeLog @@ -1,3 +1,9 @@ +1999-08-16 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_arm_pid.h: + + Proper case various display strings. + 1999-05-24 Gary Thomas <gthomas@cygnus.co.uk> * src/hal_diag.c: Clean up direct hardware access code.
--- a/packages/hal/arm/pid/current/include/pkgconf/hal_arm_pid.h +++ b/packages/hal/arm/pid/current/include/pkgconf/hal_arm_pid.h @@ -80,7 +80,7 @@ /* --------------------------------------------------------------------- {{CFG_DATA cdl_option CYGHWR_HAL_ARM_PID_DIAG_PORT { - display "Diagnostic Serial Port" + display "Diagnostic serial port" parent CYGPKG_HAL_ARM_PID type enum legal_values 0 1 @@ -95,7 +95,7 @@ /* --------------------------------------------------------------------- {{CFG_DATA cdl_option CYGHWR_HAL_ARM_PID_DIAG_BAUD { - display "Diagnostic Serial Port Baud Rate" + display "Diagnostic serial port baud rate" parent CYGPKG_HAL_ARM_PID type enum legal_values 9600 19200 38400 115200 @@ -111,7 +111,7 @@ /* --------------------------------------------------------------------- {{CFG_DATA cdl_option CYGHWR_HAL_ARM_PID_GDB_PORT { - display "GDB Serial Port" + display "GDB serial port" parent CYGPKG_HAL_ARM_PID type enum legal_values 0 1 @@ -127,7 +127,7 @@ /* --------------------------------------------------------------------- {{CFG_DATA cdl_option CYGHWR_HAL_ARM_PID_GDB_BAUD { - display "GDB Serial Port Baud Rate" + display "GDB serial port baud rate" parent CYGPKG_HAL_ARM_PID type enum legal_values 9600 19200 38400 115200
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/pid/current/misc/STUBS_config @@ -0,0 +1,31 @@ +#! /bin/sh + +# Configure ARM/AEB eCos to create PID GDB stubs + + +tcl $1/pkgconf.tcl \ + --target=arm --platform=pid --startup=stubs \ + --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ + --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ + --disable CYGPKG_ERROR --disable CYGPKG_IO \ + --disable CYGPKG_IO_SERIAL --disable CYGPKG_DEVICES_WALLCLOCK \ + --disable CYGPKG_DEVICES_WATCHDOG + +patch <<END_OF_PATCH -p0 +--- pkgconf/hal.h~ Thu Jul 8 08:26:44 1999 ++++ pkgconf/hal.h Wed Jul 28 10:51:07 1999 +@@ -369,10 +369,10 @@ + + }}CFG_DATA */ + +-#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++#define CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + #undef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + + /* + * NOTE: +END_OF_PATCH
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,12 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal.h: Rename CYG_HAL_MN10300_AM32_STDEVAL1 to + CYG_HAL_MN10300_AM31_STDEVAL1 + +1999-08-13 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_stub.c: Removed superfluous trace() extern. + 1999-08-06 Jesper Skov <jskov@cygnus.co.uk> * src/generic-stub.c (__process_packet): FLush and clear caches
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -402,7 +402,7 @@ #define CYG_HAL_USE_ROM_MONITOR #define CYG_HAL_USE_ROM_MONITOR_CYGMON #endif -#if defined(CYG_HAL_MN10300_STDEVAL1) && defined(CYG_HAL_STARTUP_RAM) +#if defined(CYG_HAL_MN10300_AM31_STDEVAL1) && defined(CYG_HAL_STARTUP_RAM) #define CYG_HAL_USE_ROM_MONITOR #define CYG_HAL_USE_ROM_MONITOR_CYGMON #endif @@ -440,13 +440,6 @@ * * NOTE: Currently the code also needs these #defines. */ -#ifdef CYG_HAL_MN10300_STDEVAL1 -# define CYG_HAL_MN10300_MN103002 -#endif -#ifdef CYG_HAL_MN10300_SIM -# define CYG_HAL_MN10300_MN103002 -#endif - #ifdef CYG_HAL_POWERPC_COGENT # define CYG_HAL_POWERPC_MPC8xx # define CYG_HAL_POWERPC_MPC860 @@ -462,7 +455,7 @@ #endif -#ifdef CYGPKG_HAL_MIPS +#if defined(CYGPKG_HAL_MIPS) || defined(CYGPKG_HAL_MN10300) #include CYGBLD_HAL_TARGET_H #endif
--- a/packages/hal/common/current/src/hal_stub.c +++ b/packages/hal/common/current/src/hal_stub.c @@ -117,7 +117,9 @@ void #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT -#if (HAL_BREAKINST_SIZE == 2) +#if (HAL_BREAKINST_SIZE == 1) +typedef cyg_uint8 t_inst; +#elif (HAL_BREAKINST_SIZE == 2) typedef cyg_uint16 t_inst; #elif (HAL_BREAKINST_SIZE == 4) typedef cyg_uint32 t_inst; @@ -421,11 +423,6 @@ int break; case CACHE_FLUSH: HAL_ICACHE_SYNC(); -#ifndef CYGPKG_HAL_MIPS - // SYNC and INVALIDATE_ALL are the same on the MIPS, - // so avoid doing it twice. - HAL_ICACHE_INVALIDATE_ALL(); -#endif break; case CACHE_NOOP: /* fall through */ @@ -457,11 +454,6 @@ int break; case CACHE_FLUSH: HAL_DCACHE_SYNC(); -#ifndef CYGPKG_HAL_MIPS - // SYNC and INVALIDATE_ALL are the same on the MIPS, - // so avoid doing it twice. - HAL_DCACHE_INVALIDATE_ALL(); -#endif break; case CACHE_NOOP: /* fall through */
--- a/packages/hal/i386/linux/current/ChangeLog +++ b/packages/hal/i386/linux/current/ChangeLog @@ -1,3 +1,9 @@ +1999-08-16 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_i386_linux.h: + + Proper case package display string. + 1999-05-20 Gary Thomas <gthomas@cygnus.co.uk> * include/pkgconf/hal_i386_linux.h: Move RTC setup here.
--- a/packages/hal/i386/linux/current/include/pkgconf/hal_i386_linux.h +++ b/packages/hal/i386/linux/current/include/pkgconf/hal_i386_linux.h @@ -46,7 +46,7 @@ {{CFG_DATA cdl_package CYGPKG_HAL_I386_LINUX { - display "Linux i386 Synthetic Target" + display "Linux i386 synthetic target" type radio parent CYGPKG_HAL_I386 platform linux
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mipsfp.c (cyg_hal_mips_process_fpe): CYG_REPORT_FUNCNAMETYPE() + must be first in a C file + 1999-07-15 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/arch.inc (hal_fpu_save_caller): Save fcr31 first as
--- a/packages/hal/mips/arch/current/src/mipsfp.c +++ b/packages/hal/mips/arch/current/src/mipsfp.c @@ -285,14 +285,14 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis cyg_uint8 computational_insn=1; // computational FP instruction cyg_bool delay_slot; // did it happen in a delay slot + CYG_REPORT_FUNCNAMETYPE("cyg_hal_mips_process_fpe", "returning %d"); + CYG_CHECK_DATA_PTR( regs, "cyg_hal_mips_process_fpe() called with invalid regs ptr"); CYG_PRECONDITION( (regs->vector>>2) == CYGNUM_HAL_VECTOR_FPE, "Asked to process non-FPE exception"); - CYG_REPORT_FUNCNAMETYPE("cyg_hal_mips_process_fpe", "returning %d"); - // First of all, we only handle the unimplemented operation exception // here, so if we don't have that, we just exit if ((regs->fcr31 & FCR31_CAUSE_E) == 0) {
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/ChangeLog @@ -0,0 +1,69 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + Copy entire package from hal/mn10300/am32 + + * include/pkgconf/hal_mn10300_am31.h: + * include/variant.inc: + * include/var_intr.h: + * include/var_arch.h: + * include/var_cache.h: + * src/PKGconf.mak: + * src/mn10300_am31.ld + * src/var_misc.c: + Rename all files and contents of files that mention am32, to am31 + +1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * include/var_intr.h: Fixed up some typos. + + * include/variant.inc: Moved diagnostic data here into a macro. + +1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal_mn10300_am32.h: + reparent CYGPKG_HAL_MN10300_AM32 under CYGPKG_HAL_MN10300_VARIANTS + +1999-07-30 Nick Garnett <nickg@cygnus.co.uk> + + * include/var_intr.h: Moved HAL_INTERRUPT_CONFIGURE() here since + it now has to be variant-specific. + Reorganized and renumbered exceptions. + +1999-07-27 Nick Garnett <nickg@cygnus.co.uk> + + * include/variant.inc: Changed all *_MIPS_* macros to *_MN10300_*. + Added definition of DCR_DE bit. + +1999-07-08 Nick Garnett <nickg@cygnus.co.uk> + + * include/variant.inc: + Added definitions of NMICR, DCR and ISR addresses. + Added hal_cpu_clear_nmid macro. + +1999-07-07 Nick Garnett <nickg@cygnus.co.uk> + + * include/variant.inc: + Added macros to get and set PSW in a CPU specific way. + +1999-06-30 Nick Garnett <nickg@cygnus.co.uk> + + * src/var_misc.c (cyg_hal_dcache_store): + changed name of symbol for testing for SIM build. + + * include/variant.inc: + Added CPU register save and restore macros. + +1999-06-29 Nick Garnett <nickg@cygnus.co.uk> + + * include/var_arch.h: + * include/var_intr.h: + * include/var_cache.h: + * include/variant.inc: + * include/pkgconf/hal_mn10300_am32.h: + * src/PKGconf.mak: + * src/mn10300_am32.ld: + * src/var_misc.c: + Added these files to contain AM32 variant implementations of the + HAL. + +
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/include/pkgconf/hal_mn10300_am31.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_PKGCONF_HAL_MN10300_AM31_H +#define CYGONCE_PKGCONF_HAL_MN10300_AM31_H +// ==================================================================== +// +// pkgconf/hal_mn10300_am31.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 1998-09-02 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_MN10300_AM31 { + display "MN10300 AM31 variant" + type radio + parent CYGPKG_HAL_MN10300_VARIANTS + target mn10300_am31 + description " + The MN10300 AM31 variant HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + } + + }}CFG_DATA */ + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_MN10300_AM31_H */ +/* EOF hal_mn10300_am31.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/include/var_arch.h @@ -0,0 +1,52 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//========================================================================== +// +// var_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1999-02-17 +// Purpose: Define architecture abstractions +// Description: This file contains any extra or modified definitions for +// this variant of the architecture. +// Usage: #include <cyg/hal/var_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// End of var_arch.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/include/var_cache.h @@ -0,0 +1,272 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H + +//============================================================================= +// +// var_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/var_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +//#include <cyg/hal/plf_cache.h> + +//============================================================================= +// MN103002 implementation + +//----------------------------------------------------------------------------- +// Cache dimensions + + +// Data cache +#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Control registers + +#define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070) + +#define HAL_CHCTR_ICEN 0x0001 +#define HAL_CHCTR_DCEN 0x0002 +#define HAL_CHCTR_ICBUSY 0x0004 +#define HAL_CHCTR_DCBUSY 0x0008 +#define HAL_CHCTR_ICINV 0x0010 +#define HAL_CHCTR_DCINV 0x0020 +#define HAL_CHCTR_DCWTMD 0x0040 +#define HAL_CHCTR_ICWMD 0x0300 +#define HAL_CHCTR_DCWMD 0x3000 + +#define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000) +#define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + chctr |= HAL_CHCTR_DCEN; \ + *HAL_CHCTR = chctr; \ +} + +// Disable the data cache +#define HAL_DCACHE_DISABLE() \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + chctr &= ~HAL_CHCTR_DCEN; \ + *HAL_CHCTR = chctr; \ + while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ +} + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \ +} + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRWORD chctr; \ + register CYG_ADDRWORD state; \ + HAL_DCACHE_IS_ENABLED(state); \ + if (state) \ + HAL_DCACHE_DISABLE(); \ + chctr = *HAL_CHCTR; \ + chctr |= HAL_CHCTR_DCINV; \ + *HAL_CHCTR = chctr; \ + while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ + if (state) \ + HAL_DCACHE_ENABLE(); \ +} + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS ) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +#define HAL_DCACHE_WRITE_MODE( _mode_ ) \ +{ \ + register CYG_ADDRWORD chctr; \ + register CYG_ADDRWORD state; \ + HAL_DCACHE_IS_ENABLED(state); \ + if (state) \ + HAL_DCACHE_DISABLE(); \ + chctr = *HAL_CHCTR; \ + chctr |= HAL_CHCTR_DCWTMD*(_mode_); \ + *HAL_CHCTR = chctr; \ + while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ + if (state) \ + HAL_DCACHE_ENABLE(); \ +} + +#define HAL_DCACHE_WRITEBACK_MODE 0 +#define HAL_DCACHE_WRITETHRU_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. + +// This functionality requires 4 register variables. To prevent register +// spilling, put the code in a separate function. +externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size); + +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ + cyg_hal_dcache_store((_base_), (_size_)) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + chctr |= HAL_CHCTR_ICEN; \ + *HAL_CHCTR = chctr; \ +} + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + chctr &= ~HAL_CHCTR_ICEN; \ + *HAL_CHCTR = chctr; \ + while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \ +} + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ +{ \ + register CYG_ADDRWORD chctr = *HAL_CHCTR; \ + _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \ +} + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() \ +{ \ + register CYG_ADDRWORD chctr; \ + register CYG_ADDRWORD state; \ + HAL_ICACHE_IS_ENABLED(state); \ + if (state) \ + HAL_ICACHE_DISABLE(); \ + chctr = *HAL_CHCTR; \ + chctr |= HAL_CHCTR_ICINV; \ + *HAL_CHCTR = chctr; \ + while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \ + if (state) \ + HAL_ICACHE_ENABLE(); \ +} + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/include/var_intr.h @@ -0,0 +1,400 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// var_intr.h +// +// AM31 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: AM31 Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for AM31 variants of the MN10300 +// architecture. +// +// Usage: +// #include <cyg/hal/var_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_intr.h> + +//-------------------------------------------------------------------------- + +// The MN10300 has a somewhat complex interrupt structure. Besides the +// reset and NMI vectors there are seven maskable interrupt vectors +// which must point to code in the 64k starting at 0x40000000. There +// are also 25 Interrupt control groups, each of which can have 4 +// interrupt lines attached, for a theoretical total of 100 interrupts +// (!). Some of these are dedicated to specific devices, other to +// external pins, and others are not connected to anything, resulting +// in only 45 that can actually be delivered. Each control group may +// be assigned one of seven interrupt levels, and is delivered to the +// corresponding vector. Software can then use a register to determine +// the delivering group and detect from there which interrupt has been +// delivered. +// +// The approach we will adopt at present is for the code attached to +// each vector to save state and jump via a table to a VSR. The +// default VSR will fully decode the delivered interrupt into a table +// of isr/data/object entries. VSR replacement will operate on the +// first level indirection table rather than the hardware +// vectors. This is the fastest mechanism, however it needs 100*3*4 + +// 7*4 = 1228 bytes for the tables. +// + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +// The level-specific hardware vectors +// These correspond to VSRs and are the values to use for HAL_VSR_GET/SET +#define CYGNUM_HAL_VECTOR_0 0 +#define CYGNUM_HAL_VECTOR_1 1 +#define CYGNUM_HAL_VECTOR_2 2 +#define CYGNUM_HAL_VECTOR_3 3 +#define CYGNUM_HAL_VECTOR_4 4 +#define CYGNUM_HAL_VECTOR_5 5 +#define CYGNUM_HAL_VECTOR_6 6 +#define CYGNUM_HAL_VECTOR_NMI_ENTRY 7 +#define CYGNUM_HAL_VECTOR_TRAP 8 +#define CYGNUM_HAL_VECTOR_NMI 9 +#define CYGNUM_HAL_VECTOR_WATCHDOG 10 +#define CYGNUM_HAL_VECTOR_SYSTEM_ERROR 11 + +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 11 +#define CYGNUM_HAL_VSR_COUNT 12 + +// Exception numbers. These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception() + +#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI +#define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG +#define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR CYGNUM_HAL_VECTOR_SYSTEM_ERROR + +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR + +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_EXCEPTION_COUNT CYGNUM_HAL_VSR_COUNT + +// The decoded interrupts + +#define CYGNUM_HAL_INTERRUPT_NMIRQ 0 +#define CYGNUM_HAL_INTERRUPT_WATCHDOG 1 +#define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2 +#define CYGNUM_HAL_INTERRUPT_RESERVED_3 3 + +#define CYGNUM_HAL_INTERRUPT_RESERVED_4 4 +#define CYGNUM_HAL_INTERRUPT_RESERVED_5 5 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6 6 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7 7 + +#define CYGNUM_HAL_INTERRUPT_TIMER_0 8 +#define CYGNUM_HAL_INTERRUPT_RESERVED_9 9 +#define CYGNUM_HAL_INTERRUPT_RESERVED_10 10 +#define CYGNUM_HAL_INTERRUPT_RESERVED_11 11 + +#define CYGNUM_HAL_INTERRUPT_TIMER_1 12 +#define CYGNUM_HAL_INTERRUPT_RESERVED_13 13 +#define CYGNUM_HAL_INTERRUPT_RESERVED_14 14 +#define CYGNUM_HAL_INTERRUPT_RESERVED_15 15 + +#define CYGNUM_HAL_INTERRUPT_TIMER_2 16 +#define CYGNUM_HAL_INTERRUPT_RESERVED_17 17 +#define CYGNUM_HAL_INTERRUPT_RESERVED_18 18 +#define CYGNUM_HAL_INTERRUPT_RESERVED_19 19 + +#define CYGNUM_HAL_INTERRUPT_TIMER_3 20 +#define CYGNUM_HAL_INTERRUPT_RESERVED_21 21 +#define CYGNUM_HAL_INTERRUPT_RESERVED_22 22 +#define CYGNUM_HAL_INTERRUPT_RESERVED_23 23 + +#define CYGNUM_HAL_INTERRUPT_TIMER_4 24 +#define CYGNUM_HAL_INTERRUPT_RESERVED_25 25 +#define CYGNUM_HAL_INTERRUPT_RESERVED_26 26 +#define CYGNUM_HAL_INTERRUPT_RESERVED_27 27 + +#define CYGNUM_HAL_INTERRUPT_TIMER_5 28 +#define CYGNUM_HAL_INTERRUPT_RESERVED_29 29 +#define CYGNUM_HAL_INTERRUPT_RESERVED_30 30 +#define CYGNUM_HAL_INTERRUPT_RESERVED_31 31 + +#define CYGNUM_HAL_INTERRUPT_TIMER_6 32 +#define CYGNUM_HAL_INTERRUPT_RESERVED_33 33 +#define CYGNUM_HAL_INTERRUPT_RESERVED_34 34 +#define CYGNUM_HAL_INTERRUPT_RESERVED_35 35 + +#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A 36 +#define CYGNUM_HAL_INTERRUPT_RESERVED_37 37 +#define CYGNUM_HAL_INTERRUPT_RESERVED_38 38 +#define CYGNUM_HAL_INTERRUPT_RESERVED_39 39 + +#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B 40 +#define CYGNUM_HAL_INTERRUPT_RESERVED_41 41 +#define CYGNUM_HAL_INTERRUPT_RESERVED_42 42 +#define CYGNUM_HAL_INTERRUPT_RESERVED_43 43 + +#define CYGNUM_HAL_INTERRUPT_RESERVED_44 44 +#define CYGNUM_HAL_INTERRUPT_RESERVED_45 45 +#define CYGNUM_HAL_INTERRUPT_RESERVED_46 46 +#define CYGNUM_HAL_INTERRUPT_RESERVED_47 47 + +#define CYGNUM_HAL_INTERRUPT_DMA0 48 +#define CYGNUM_HAL_INTERRUPT_RESERVED_49 49 +#define CYGNUM_HAL_INTERRUPT_RESERVED_50 50 +#define CYGNUM_HAL_INTERRUPT_RESERVED_51 51 + +#define CYGNUM_HAL_INTERRUPT_DMA1 52 +#define CYGNUM_HAL_INTERRUPT_RESERVED_53 53 +#define CYGNUM_HAL_INTERRUPT_RESERVED_54 54 +#define CYGNUM_HAL_INTERRUPT_RESERVED_55 55 + +#define CYGNUM_HAL_INTERRUPT_DMA2 56 +#define CYGNUM_HAL_INTERRUPT_RESERVED_57 57 +#define CYGNUM_HAL_INTERRUPT_RESERVED_58 58 +#define CYGNUM_HAL_INTERRUPT_RESERVED_59 59 + +#define CYGNUM_HAL_INTERRUPT_DMA3 60 +#define CYGNUM_HAL_INTERRUPT_RESERVED_61 61 +#define CYGNUM_HAL_INTERRUPT_RESERVED_62 62 +#define CYGNUM_HAL_INTERRUPT_RESERVED_63 63 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 64 +#define CYGNUM_HAL_INTERRUPT_RESERVED_65 65 +#define CYGNUM_HAL_INTERRUPT_RESERVED_66 66 +#define CYGNUM_HAL_INTERRUPT_RESERVED_67 67 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 68 +#define CYGNUM_HAL_INTERRUPT_RESERVED_69 69 +#define CYGNUM_HAL_INTERRUPT_RESERVED_70 70 +#define CYGNUM_HAL_INTERRUPT_RESERVED_71 71 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 72 +#define CYGNUM_HAL_INTERRUPT_RESERVED_73 73 +#define CYGNUM_HAL_INTERRUPT_RESERVED_74 74 +#define CYGNUM_HAL_INTERRUPT_RESERVED_75 75 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 76 +#define CYGNUM_HAL_INTERRUPT_RESERVED_77 77 +#define CYGNUM_HAL_INTERRUPT_RESERVED_78 78 +#define CYGNUM_HAL_INTERRUPT_RESERVED_79 79 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 80 +#define CYGNUM_HAL_INTERRUPT_RESERVED_81 81 +#define CYGNUM_HAL_INTERRUPT_RESERVED_82 82 +#define CYGNUM_HAL_INTERRUPT_RESERVED_83 83 + +#define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 84 +#define CYGNUM_HAL_INTERRUPT_RESERVED_85 85 +#define CYGNUM_HAL_INTERRUPT_RESERVED_86 86 +#define CYGNUM_HAL_INTERRUPT_RESERVED_87 87 + +#define CYGNUM_HAL_INTERRUPT_RESERVED_88 88 +#define CYGNUM_HAL_INTERRUPT_RESERVED_89 89 +#define CYGNUM_HAL_INTERRUPT_RESERVED_90 90 +#define CYGNUM_HAL_INTERRUPT_RESERVED_91 91 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 92 +#define CYGNUM_HAL_INTERRUPT_RESERVED_93 93 +#define CYGNUM_HAL_INTERRUPT_RESERVED_94 94 +#define CYGNUM_HAL_INTERRUPT_RESERVED_95 95 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 96 +#define CYGNUM_HAL_INTERRUPT_RESERVED_97 97 +#define CYGNUM_HAL_INTERRUPT_RESERVED_98 98 +#define CYGNUM_HAL_INTERRUPT_RESERVED_99 99 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 100 +#define CYGNUM_HAL_INTERRUPT_RESERVED_101 101 +#define CYGNUM_HAL_INTERRUPT_RESERVED_102 102 +#define CYGNUM_HAL_INTERRUPT_RESERVED_103 103 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 104 +#define CYGNUM_HAL_INTERRUPT_RESERVED_105 105 +#define CYGNUM_HAL_INTERRUPT_RESERVED_106 106 +#define CYGNUM_HAL_INTERRUPT_RESERVED_107 107 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 108 +#define CYGNUM_HAL_INTERRUPT_RESERVED_109 109 +#define CYGNUM_HAL_INTERRUPT_RESERVED_110 110 +#define CYGNUM_HAL_INTERRUPT_RESERVED_111 111 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 112 +#define CYGNUM_HAL_INTERRUPT_RESERVED_113 113 +#define CYGNUM_HAL_INTERRUPT_RESERVED_114 114 +#define CYGNUM_HAL_INTERRUPT_RESERVED_115 115 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 116 +#define CYGNUM_HAL_INTERRUPT_RESERVED_117 117 +#define CYGNUM_HAL_INTERRUPT_RESERVED_118 118 +#define CYGNUM_HAL_INTERRUPT_RESERVED_119 119 + +#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 120 +#define CYGNUM_HAL_INTERRUPT_RESERVED_121 121 +#define CYGNUM_HAL_INTERRUPT_RESERVED_122 122 +#define CYGNUM_HAL_INTERRUPT_RESERVED_123 123 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 123 + +#define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4)) + +// The vector used by the Real time clock + +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5 + +//-------------------------------------------------------------------------- +// Interrupt vector translation. + +#if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ + _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \ + (_vector_) : \ + (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3)) + +#endif + +//-------------------------------------------------------------------------- +// MN10300 specific version of HAL_INTERRUPT_CONFIGURE + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ +CYG_MACRO_START \ + if( _vector_ >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 ) \ + { \ + cyg_uint32 _v_ = _vector_; \ + cyg_uint16 _val_ = 0; \ + cyg_uint16 _reg_; \ + \ + /* adjust vector to bit offset in EXTMD */ \ + _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \ + _v_ >>= 1; \ + \ + /* set bits according to requirements */ \ + if( _up_ ) _val_ |= 1; \ + if( !(_level_) ) _val_ |= 2; \ + \ + /* get EXTMD */ \ + _reg_ = mn10300_interrupt_control[0x180>>1]; \ + \ + /* clear old value and set new */ \ + _reg_ &= ~(3<<_v_); \ + _reg_ |= _val_<<_v_; \ + \ + /* restore EXTMD */ \ + mn10300_interrupt_control[0x180>>1] = _reg_; \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE_DEFINED + +//-------------------------------------------------------------------------- +// Timer control registers. +// On the mn103002 we use timers 4 and 5 + +#define TIMER4_CR 0x340010a0 +#define TIMER4_BR 0x34001090 +#define TIMER4_MD 0x34001080 + +#define TIMER5_CR 0x340010a2 +#define TIMER5_BR 0x34001092 +#define TIMER5_MD 0x34001082 + +#define TIMER_CR TIMER5_CR +#define TIMER_BR TIMER5_BR +#define TIMER_MD TIMER5_MD + +#define TIMER0_MD 0x34001000 +#define TIMER0_BR 0x34001010 +#define TIMER0_CR 0x34001020 + +//-------------------------------------------------------------------------- +// Clock control. + +#define HAL_CLOCK_INITIALIZE( _period_ ) \ +{ \ + volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \ + volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \ + volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \ + volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \ + \ + /* Set timers 4 and 5 into cascade mode */ \ + \ + *timer5_br = (_period_)>>16; \ + \ + *timer5_md = 0x40; \ + *timer5_md = 0x83; \ + \ + *timer4_br = (_period_)&0x0000FFFF; \ + \ + *timer4_md = 0x40; \ + *timer4_md = 0x80; \ +} + +#define HAL_CLOCK_RESET( _vector_, _period_ ) + +#define HAL_CLOCK_READ( _pvalue_ ) \ +{ \ + volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \ + volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \ + \ + cyg_uint16 t5; \ + cyg_uint16 t4; \ + \ + /* Loop reading the two timers until we can read t5 twice */ \ + /* with the same value. This avoids getting silly times if */ \ + /* the timers carry between reading the two regs. */ \ + do { \ + t5 = *timer5_cr; \ + t4 = *timer4_cr; \ + } while( t5 != *timer5_cr ); \ + \ + *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \ +} + +// FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since +// this means the HAL gets configured by kernel options even when the +// kernel is disabled! + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/include/variant.inc @@ -0,0 +1,322 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## AM31 assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: AM31 definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the AM31 CPU variant. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/platform.inc> + + +#------------------------------------------------------------------------------ +# Register definitions + +#define NMICR 0x34000100 // NMI control register +#define DCR 0x20000030 // Debug control register +#define ISR 0x20000034 // Interrupt control register + +#define DCR_DE 0x0010 // DE bit in DCR + +#------------------------------------------------------------------------------ +# CPU state save and restore macros + + .macro hal_cpu_save_all + movm [d2,d3,a2,a3,other],(sp) # push all registers + .endm + + .macro hal_cpu_load_all + movm (sp),[d2,d3,a2,a3,other] # pop regs + .endm + + .macro hal_cpu_get_psw reg + mov psw,\reg + .endm + + .macro hal_cpu_set_psw reg + mov \reg,psw + .endm + +##----------------------------------------------------------------------------- +# It appears that there is an undocumented extra bit +# in the PSW that masks the delivery of NMIs. It is in +# the upper 16 bits of the register that we cannot access +# directly. So, to clear it, we must set up a fake interrupt +# state and do an RTI to load the PSW. We need to do this if +# we are going to be able to set breakpoints in NMI handlers. + + .macro hal_cpu_clear_nmid + mov PSW,d3 # D3 = PSW + and 0xFFFF,d3 + mov nmid\@,d2 # D2 = Next PC + movm [d2,d3],(sp) # Push + rti # and load into CPU +nmid\@: + .endm + + +##----------------------------------------------------------------------------- +## Register addresses and initialization values + + .equ IOBCTR ,0x32000010 + .equ MEMCTR0 ,0x32000020 + .equ MEMCTR1 ,0x32000022 + .equ MEMCTR2 ,0x32000024 + .equ MEMCTR3 ,0x32000026 + .equ MEMCTR4 ,0x32000028 + .equ MEMCTR5 ,0x3200002a + .equ MEMCTR6 ,0x3200002c + .equ MEMCTR7 ,0x3200002e + .equ DRAMCTR ,0x32000040 + .equ REFCNT ,0x32000042 + + .equ INIT_MEMCTR0,0x1200 # 2wait + .equ INIT_MEMCTR1,0x0120 # 1wait-32bit- + .equ INIT_MEMCTR2,0x0065 + .equ INIT_DRAMCTR,0x0287 + .equ INIT_REFCNT,0x00eb + + .equ P2OUT ,0x36008004 + .equ P2MD ,0x36008024 + .equ P2SS ,0x36008044 + .equ P2DIR ,0x36008064 + + .equ INIT_P2MD,0xf0 + .equ INIT_P2DIR,0xff + +#------------------------------------------------------------------------------ +# MEMC macros. + +#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED + + .macro hal_memc_init + mov INIT_MEMCTR0,d2 + movhu d2,(MEMCTR0) + + mov INIT_MEMCTR1,d2 + movhu d2,(MEMCTR1) + + mov INIT_MEMCTR2,d2 + movhu d2,(MEMCTR2) + + mov INIT_REFCNT,d2 + movhu d2,(REFCNT) + + mov INIT_DRAMCTR,d2 + movhu d2,(DRAMCTR) + .endm + +#define CYGPKG_HAL_MN10300_MEMC_DEFINED + +#endif + +##----------------------------------------------------------------------------- +# Default interrupt decoding macros. + +#ifndef CYGPKG_HAL_MN10300_INTC_DEFINED + + + + # initialize all interrupts to disabled + .macro hal_intc_init + .endm + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + +#define CYG_ISR_TABLE_SIZE 10 + + .macro hal_intc_decode dreg,areg,dreg1 + mov _mn10300_interrupt_control,\areg + movhu (0x100,\areg),\dreg1 # dreg1 = IAGR + mov (0,a2),\dreg # dreg = vector priority + mov \dreg1,(0,a2) # store real vector in saved state + asl 2,\dreg # dreg = byte index of isr + add 12,\dreg # skip NMI vectors + .endm + +#else + +#define CYG_ISR_TABLE_SIZE 34 + + # decode the interrupt + .macro hal_intc_decode dreg,areg,dreg1 + mov _mn10300_interrupt_control,\areg + movhu (0x100,\areg),\dreg # dreg = IAGR + mov \dreg,(0,a2) # store real vector in saved state + add 12,\dreg # skip NMI vectors + .endm + +#endif + +#define CYGPKG_HAL_MN10300_INTC_DEFINED + +#endif + + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED + + .macro hal_diag_init + # Set up LED + mov INIT_P2MD,d2 + movbu d2,(P2MD) + mov INIT_P2DIR,d2 + movbu d2,(P2DIR) + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm + + .macro hal_diag_led val + movm [d2],(sp) + mov \val,d2 + asl 4,d2 + movbu d2,(P2OUT) + movm (sp),[d2] + .endm + + + .macro hal_diag_data +led_count: .long 0 +led_value: .byte 0x40 +led_foo1: .byte 0x00 # Keep alignment to work around compiler/linker bug +led_foo2: .byte 0x00 +led_foo3: .byte 0x00 + .endm + +#define CYGPKG_HAL_MN10300_DIAG_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MN10300_MON_DEFINED + + .macro hal_mon_init + hal_mon_init_vectors + hal_mon_init_vsr + .endm + +#if defined(CYG_HAL_STARTUP_ROM) + .macro hal_mon_init_vectors + mov _mn10300_interrupt_vectors,a0 + mov __hardware_vector_0,d0 + movhu d0,(0,a0) + mov __hardware_vector_1,d0 + movhu d0,(4,a0) + mov __hardware_vector_2,d0 + movhu d0,(8,a0) + mov __hardware_vector_3,d0 + movhu d0,(12,a0) + mov __hardware_vector_4,d0 + movhu d0,(16,a0) + mov __hardware_vector_5,d0 + movhu d0,(20,a0) + mov __hardware_vector_6,d0 + movhu d0,(24,a0) + .endm +#else + .macro hal_mon_init_vectors + .endm +#endif + +#if defined(CYG_HAL_STARTUP_RAM) + + # init vsr table in SRAM where the ROM + # vectors the interrupts. + + .macro hal_mon_init_vsr + mov _hal_vsr_table,a0 + mov __default_interrupt_vsr,d0 + mov d0,(0,a0) + mov d0,(4,a0) + mov d0,(8,a0) +#ifndef CYG_HAL_USE_ROM_MONITOR_CYGMON + # When using Cygmon, leave level 3 for GDB + # Ctrl-C interrupts. + mov d0,(12,a0) +#endif + mov d0,(16,a0) + mov d0,(20,a0) + mov d0,(24,a0) + mov __default_nmi_vsr,d0 + mov d0,(28,a0) + mov __default_trap_vsr,d0 + mov d0,(32,a0) + .endm + +#else + .macro hal_mon_init_vsr + .endm +#endif + +#if !(defined(CYG_HAL_STARTUP_ROM) || \ + defined(CYG_HAL_MN10300_SIM) || \ + !defined(CYG_HAL_USE_ROM_MONITOR)) + +#define CYG_HAL_MN10300_VSR_TABLE_DEFINED + +#endif + + + +#define CYGPKG_HAL_MN10300_MON_DEFINED + +#endif + + + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/src/PKGconf.mak @@ -0,0 +1,62 @@ +#============================================================================== +# +# makefile +# +# hal/mn10300/am31/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_mn10300_am31 +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := var_misc.c +OTHER_OBJS := +OTHER_TARGETS := ldscript.stamp +OTHER_CLEAN := ldscript.clean +OTHER_DEPS := ldscript.d + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src + +.PHONY: ldscript.clean + +EXTRAS = $(wildcard $(PREFIX)/lib/libextras.a) + +ldscript.stamp: mn10300_am31.ld $(EXTRAS) +ifneq ($(EXTRAS),) + $(LD) -EL --whole-archive $(PREFIX)/lib/libextras.a -r -o $(PREFIX)/lib/extras.o + $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=$(EXTRAS) -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< +else + $(CC) -E -P -Wp,-MD,ldscript.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< +endif + @echo > ldscript.d + @echo $@ ':' $< '\' >> ldscript.d + @tail -n +2 ldscript.tmp >> ldscript.d + @rm ldscript.tmp + $(TOUCH) $@ + +ldscript.clean: + $(RM) -f $(PREFIX)/lib/target.ld + $(RM) -f ldscript.stamp
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/src/mn10300_am31.ld @@ -0,0 +1,118 @@ +//=========================================================================== +// +// MLT linker script for MN10300 +// adapted from packages\hal\mn10300\stdeval1\v1_1\src\stdeval1.ld +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +#include <pkgconf/system.h> +STARTUP(vectors.o) +ENTRY(reset_vector) +#ifdef EXTRAS +INPUT(extras.o) +#endif +GROUP(libtarget.a libgcc.a) + + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { FORCE_OUTPUT; KEEP (*(.vectors)) } \ + > _region_ + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ + > _region_ \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fixup) } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.gcc_except_table) } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); *(.data*) *(.data1) \ + . = ALIGN(4); \ + ___DEVTAB__ = ABSOLUTE (.); KEEP (*(SORT (.devtab*))) ___DEVTAB_END__ = ABSOLUTE (.); \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + . = ALIGN (4); \ + __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \ + __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \ + _GOT_START = ABSOLUTE (.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.) + 32768; _SDA_BASE_ = ABSOLUTE (.); \ + *(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \ + *(.dynamic) *(.sdata*) *(.sbss*) } \ + > _region_ \ + __rom_data_start = LOADADDR (.data); \ + __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + *(.scommon) *(.dynbss) *(.bss) *(COMMON) \ + __bss_end = ABSOLUTE (.); } \ + > _region_ + +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); + +#include CYGHWR_MEMORY_LAYOUT_LDI + +_mn10300_interrupt_control = 0x34000100; +_mn10300_interrupt_vectors = 0x20000000; + +#if (defined (CYG_HAL_STARTUP_RAM) && ! defined (CYGPKG_HAL_MN10300_SIM)) +#define VSR_BASE 0x48000000 +_hal_vsr_table = VSR_BASE; +_hal_virtual_vector_table = VSR_BASE + 0x80; +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/am31/current/src/var_misc.c @@ -0,0 +1,89 @@ +//========================================================================== +// +// var_misc.c +// +// HAL CPU variant miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_cache.h> + +/*------------------------------------------------------------------------*/ +/* Variant specific initialization routine. */ + +void hal_variant_init(void) +{ +} + +/*------------------------------------------------------------------------*/ +/* Cache functions. */ + +#if !defined(CYG_HAL_MN10300_SIM) +void cyg_hal_dcache_store(CYG_ADDRWORD base, int size) +{ + volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0; + volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1; + register int i; + register CYG_ADDRWORD state; + + HAL_DCACHE_IS_ENABLED(state); + if (state) + HAL_DCACHE_DISABLE(); + + way0 += base & 0x000007f0; + way1 += base & 0x000007f0; + for( i = 0; i < size; i += HAL_DCACHE_LINE_SIZE ) + { + *(CYG_ADDRWORD *)way0 = 0; + *(CYG_ADDRWORD *)way1 = 0; + way0 += HAL_DCACHE_LINE_SIZE; + way1 += HAL_DCACHE_LINE_SIZE; + } + if (state) + HAL_DCACHE_ENABLE(); +} +#endif + + +/*------------------------------------------------------------------------*/ +/* End of var_misc.c */
--- a/packages/hal/mn10300/arch/current/ChangeLog +++ b/packages/hal/mn10300/arch/current/ChangeLog @@ -1,3 +1,127 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/arch.inc: rename CYGPKG_HAL_MN10300_AM32_STDEVAL1 to + CYGPKG_HAL_MN10300_AM31_STDEVAL1 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changed from development branch. + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/vectors.S: Removed debug code. + + * include/hal_intr.h: Made mn10300_interrupt_control[] unsized + since it is different sizes on different variants. + + * include/arch.inc: + Changed hal_cpu_int_merge so that both the IE and IPL bits are + changed across a thread switch. + Some minor tweaks to trace code for AM32. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal_mn10300.h: + Move CYGPKG_HAL_MN10300's "target mn10300" under the variant + packages instead. + Add CYGPKG_HAL_MN10300_VARIANTS + + 1999-07-30 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_misc.c: Added default ISR. + + * src/vectors.S: + Added Ctrl-C support. Extended VSR table to include new + exceptions. Install default ISR by default. + + * src/mn10300_stub.c: + Added asynchronous breakpoint support. + [Later] Tidied up install_async_breakpoint() and fixed indirection + bug. + + * include/hal_intr.h: + Added default ISR. Removed HAL_INTERRUPT_CONFIGURE(), this is now + variant-specific. + + 1999-07-27 Nick Garnett <nickg@cygnus.co.uk> + + * src/vectors.S: + Some reorganization to make code more generic. + Some diagnostic macros added. + Note: some trace/debug code has been left in place temporarily, + this will be removed eventually. + + * include/arch.inc: + Changed all *_MIPS_* to *_MN10300_*. + Added some temporary trace/debug macros. + + 1999-07-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_misc.c: + * include/hal_arch.h: + Added hal_idle_thread_action(); + + * include/arch.inc: Made hal_cpu_init definition optional. + + 1999-07-08 Nick Garnett <nickg@cygnus.co.uk> + + * src/vectors.S: + Moved some code to variant specific macros. Now pass ISR register + to cyg_hal_exception_handler() to enable further decoding. + + * src/hal_misc.c (cyg_hal_exception_handler): + Added extra argument to pass ISR register value. Now decodes ISR + value to specify extra exceptions. + + 1999-07-07 Nick Garnett <nickg@cygnus.co.uk> + + * include/hal_intr.h: + Added HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() macro to support + calling of DSRs on the interrupt stack. + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): + Initialize the PSW to enable all interrupts on entry to thread. + + * include/arch.inc: + Added implementations of CPU control macros. + + * src/context.S: + Added code to preserve PSW across context switches. + + * src/vectors.S: + Implemented mechanism to call DSRs on the interrupt stack. + Refined condition for defining VSR table here. + + 1999-06-30 Nick Garnett <nickg@cygnus.co.uk> + + * src/context.S: + * src/vectors.S: + Use hal_cpu_save_all and hal_cpu_load_all macros to save and + restore CPU register sets. + + * include/hal_arch.h: + Modified HAL_THREAD_INIT_CONTEXT_EXTRA() to take some arguments. + + 1999-06-29 Nick Garnett <nickg@cygnus.co.uk> + + * include/hal_arch.h: + Added include of variant header. + + * include/hal_cache.h: + * include/hal_intr.h: + * src/vectors.S: + * src/hal_misc.c: + Extensive changes to convert to new HAL organization. These mostly + involve moving variant and platform specific stuff out to the + appropriate headers in the variant and platform directories. + + * src/PKGconf.mak: + * src/mn10300.ld (removed): + Moved build of target.ld to variant directory. + + * include/arch.inc: + Added this file to contain architecture specific macros. + 1999-06-08 Jesper Skov <jskov@cygnus.co.uk> * src/hal_misc.c (cyg_hal_dcache_store): Only define for HW target.
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/arch/current/include/arch.inc @@ -0,0 +1,229 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +##============================================================================= +## +## arch.inc +## +## MN10300 assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1997-10-16 +## Purpose: Architecture definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the MN10300 CPU family. +## Usage: +## #include <cyg/hal/arch.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/variant.inc> + +##----------------------------------------------------------------------------- +## CPU specific macros. These provide a common assembler interface to +## operations that may have CPU specific implementations on different +## variants of the architecture. + +#ifndef CYGPKG_HAL_MN10300_CPU_INIT_DEFINED + # Initialize CPU + .macro hal_cpu_init + # Set up the PSW + mov 0x0700,d0 + mov d0,psw + .endm +#endif + + # Enable interrupts + .macro hal_cpu_int_enable + or 0x0800,psw + .endm + + # Disable interrupts + .macro hal_cpu_int_disable + and 0xF7ff,psw + .endm + + # Merge the interrupt enable state of the status register in + # \sr with the current sr. + .macro hal_cpu_int_merge sr + and 0x00000F00,\sr # isolate IE bit + mov psw,d0 + and 0xfffff0ff,d0 + or d0,\sr + mov \sr,psw + .endm + + # Enable further exception processing, and disable + # interrupt processing. + .macro hal_cpu_except_enable + .endm + + # Return from exception. + .macro hal_cpu_eret pc,sr + .endm + +##----------------------------------------------------------------------------- +# Default interrupt decoding macros. + +#ifndef CYGPKG_HAL_MN10300_INTC_DEFINED + +#ifndef CYGPKG_HAL_MN10300_INTC_INIT_DEFINED + # initialize all interrupts to disabled + .macro hal_intc_init + .endm +#endif + + .macro hal_intc_decode vnum + .endm + +#endif + +#------------------------------------------------------------------------------ +# MMU macros. + +#ifndef CYGPKG_HAL_MN10300_MMU_DEFINED + + .macro hal_mmu_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# MEMC macros. + +#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED + + .macro hal_memc_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_MN10300_CACHE_DEFINED + + .macro hal_cache_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED + + .macro hal_diag_init + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm + + .macro hal_diag_data + .endm +#endif + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_MN10300_TIMER_DEFINED + + .macro hal_timer_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MN10300_MON_DEFINED + + .macro hal_mon_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# temporary trace macros + +#if 0 + +#ifdef CYGPKG_HAL_MN10300_AM31_STDEVAL1 +#define TRACE_BASE 0x48100000 +#else +#error TRACE_BASE not defined for platform +#endif + + .macro traceinit + mov TRACE_BASE,a2 + mov TRACE_BASE+0x10,d0 + mov d0,(a2) + .endm + + .macro trace,tag,arg1=0,arg2=0 + movm [d2,a2,a3],(sp) + mov TRACE_BASE,a2 + mov (a2),a3 + mov \tag,d2 + mov d2,(a3) + mov (12,a2),d2 + mov d2,(4,a3) + add 1,d2 + mov d2,(12,a2) + mov \arg1,d2 + mov d2,(8,a3) + mov \arg2,d2 + mov d2,(12,a3) + add 16,a3 + mov a3,(a2) + movm (sp),[d2,a2,a3] + .endm +#else + .macro traceinit + .endm + + .macro trace,tag,arg1=0,arg2=0 + .endm +#endif + + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_ARCH_INC +# end of arch.inc
--- a/packages/hal/mn10300/arch/current/include/hal_arch.h +++ b/packages/hal/mn10300/arch/current/include/hal_arch.h @@ -44,6 +44,8 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_arch.h> + //-------------------------------------------------------------------------- // Processor saved states: @@ -51,26 +53,26 @@ typedef struct HAL_SavedRegisters { // These are common to all saved states and are in the order // stored and loaded by the movm instruction. - cyg_uint32 vector; /* Vector number/dummy */ - cyg_uint32 lar; /* Loop address register */ - cyg_uint32 lir; /* Loop instruction register */ - cyg_uint32 mdr; /* Multiply/Divide register */ - cyg_uint32 a1; - cyg_uint32 a0; - cyg_uint32 d1; - cyg_uint32 d0; - cyg_uint32 a3; - cyg_uint32 a2; - cyg_uint32 d3; - cyg_uint32 d2; - + CYG_ADDRWORD vector; /* Vector number/dummy */ + CYG_ADDRWORD lar; /* Loop address register */ + CYG_ADDRWORD lir; /* Loop instruction register */ + CYG_ADDRWORD mdr; /* Multiply/Divide register */ + CYG_ADDRWORD a1; + CYG_ADDRWORD a0; + CYG_ADDRWORD d1; + CYG_ADDRWORD d0; + CYG_ADDRWORD a3; + CYG_ADDRWORD a2; + CYG_ADDRWORD d3; + CYG_ADDRWORD d2; + /* On interrupts the PC and PSW are pushed automatically by the */ /* CPU and SP is pushed for debugging reasons. On a thread switch */ /* the saved context is made to look the same. */ - cyg_uint32 sp; /* Saved copy of SP in some states */ - cyg_uint32 psw; /* Status word */ - cyg_uint32 pc; /* Program Counter */ + CYG_ADDRWORD sp; /* Saved copy of SP in some states */ + CYG_ADDRWORD psw; /* Status word */ + CYG_ADDRWORD pc; /* Program Counter */ } HAL_SavedRegisters; @@ -102,12 +104,16 @@ externC cyg_uint32 hal_msbit_index(cyg_u // _entry_ entry point address. // _id_ bit pattern used in initializing registers, for debugging. +#ifndef HAL_THREAD_INIT_CONTEXT_EXTRA +#define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_) +#endif #define HAL_THREAD_INIT_CONTEXT( _sp_, _thread_, _entry_, _id_ ) \ { \ register HAL_SavedRegisters *_regs_; \ _regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)&~15) - \ sizeof(HAL_SavedRegisters)*2); \ + HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_); \ _regs_->d0 = (CYG_WORD)(_thread_); \ _regs_->d1 = (_id_)|0xddd1; \ _regs_->d2 = (_id_)|0xddd2; \ @@ -119,7 +125,7 @@ externC cyg_uint32 hal_msbit_index(cyg_u _regs_->mdr = 0; \ _regs_->lir = 0; \ _regs_->lar = 0; \ -/* _regs_->psw = 0x0F00; */ \ + _regs_->psw = 0x0000F00; \ _regs_->pc = (CYG_WORD)(_entry_); \ _sp_ = (CYG_ADDRESS)_regs_; \ } @@ -174,29 +180,38 @@ asm volatile (" .globl " #_label_ ";" #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ (_regs_) = (HAL_SavedRegisters *)(_sp_) +#ifndef HAL_GET_GDB_EXTRA_REGISTERS +#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) +#endif +#ifndef HAL_SET_GDB_EXTRA_REGISTERS +#define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ) +#endif + + // Copy a set of registers from a HAL_SavedRegisters structure into a // GDB ordered array. -#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ -{ \ - CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ - \ - _regval_[0] = (_regs_)->d0; \ - _regval_[1] = (_regs_)->d1; \ - _regval_[2] = (_regs_)->d2; \ - _regval_[3] = (_regs_)->d3; \ - _regval_[4] = (_regs_)->a0; \ - _regval_[5] = (_regs_)->a1; \ - _regval_[6] = (_regs_)->a2; \ - _regval_[7] = (_regs_)->a3; \ - \ - _regval_[8] = (CYG_ADDRWORD)(_regs_) + \ - sizeof(HAL_SavedRegisters); \ - _regval_[9] = (_regs_)->pc; \ - _regval_[10] = (_regs_)->mdr; \ - _regval_[11] = (_regs_)->psw; \ - \ - _regval_[12] = (_regs_)->lar; \ - _regval_[13] = (_regs_)->lir; \ +#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ +{ \ + CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + \ + _regval_[0] = (_regs_)->d0; \ + _regval_[1] = (_regs_)->d1; \ + _regval_[2] = (_regs_)->d2; \ + _regval_[3] = (_regs_)->d3; \ + _regval_[4] = (_regs_)->a0; \ + _regval_[5] = (_regs_)->a1; \ + _regval_[6] = (_regs_)->a2; \ + _regval_[7] = (_regs_)->a3; \ + \ + _regval_[8] = (CYG_ADDRWORD)(_regs_) + \ + sizeof(HAL_SavedRegisters); \ + _regval_[9] = (_regs_)->pc; \ + _regval_[10] = (_regs_)->mdr; \ + _regval_[11] = (_regs_)->psw; \ + \ + _regval_[12] = (_regs_)->lar; \ + _regval_[13] = (_regs_)->lir; \ + HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \ } // Copy a GDB ordered array into a HAL_SavedRegisters structure. @@ -223,6 +238,8 @@ asm volatile (" .globl " #_label_ ";" * mess up the saved state. No PSW is saved on thread context \ * switches, so there is nowhere to save it to. \ */ \ + \ + HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \ } //------------------------------------------------------------------------- @@ -250,9 +267,9 @@ externC void hal_longjmp(hal_jmp_buf env // chance to insert code. Typical idle thread behaviour might be to halt the // processor. -//externC void hal_idle_thread_action(cyg_uint32 loop_count); +externC void hal_idle_thread_action(cyg_uint32 loop_count); -#define HAL_IDLE_THREAD_ACTION(_count_) +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) //----------------------------------------------------------------------------- // Minimal and sensible stack sizes: the intention is that applications
--- a/packages/hal/mn10300/arch/current/include/hal_cache.h +++ b/packages/hal/mn10300/arch/current/include/hal_cache.h @@ -50,6 +50,8 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_cache.h> + //============================================================================= // MN10300 Simulator @@ -167,225 +169,6 @@ #endif -//============================================================================= -// MN103002 implementation - -#if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002) - -//----------------------------------------------------------------------------- -// Cache dimensions - - -// Data cache -#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes -#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line -#define HAL_DCACHE_WAYS 2 // Associativity of the cache - -// Instruction cache -#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes -#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line -#define HAL_ICACHE_WAYS 2 // Associativity of the cache - -#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) - -//----------------------------------------------------------------------------- -// Control registers - -#define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070) - -#define HAL_CHCTR_ICEN 0x0001 -#define HAL_CHCTR_DCEN 0x0002 -#define HAL_CHCTR_ICBUSY 0x0004 -#define HAL_CHCTR_DCBUSY 0x0008 -#define HAL_CHCTR_ICINV 0x0010 -#define HAL_CHCTR_DCINV 0x0020 -#define HAL_CHCTR_DCWTMD 0x0040 -#define HAL_CHCTR_ICWMD 0x0300 -#define HAL_CHCTR_DCWMD 0x3000 - -#define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000) -#define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000) - -//----------------------------------------------------------------------------- -// Global control of data cache - -// Enable the data cache -#define HAL_DCACHE_ENABLE() \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - chctr |= HAL_CHCTR_DCEN; \ - *HAL_CHCTR = chctr; \ -} - -// Disable the data cache -#define HAL_DCACHE_DISABLE() \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - chctr &= ~HAL_CHCTR_DCEN; \ - *HAL_CHCTR = chctr; \ - while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ -} - -// Query the state of the data cache -#define HAL_DCACHE_IS_ENABLED(_state_) \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \ -} - -// Invalidate the entire cache -#define HAL_DCACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRWORD chctr; \ - register CYG_ADDRWORD state; \ - HAL_DCACHE_IS_ENABLED(state); \ - if (state) \ - HAL_DCACHE_DISABLE(); \ - chctr = *HAL_CHCTR; \ - chctr |= HAL_CHCTR_DCINV; \ - *HAL_CHCTR = chctr; \ - while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ - if (state) \ - HAL_DCACHE_ENABLE(); \ -} - -// Synchronize the contents of the cache with memory. -#define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS ) - -// Set the data cache refill burst size -//#define HAL_DCACHE_BURST_SIZE(_size_) - -// Set the data cache write mode -#define HAL_DCACHE_WRITE_MODE( _mode_ ) \ -{ \ - register CYG_ADDRWORD chctr; \ - register CYG_ADDRWORD state; \ - HAL_DCACHE_IS_ENABLED(state); \ - if (state) \ - HAL_DCACHE_DISABLE(); \ - chctr = *HAL_CHCTR; \ - chctr |= HAL_CHCTR_DCWTMD*(_mode_); \ - *HAL_CHCTR = chctr; \ - while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \ - if (state) \ - HAL_DCACHE_ENABLE(); \ -} - -#define HAL_DCACHE_WRITEBACK_MODE 0 -#define HAL_DCACHE_WRITETHRU_MODE 1 - -// Load the contents of the given address range into the data cache -// and then lock the cache so that it stays there. -//#define HAL_DCACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_DCACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_DCACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Data cache line control - -// Allocate cache lines for the given address range without reading its -// contents from memory. -//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) - -// Write dirty cache lines to memory and invalidate the cache entries -// for the given address range. -//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) - -// Write dirty cache lines to memory for the given address range. - -// This functionality requires 4 register variables. To prevent register -// spilling, put the code in a separate function. -externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size); - -#define HAL_DCACHE_STORE( _base_ , _size_ ) \ - cyg_hal_dcache_store((_base_), (_size_)) - -// Preread the given range into the cache with the intention of reading -// from it later. -//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) - -// Preread the given range into the cache with the intention of writing -// to it later. -//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) - -// Allocate and zero the cache lines associated with the given range. -//#define HAL_DCACHE_ZERO( _base_ , _size_ ) - -//----------------------------------------------------------------------------- -// Global control of Instruction cache - -// Enable the instruction cache -#define HAL_ICACHE_ENABLE() \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - chctr |= HAL_CHCTR_ICEN; \ - *HAL_CHCTR = chctr; \ -} - -// Disable the instruction cache -#define HAL_ICACHE_DISABLE() \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - chctr &= ~HAL_CHCTR_ICEN; \ - *HAL_CHCTR = chctr; \ - while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \ -} - -// Query the state of the instruction cache -#define HAL_ICACHE_IS_ENABLED(_state_) \ -{ \ - register CYG_ADDRWORD chctr = *HAL_CHCTR; \ - _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \ -} - -// Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRWORD chctr; \ - register CYG_ADDRWORD state; \ - HAL_ICACHE_IS_ENABLED(state); \ - if (state) \ - HAL_ICACHE_DISABLE(); \ - chctr = *HAL_CHCTR; \ - chctr |= HAL_CHCTR_ICINV; \ - *HAL_CHCTR = chctr; \ - while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \ - if (state) \ - HAL_ICACHE_ENABLE(); \ -} - -// Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() - -// Set the instruction cache refill burst size -//#define HAL_ICACHE_BURST_SIZE(_size_) - -// Load the contents of the given address range into the instruction cache -// and then lock the cache so that it stays there. -//#define HAL_ICACHE_LOCK(_base_, _size_) - -// Undo a previous lock operation -//#define HAL_ICACHE_UNLOCK(_base_, _size_) - -// Unlock entire cache -//#define HAL_ICACHE_UNLOCK_ALL() - -//----------------------------------------------------------------------------- -// Instruction cache line control - -// Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) - -#endif - //----------------------------------------------------------------------------- // Check that a supported configuration has actually defined some macros.
--- a/packages/hal/mn10300/arch/current/include/hal_intr.h +++ b/packages/hal/mn10300/arch/current/include/hal_intr.h @@ -46,425 +46,12 @@ // //========================================================================== -#include <cyg/infra/cyg_type.h> - #include <pkgconf/hal.h> -//-------------------------------------------------------------------------- - -// The MN10300 has a somewhat complex interrupt structure. Besides the -// reset and NMI vectors there are seven maskable interrupt vectors -// which must point to code in the 64k starting at 0x40000000. There -// are also 25 Interrupt control groups, each of which can have 4 -// interrupt lines attached, for a theoretical total of 100 interrupts -// (!). Some of these are dedicated to specific devices, other to -// external pins, and others are not connected to anything, resulting -// in only 45 that can actually be delivered. Each control group may -// be assigned one of seven interrupt levels, and is delivered to the -// corresponding vector. Software can then use a register to determine -// the delivering group and detect from there which interrupt has been -// delivered. -// -// The approach we will adopt at present is for the code attached to -// each vector to save state and jump via a table to a VSR. The -// default VSR will fully decode the delivered interrupt into a table -// of isr/data/object entries. VSR replacement will operate on the -// first level indirection table rather than the hardware -// vectors. This is the fastest mechanism, however it needs 100*3*4 + -// 7*4 = 1228 bytes for the tables. -// - -//-------------------------------------------------------------------------- -// Interrupt vectors. - -// The level-specific hardware vectors -// These correspond to VSRs and are the values to use for HAL_VSR_GET/SET -#define CYGNUM_HAL_VECTOR_0 0 -#define CYGNUM_HAL_VECTOR_1 1 -#define CYGNUM_HAL_VECTOR_2 2 -#define CYGNUM_HAL_VECTOR_3 3 -#define CYGNUM_HAL_VECTOR_4 4 -#define CYGNUM_HAL_VECTOR_5 5 -#define CYGNUM_HAL_VECTOR_6 6 -#define CYGNUM_HAL_VECTOR_NMI 7 -#define CYGNUM_HAL_VECTOR_TRAP 8 - -#define CYGNUM_HAL_VSR_MIN 0 -#define CYGNUM_HAL_VSR_MAX 8 -#define CYGNUM_HAL_VSR_COUNT 9 - -// Exception vectors. These are the values used when passed out to an -// external exception handler using cyg_hal_deliver_exception() - -#define CYGNUM_HAL_EXCEPTION_NMI 0 -#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS \ - CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR -#define CYGNUM_HAL_EXCEPTION_TRAP 3 - -#define CYGNUM_HAL_EXCEPTION_MIN 0 -#define CYGNUM_HAL_EXCEPTION_MAX 3 -#define CYGNUM_HAL_EXCEPTION_COUNT 4 - - -#if defined(CYG_HAL_MN10300_MN103000) - -// The decoded interrupts - -#define CYGNUM_HAL_INTERRUPT_NMIRQ 0 -#define CYGNUM_HAL_INTERRUPT_WATCHDOG 1 -#define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2 -#define CYGNUM_HAL_INTERRUPT_RESERVED_3 3 - -#define CYGNUM_HAL_INTERRUPT_RESERVED_4 4 -#define CYGNUM_HAL_INTERRUPT_RESERVED_5 5 -#define CYGNUM_HAL_INTERRUPT_RESERVED_6 6 -#define CYGNUM_HAL_INTERRUPT_RESERVED_7 7 - -#define CYGNUM_HAL_INTERRUPT_TIMER_0 8 -#define CYGNUM_HAL_INTERRUPT_TIMER_1 9 -#define CYGNUM_HAL_INTERRUPT_TIMER_2 10 -#define CYGNUM_HAL_INTERRUPT_TIMER_3 11 - -#define CYGNUM_HAL_INTERRUPT_TIMER_4 12 -#define CYGNUM_HAL_INTERRUPT_TIMER_5 13 -#define CYGNUM_HAL_INTERRUPT_TIMER_6 14 -#define CYGNUM_HAL_INTERRUPT_TIMER_7 15 - -#define CYGNUM_HAL_INTERRUPT_TIMER_8 16 -#define CYGNUM_HAL_INTERRUPT_TIMER_8_COMPARE_A 17 -#define CYGNUM_HAL_INTERRUPT_TIMER_8_COMPARE_B 18 -#define CYGNUM_HAL_INTERRUPT_RESERVED_19 19 - -#define CYGNUM_HAL_INTERRUPT_TIMER_9 20 -#define CYGNUM_HAL_INTERRUPT_TIMER_9_COMPARE_A 21 -#define CYGNUM_HAL_INTERRUPT_TIMER_9_COMPARE_B 22 -#define CYGNUM_HAL_INTERRUPT_RESERVED_23 23 - -#define CYGNUM_HAL_INTERRUPT_TIMER_10 24 -#define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_A 25 -#define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_B 26 -#define CYGNUM_HAL_INTERRUPT_TIMER_10_COMPARE_C 27 - -#define CYGNUM_HAL_INTERRUPT_TIMER_11 28 -#define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_A 29 -#define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_B 30 -#define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_C 31 - -#define CYGNUM_HAL_INTERRUPT_TIMER_12 32 -#define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_A 33 -#define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_B 34 -#define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_C 35 - -#define CYGNUM_HAL_INTERRUPT_TIMER_11_COMPARE_D 36 -#define CYGNUM_HAL_INTERRUPT_TIMER_12_COMPARE_D 37 -#define CYGNUM_HAL_INTERRUPT_RESERVED_38 38 -#define CYGNUM_HAL_INTERRUPT_RESERVED_39 39 - -#define CYGNUM_HAL_INTERRUPT_DMA0 40 -#define CYGNUM_HAL_INTERRUPT_RESERVED_41 41 -#define CYGNUM_HAL_INTERRUPT_RESERVED_42 42 -#define CYGNUM_HAL_INTERRUPT_RESERVED_43 43 - -#define CYGNUM_HAL_INTERRUPT_DMA1 44 -#define CYGNUM_HAL_INTERRUPT_RESERVED_45 45 -#define CYGNUM_HAL_INTERRUPT_RESERVED_46 46 -#define CYGNUM_HAL_INTERRUPT_RESERVED_47 47 - -#define CYGNUM_HAL_INTERRUPT_DMA2 48 -#define CYGNUM_HAL_INTERRUPT_RESERVED_49 49 -#define CYGNUM_HAL_INTERRUPT_RESERVED_50 50 -#define CYGNUM_HAL_INTERRUPT_RESERVED_51 51 - -#define CYGNUM_HAL_INTERRUPT_DMA3 52 -#define CYGNUM_HAL_INTERRUPT_RESERVED_53 53 -#define CYGNUM_HAL_INTERRUPT_RESERVED_54 54 -#define CYGNUM_HAL_INTERRUPT_RESERVED_55 55 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 56 -#define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 57 -#define CYGNUM_HAL_INTERRUPT_RESERVED_58 58 -#define CYGNUM_HAL_INTERRUPT_RESERVED_59 59 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 60 -#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 61 -#define CYGNUM_HAL_INTERRUPT_RESERVED_62 62 -#define CYGNUM_HAL_INTERRUPT_RESERVED_63 63 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 64 -#define CYGNUM_HAL_INTERRUPT_RESERVED_65 65 -#define CYGNUM_HAL_INTERRUPT_RESERVED_66 66 -#define CYGNUM_HAL_INTERRUPT_RESERVED_67 67 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 68 -#define CYGNUM_HAL_INTERRUPT_RESERVED_69 69 -#define CYGNUM_HAL_INTERRUPT_RESERVED_70 70 -#define CYGNUM_HAL_INTERRUPT_RESERVED_71 71 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 72 -#define CYGNUM_HAL_INTERRUPT_RESERVED_73 73 -#define CYGNUM_HAL_INTERRUPT_RESERVED_74 74 -#define CYGNUM_HAL_INTERRUPT_RESERVED_75 75 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 76 -#define CYGNUM_HAL_INTERRUPT_RESERVED_77 77 -#define CYGNUM_HAL_INTERRUPT_RESERVED_78 78 -#define CYGNUM_HAL_INTERRUPT_RESERVED_79 79 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 80 -#define CYGNUM_HAL_INTERRUPT_RESERVED_81 81 -#define CYGNUM_HAL_INTERRUPT_RESERVED_82 82 -#define CYGNUM_HAL_INTERRUPT_RESERVED_83 83 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 84 -#define CYGNUM_HAL_INTERRUPT_RESERVED_85 85 -#define CYGNUM_HAL_INTERRUPT_RESERVED_86 86 -#define CYGNUM_HAL_INTERRUPT_RESERVED_87 87 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 88 -#define CYGNUM_HAL_INTERRUPT_RESERVED_89 89 -#define CYGNUM_HAL_INTERRUPT_RESERVED_90 90 -#define CYGNUM_HAL_INTERRUPT_RESERVED_91 91 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 92 -#define CYGNUM_HAL_INTERRUPT_RESERVED_93 93 -#define CYGNUM_HAL_INTERRUPT_RESERVED_94 94 -#define CYGNUM_HAL_INTERRUPT_RESERVED_95 95 - -#define CYGNUM_HAL_INTERRUPT_AD_CONVERSION 96 -#define CYGNUM_HAL_INTERRUPT_RESERVED_97 97 -#define CYGNUM_HAL_INTERRUPT_RESERVED_98 98 -#define CYGNUM_HAL_INTERRUPT_RESERVED_99 99 - -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX 99 - -#define CYGNUM_HAL_ISR_COUNT 100 - -#elif defined(CYG_HAL_MN10300_MN103002) - -// The decoded interrupts - -#define CYGNUM_HAL_INTERRUPT_NMIRQ 0 -#define CYGNUM_HAL_INTERRUPT_WATCHDOG 1 -#define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2 -#define CYGNUM_HAL_INTERRUPT_RESERVED_3 3 - -#define CYGNUM_HAL_INTERRUPT_RESERVED_4 4 -#define CYGNUM_HAL_INTERRUPT_RESERVED_5 5 -#define CYGNUM_HAL_INTERRUPT_RESERVED_6 6 -#define CYGNUM_HAL_INTERRUPT_RESERVED_7 7 +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> -#define CYGNUM_HAL_INTERRUPT_TIMER_0 8 -#define CYGNUM_HAL_INTERRUPT_RESERVED_9 9 -#define CYGNUM_HAL_INTERRUPT_RESERVED_10 10 -#define CYGNUM_HAL_INTERRUPT_RESERVED_11 11 - -#define CYGNUM_HAL_INTERRUPT_TIMER_1 12 -#define CYGNUM_HAL_INTERRUPT_RESERVED_13 13 -#define CYGNUM_HAL_INTERRUPT_RESERVED_14 14 -#define CYGNUM_HAL_INTERRUPT_RESERVED_15 15 - -#define CYGNUM_HAL_INTERRUPT_TIMER_2 16 -#define CYGNUM_HAL_INTERRUPT_RESERVED_17 17 -#define CYGNUM_HAL_INTERRUPT_RESERVED_18 18 -#define CYGNUM_HAL_INTERRUPT_RESERVED_19 19 - -#define CYGNUM_HAL_INTERRUPT_TIMER_3 20 -#define CYGNUM_HAL_INTERRUPT_RESERVED_21 21 -#define CYGNUM_HAL_INTERRUPT_RESERVED_22 22 -#define CYGNUM_HAL_INTERRUPT_RESERVED_23 23 - -#define CYGNUM_HAL_INTERRUPT_TIMER_4 24 -#define CYGNUM_HAL_INTERRUPT_RESERVED_25 25 -#define CYGNUM_HAL_INTERRUPT_RESERVED_26 26 -#define CYGNUM_HAL_INTERRUPT_RESERVED_27 27 - -#define CYGNUM_HAL_INTERRUPT_TIMER_5 28 -#define CYGNUM_HAL_INTERRUPT_RESERVED_29 29 -#define CYGNUM_HAL_INTERRUPT_RESERVED_30 30 -#define CYGNUM_HAL_INTERRUPT_RESERVED_31 31 - -#define CYGNUM_HAL_INTERRUPT_TIMER_6 32 -#define CYGNUM_HAL_INTERRUPT_RESERVED_33 33 -#define CYGNUM_HAL_INTERRUPT_RESERVED_34 34 -#define CYGNUM_HAL_INTERRUPT_RESERVED_35 35 - -#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A 36 -#define CYGNUM_HAL_INTERRUPT_RESERVED_37 37 -#define CYGNUM_HAL_INTERRUPT_RESERVED_38 38 -#define CYGNUM_HAL_INTERRUPT_RESERVED_39 39 - -#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B 40 -#define CYGNUM_HAL_INTERRUPT_RESERVED_41 41 -#define CYGNUM_HAL_INTERRUPT_RESERVED_42 42 -#define CYGNUM_HAL_INTERRUPT_RESERVED_43 43 - -#define CYGNUM_HAL_INTERRUPT_RESERVED_44 44 -#define CYGNUM_HAL_INTERRUPT_RESERVED_45 45 -#define CYGNUM_HAL_INTERRUPT_RESERVED_46 46 -#define CYGNUM_HAL_INTERRUPT_RESERVED_47 47 - -#define CYGNUM_HAL_INTERRUPT_DMA0 48 -#define CYGNUM_HAL_INTERRUPT_RESERVED_49 49 -#define CYGNUM_HAL_INTERRUPT_RESERVED_50 50 -#define CYGNUM_HAL_INTERRUPT_RESERVED_51 51 - -#define CYGNUM_HAL_INTERRUPT_DMA1 52 -#define CYGNUM_HAL_INTERRUPT_RESERVED_53 53 -#define CYGNUM_HAL_INTERRUPT_RESERVED_54 54 -#define CYGNUM_HAL_INTERRUPT_RESERVED_55 55 - -#define CYGNUM_HAL_INTERRUPT_DMA2 56 -#define CYGNUM_HAL_INTERRUPT_RESERVED_57 57 -#define CYGNUM_HAL_INTERRUPT_RESERVED_58 58 -#define CYGNUM_HAL_INTERRUPT_RESERVED_59 59 - -#define CYGNUM_HAL_INTERRUPT_DMA3 60 -#define CYGNUM_HAL_INTERRUPT_RESERVED_61 61 -#define CYGNUM_HAL_INTERRUPT_RESERVED_62 62 -#define CYGNUM_HAL_INTERRUPT_RESERVED_63 63 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 64 -#define CYGNUM_HAL_INTERRUPT_RESERVED_65 65 -#define CYGNUM_HAL_INTERRUPT_RESERVED_66 66 -#define CYGNUM_HAL_INTERRUPT_RESERVED_67 67 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 68 -#define CYGNUM_HAL_INTERRUPT_RESERVED_69 69 -#define CYGNUM_HAL_INTERRUPT_RESERVED_70 70 -#define CYGNUM_HAL_INTERRUPT_RESERVED_71 71 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 72 -#define CYGNUM_HAL_INTERRUPT_RESERVED_73 73 -#define CYGNUM_HAL_INTERRUPT_RESERVED_74 74 -#define CYGNUM_HAL_INTERRUPT_RESERVED_75 75 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 76 -#define CYGNUM_HAL_INTERRUPT_RESERVED_77 77 -#define CYGNUM_HAL_INTERRUPT_RESERVED_78 78 -#define CYGNUM_HAL_INTERRUPT_RESERVED_79 79 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 80 -#define CYGNUM_HAL_INTERRUPT_RESERVED_81 81 -#define CYGNUM_HAL_INTERRUPT_RESERVED_82 82 -#define CYGNUM_HAL_INTERRUPT_RESERVED_83 83 - -#define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 84 -#define CYGNUM_HAL_INTERRUPT_RESERVED_85 85 -#define CYGNUM_HAL_INTERRUPT_RESERVED_86 86 -#define CYGNUM_HAL_INTERRUPT_RESERVED_87 87 - -#define CYGNUM_HAL_INTERRUPT_RESERVED_88 88 -#define CYGNUM_HAL_INTERRUPT_RESERVED_89 89 -#define CYGNUM_HAL_INTERRUPT_RESERVED_90 90 -#define CYGNUM_HAL_INTERRUPT_RESERVED_91 91 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 92 -#define CYGNUM_HAL_INTERRUPT_RESERVED_93 93 -#define CYGNUM_HAL_INTERRUPT_RESERVED_94 94 -#define CYGNUM_HAL_INTERRUPT_RESERVED_95 95 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 96 -#define CYGNUM_HAL_INTERRUPT_RESERVED_97 97 -#define CYGNUM_HAL_INTERRUPT_RESERVED_98 98 -#define CYGNUM_HAL_INTERRUPT_RESERVED_99 99 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 100 -#define CYGNUM_HAL_INTERRUPT_RESERVED_101 101 -#define CYGNUM_HAL_INTERRUPT_RESERVED_102 102 -#define CYGNUM_HAL_INTERRUPT_RESERVED_103 103 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 104 -#define CYGNUM_HAL_INTERRUPT_RESERVED_105 105 -#define CYGNUM_HAL_INTERRUPT_RESERVED_106 106 -#define CYGNUM_HAL_INTERRUPT_RESERVED_107 107 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 108 -#define CYGNUM_HAL_INTERRUPT_RESERVED_109 109 -#define CYGNUM_HAL_INTERRUPT_RESERVED_110 110 -#define CYGNUM_HAL_INTERRUPT_RESERVED_111 111 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 112 -#define CYGNUM_HAL_INTERRUPT_RESERVED_113 113 -#define CYGNUM_HAL_INTERRUPT_RESERVED_114 114 -#define CYGNUM_HAL_INTERRUPT_RESERVED_115 115 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 116 -#define CYGNUM_HAL_INTERRUPT_RESERVED_117 117 -#define CYGNUM_HAL_INTERRUPT_RESERVED_118 118 -#define CYGNUM_HAL_INTERRUPT_RESERVED_119 119 - -#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 120 -#define CYGNUM_HAL_INTERRUPT_RESERVED_121 121 -#define CYGNUM_HAL_INTERRUPT_RESERVED_122 122 -#define CYGNUM_HAL_INTERRUPT_RESERVED_123 123 - -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX 123 - -#define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4)) - -#endif - -// The vector used by the Real time clock - -#ifdef CYG_HAL_MN10300_SIM -# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5 -//# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_EXTERNAL_1 -#else -# ifdef CYG_HAL_MN10300_MN103000 -# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_8 -# endif -# ifdef CYG_HAL_MN10300_MN103002 -# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5 -# endif -#endif - -//-------------------------------------------------------------------------- -// Timer control registers. - -// On simulator we use simulated external interrupt - -#if defined(CYG_HAL_MN10300_MN103002) - -// On the mn103002 we use timers 4 and 5 - -#define TIMER4_CR 0x340010a0 -#define TIMER4_BR 0x34001090 -#define TIMER4_MD 0x34001080 - -#define TIMER5_CR 0x340010a2 -#define TIMER5_BR 0x34001092 -#define TIMER5_MD 0x34001082 - -#define TIMER_CR TIMER5_CR -#define TIMER_BR TIMER5_BR -#define TIMER_MD TIMER5_MD - -#define TIMER0_MD 0x34001000 -#define TIMER0_BR 0x34001010 -#define TIMER0_CR 0x34001020 - -#elif defined(CYG_HAL_MN10300_MN103000) - -// on the mn103000 we use timers 4 and 5 -#define TIMER4_CR 0x340010a0 -#define TIMER4_BR 0x34001090 -#define TIMER4_MD 0x34001080 - -#define TIMER5_CR 0x340010a2 -#define TIMER5_BR 0x34001092 -#define TIMER5_MD 0x34001082 - -#define TIMER_CR TIMER5_CR -#define TIMER_BR TIMER5_BR -#define TIMER_MD TIMER5_MD - -#define TIMER0_MD 0x34001000 -#define TIMER0_BR 0x34001010 -#define TIMER0_CR 0x34001020 - -#endif +#include <cyg/hal/var_intr.h> //-------------------------------------------------------------------------- // Static data used by HAL @@ -478,7 +65,16 @@ externC volatile CYG_ADDRESS hal_inte externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; // MN10300 interrupt control registers, mapped by linker script. -externC volatile cyg_uint16 mn10300_interrupt_control[0x300/2]; +externC volatile cyg_uint16 mn10300_interrupt_control[]; + +//-------------------------------------------------------------------------- +// Default ISR +// The #define is used to test whether this routine exists, and to allow +// us to call it. + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_DEFAULT_ISR hal_default_isr //-------------------------------------------------------------------------- // Interrupt state storage @@ -486,8 +82,14 @@ externC volatile cyg_uint16 mn10300_ typedef cyg_uint32 CYG_INTERRUPT_STATE; //-------------------------------------------------------------------------- + #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +// Routine to execute DSRs using separate interrupt stack +externC void hal_interrupt_stack_call_pending_DSRs(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ + hal_interrupt_stack_call_pending_DSRs() + // these are offered solely for stack usage testing // if they are not defined, then there is no interrupt stack. #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base @@ -496,6 +98,7 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; // extern char HAL_INTERRUPT_STACK_BASE[]; // extern char HAL_INTERRUPT_STACK_TOP[]; // is recommended + #endif //-------------------------------------------------------------------------- @@ -548,7 +151,9 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; // only one interrupt per controller, so we can have just one ISR per // controller, except for the NMI vectors which occupy the first 3 slots. -#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN +#ifndef HAL_TRANSLATE_VECTOR + +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ { \ @@ -569,61 +174,51 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; #else -#if defined(CYG_HAL_MN10300_MN103000) - #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_) -#elif defined(CYG_HAL_MN10300_MN103002) - -#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ - _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \ - (_vector_) : \ - (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3)) - #endif #endif - //-------------------------------------------------------------------------- // Interrupt and VSR attachment macros -#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ - CYG_MACRO_START \ - cyg_uint32 _index_; \ - HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ - \ - if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL ) \ - (_state_) = 0; \ - else \ - (_state_) = 1; \ - CYG_MACRO_END +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ +CYG_MACRO_END -#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ -{ \ - cyg_uint32 _index_; \ - HAL_TRANSLATE_VECTOR(_vector_,_index_); \ - \ - if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL ) \ - { \ - hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ - hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ - hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ - } \ -} +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR(_vector_,_index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ + { \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ + hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ + } \ +CYG_MACRO_END #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ -{ \ +CYG_MACRO_START \ cyg_uint32 _index_; \ HAL_TRANSLATE_VECTOR(_vector_,_index_); \ \ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ { \ - hal_interrupt_handlers[_index_] = (CYG_ADDRESS)NULL; \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ hal_interrupt_data[_index_] = 0; \ hal_interrupt_objects[_index_] = 0; \ } \ -} +CYG_MACRO_END #define HAL_VSR_GET( _vector_, _pvsr_ ) \ *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_]; @@ -691,30 +286,11 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; _icr_ = mn10300_interrupt_control[_index_]; \ } -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ -{ \ - cyg_uint32 _v_ = _vector_; \ - cyg_uint16 _val_ = 0; \ - cyg_uint16 _reg_; \ - \ - /* adjust vector to bit offset in EXTMD */ \ - _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \ - _v_ >>= 1; \ - \ - /* set bits according to requirements */ \ - if( _up_ ) _val_ |= 1; \ - if( !(_level_) ) _val_ |= 2; \ - \ - /* get EXTMD */ \ - _reg_ = mn10300_interrupt_control[0x180>>1]; \ - \ - /* clear old value and set new */ \ - _reg_ &= ~(3<<_v_); \ - _reg_ |= _val_<<_v_; \ - \ - /* restore EXTMD */ \ - mn10300_interrupt_control[0x180>>1] = _reg_; \ -} +#if !defined(HAL_INTERRUPT_CONFIGURE) + +#error HAL_INTERRUPT_CONFIGURE not defined by variant + +#endif #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ { \ @@ -734,120 +310,8 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE; } //-------------------------------------------------------------------------- -// Clock control - - -#if 0 // defined(CYG_HAL_MN10300_SIM) - -#define OEA_DEV 0x31000000 - -#define HAL_SWAP(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)| \ - (((x)&0xff0000)>>8)|(((x)&0xff000000)>>24)) - -#define PAL_COUNTDOWN_TIMER 0x20 // one shot on IR0 -#define PAL_COUNTDOWN_VALUE 0x24 -#define PAL_PERIODIC_TIMER 0x28 // repeating on IR1 -#define PAL_PERIODIC_VALUE 0x2c - - -// IRQ1 set to receive clock intrs -#define HAL_CLOCK_INITIALIZE( _period_ ) \ -{ \ - volatile cyg_uint32 *timer = (cyg_uint32 *) \ - (OEA_DEV + PAL_PERIODIC_TIMER); \ - cyg_uint32 p = _period_; \ - \ - *timer = HAL_SWAP(p); \ -} - -#elif defined(CYG_HAL_MN10300_MN103000) - -#define HAL_CLOCK_INITIALIZE( _period_ ) \ -{ \ - volatile cyg_uint16 *timer_ctr = (cyg_uint16 *)TIMER_BR; \ - volatile cyg_uint16 *timer_mode = (cyg_uint16 *)TIMER_MD; \ - volatile cyg_uint8 *timer_a_mode = (cyg_uint8 *)0x34001084; \ - \ - *timer_a_mode = 0x04; \ - \ - *timer_ctr = 0xf000; \ - \ - *timer_mode = 0x0013; \ - *timer_mode = 0x4013; \ - *timer_mode = 0x0013; \ - *timer_mode = 0x8013; \ -} - -#elif defined(CYG_HAL_MN10300_MN103002) - -#define HAL_CLOCK_INITIALIZE( _period_ ) \ -{ \ - volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \ - volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \ - volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \ - volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \ - \ - /* Set timers 4 and 5 into cascade mode */ \ - \ - *timer5_br = (_period_)>>16; \ - \ - *timer5_md = 0x40; \ - *timer5_md = 0x83; \ - \ - *timer4_br = (_period_)&0x0000FFFF; \ - \ - *timer4_md = 0x40; \ - *timer4_md = 0x80; \ -} - -#else - -#error Undefined MN10300 model - -#endif - -#define HAL_CLOCK_RESET( _vector_, _period_ ) - -#if 0 //def CYG_HAL_MN10300_SIM - -// This timer counts down, so subtract from set value. -#define HAL_CLOCK_READ( _pvalue_ ) \ -{ \ - volatile cyg_uint32 *timer = (cyg_uint32 *) \ - (OEA_DEV + PAL_PERIODIC_TIMER); \ - volatile cyg_uint32 *value = (cyg_uint32 *) \ - (OEA_DEV + PAL_PERIODIC_VALUE); \ - cyg_uint32 t,v; \ - t = *timer; \ - v = *value; \ - *(_pvalue_) = HAL_SWAP(t) - HAL_SWAP(v); \ -} - -#else // CYG_HAL_MN10300_SIM not -#define HAL_CLOCK_READ( _pvalue_ ) \ -{ \ - volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \ - volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \ - \ - cyg_uint16 t5; \ - cyg_uint16 t4; \ - \ - /* Loop reading the two timers until we can read t5 twice */ \ - /* with the same value. This avoids getting silly times if */ \ - /* the timers carry between reading the two regs. */ \ - do { \ - t5 = *timer5_cr; \ - t4 = *timer4_cr; \ - } while( t5 != *timer5_cr ); \ - \ - *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \ -} - -// FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since -// this means the HAL gets configured by kernel options even when the -// kernel is disabled! - -#endif // CYG_HAL_MN10300_SIM +// Clock control. +// This is almost all handled in the var_intr.h. #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY #define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
--- a/packages/hal/mn10300/arch/current/include/pkgconf/hal_mn10300.h +++ b/packages/hal/mn10300/arch/current/include/pkgconf/hal_mn10300.h @@ -49,7 +49,6 @@ display "MN10300 architecture" type radio parent CYGPKG_HAL - target mn10300 description " The MN10300 architecture HAL package provides generic support for this processor architecture. It is also @@ -57,6 +56,14 @@ package." } + cdl_package CYGPKG_HAL_MN10300_VARIANTS { + display "MN10300 family variants" + type dummy + parent CYGPKG_HAL_MN10300 + description "The MN10300/AM3x family of processors have a number of + architectural variants. You must choose one." + } + }}CFG_DATA */ /* -------------------------------------------------------------------*/
--- a/packages/hal/mn10300/arch/current/src/PKGconf.mak +++ b/packages/hal/mn10300/arch/current/src/PKGconf.mak @@ -34,14 +34,12 @@ include ../../../../../pkgconf/pkgconf.m LIBRARY := libtarget.a COMPILE := hal_misc.c context.S mn10300_stub.c OTHER_OBJS := -OTHER_TARGETS := vectors.stamp ldscript.stamp -OTHER_DEPS := $(PACKAGE)_vectors.d ldscript.d -OTHER_CLEAN := vectors.clean ldscript.clean +OTHER_TARGETS := vectors.stamp +OTHER_DEPS := $(PACKAGE)_vectors.d +OTHER_CLEAN := vectors.clean include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src -.PHONY: ldscript.clean - vectors.stamp: $(PACKAGE)_vectors.o $(CP) $< $(PREFIX)/lib/vectors.o @$(TOUCH) $@ @@ -52,15 +50,3 @@ vectors.clean: $(PACKAGE)_vectors.o: $(BUILD_TREE)/pkgconf/pkgconf.mak \ $(BUILD_TREE)/pkgconf/makevars $(PACKAGE_RULES_FILE) - -ldscript.stamp: mn10300.ld - $(CC) -E -P -Wp,-MD,ldscript.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $(PREFIX)/lib/target.ld $< - @echo > ldscript.d - @echo $@ ':' $< '\' >> ldscript.d - @tail +2 ldscript.tmp >> ldscript.d - @rm ldscript.tmp - $(TOUCH) $@ - -ldscript.clean: - $(RM) -f $(PREFIX)/lib/target.ld - $(RM) -f ldscript.stamp
--- a/packages/hal/mn10300/arch/current/src/context.S +++ b/packages/hal/mn10300/arch/current/src/context.S @@ -43,19 +43,8 @@ #include <pkgconf/hal.h> -#------------------------------------------------------------------------------ -# Configure to use either a minimal or maximal thread state - -#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM +#include <cyg/hal/arch.inc> -#define SAVE_REGS [d2,d3,a2,a3,other] - -#else - -#define SAVE_REGS [d2,d3,a2,a3,other] - -#endif - #------------------------------------------------------------------------------ # hal_thread_switch_context # Switch thread contexts @@ -65,9 +54,12 @@ .global _hal_thread_switch_context _hal_thread_switch_context: add -8,sp # space for SP and PSW - movm SAVE_REGS,(sp) # dump all registers onto stack - mov psw,d2 # put PSW into saved state - mov d2,(52,sp) + mov d2,a0 # move d2->a0 since PSW can only be + # saved to a data register + hal_cpu_get_psw d2 # save PSW to d2 + mov d2,(4,sp) # store in stack loc + mov a0,d2 # retrieve old d2 value + hal_cpu_save_all # save entire register set mov d1,a2 # move save loc addr to A2 mov sp,(0,a2) # store SP in save location @@ -86,9 +78,11 @@ mov d0,a2 # move next sp loc to a2 mov (0,a2),sp # load SP with new value - movm (sp),SAVE_REGS # load all registers - add 8,sp # skip SP & PSW, we never restore them. - ret [],0 + hal_cpu_load_all # load whole register set + mov (4,sp),d1 # retrieve saved PSW + hal_cpu_set_psw d1 # and restore it + add 8,sp # skip saved SP and PSW + ret [],0 # and return ##----------------------------------------------------------------------------- ## HAL longjmp(), setjmp() implementations
--- a/packages/hal/mn10300/arch/current/src/hal_misc.c +++ b/packages/hal/mn10300/arch/current/src/hal_misc.c @@ -43,6 +43,7 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> #include <cyg/hal/hal_arch.h> @@ -98,44 +99,6 @@ cyg_hal_invoke_constructors(void) } // cyg_hal_invoke_constructors() -void -cyg_hal_enable_caches(void) -{ -#ifdef CYG_HAL_MN10300_STDEVAL1 - - // On the real hardware we also enable the cache. - // doing this here is a temporary measure until we - // have a proper platform specific place to do it. - - // Note that the hardware seems to come up with the - // caches containing random data. Hence they must be - // invalidated before being enabled. - - HAL_ICACHE_INVALIDATE_ALL(); - HAL_ICACHE_ENABLE(); - HAL_DCACHE_INVALIDATE_ALL(); - HAL_DCACHE_ENABLE(); - -#endif - -} // cyg_hal_enable_caches() - -void -cyg_hal_debug_init(void) -{ -#if defined(CYGPKG_KERNEL) && \ - defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ - defined(CYG_HAL_USE_ROM_MONITOR) && \ - defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) - { - extern CYG_ADDRESS hal_virtual_vector_table[32]; - extern void patch_dbg_syscalls(void * vector); - patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); - } -#endif - -} - /*------------------------------------------------------------------------*/ /* Determine the index of the ls bit of the supplied mask. */ @@ -192,8 +155,21 @@ externC void __handle_exception (void); externC HAL_SavedRegisters *_hal_registers; void -cyg_hal_exception_handler(HAL_SavedRegisters *regs) +cyg_hal_exception_handler(HAL_SavedRegisters *regs, CYG_WORD32 isr) { + CYG_WORD vector = regs->vector; + +#if defined(CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR) && defined(CYGNUM_HAL_EXCEPTION_JTAG) + if( vector == CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR ) + { + // Translate vector number via ISR bits into the full + // set. + vector = CYGNUM_HAL_EXCEPTION_JTAG+hal_lsbit_index( isr ); + + regs->vector = vector; + } +#endif + #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS // Set the pointer to the registers of the current exception @@ -205,8 +181,6 @@ cyg_hal_exception_handler(HAL_SavedRegis #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) - CYG_WORD vector = regs->vector; - if( vector == CYGNUM_HAL_INTERRUPT_WATCHDOG ) { // Special case the watchdog timer exception, look for an @@ -247,33 +221,35 @@ cyg_hal_exception_handler(HAL_SavedRegis } /*------------------------------------------------------------------------*/ -/* Cache functions. */ +/* default ISR */ -#if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002) -void cyg_hal_dcache_store(CYG_ADDRWORD base, int size) +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) { - volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0; - volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1; - register int i; - register CYG_ADDRWORD state; - - HAL_DCACHE_IS_ENABLED(state); - if (state) - HAL_DCACHE_DISABLE(); +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) && \ + defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ + defined(HAL_CTRLC_ISR) - way0 += base & 0x000007f0; - way1 += base & 0x000007f0; - for( i = 0; i < size; i += HAL_DCACHE_LINE_SIZE ) +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + if( vector == CYGHWR_HAL_GDB_PORT_VECTOR ) +#endif { - *(CYG_ADDRWORD *)way0 = 0; - *(CYG_ADDRWORD *)way1 = 0; - way0 += HAL_DCACHE_LINE_SIZE; - way1 += HAL_DCACHE_LINE_SIZE; + cyg_uint32 result = HAL_CTRLC_ISR( vector, data ); + if( result != 0 ) return result; } - if (state) - HAL_DCACHE_ENABLE(); + +#endif + + CYG_TRACE1(true, "Interrupt: %d", vector); + CYG_FAIL("Spurious Interrupt!!!"); + return 0; } -#endif + +/*------------------------------------------------------------------------*/ +/* Idle thread activity. */ + +externC void hal_idle_thread_action(cyg_uint32 loop_count) +{ +} /*------------------------------------------------------------------------*/ /* End of hal_misc.c */
deleted file mode 100644 --- a/packages/hal/mn10300/arch/current/src/mn10300.ld +++ /dev/null @@ -1,118 +0,0 @@ -//=========================================================================== -// -// MLT linker script for MN10300 -// adapted from packages\hal\mn10300\stdeval1\v1_1\src\stdeval1.ld -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -#include <pkgconf/system.h> -STARTUP(vectors.o) -ENTRY(reset_vector) -#ifdef EXTRAS -INPUT(extras.o) -#endif -GROUP(libtarget.a libgcc.a) - - -#define ALIGN_LMA 4 -#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) -#define LMA_EQ_VMA -#define FORCE_OUTPUT . = . - -#define SECTIONS_BEGIN - -#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ - .rom_vectors _vma_ : _lma_ \ - { FORCE_OUTPUT; KEEP (*(.vectors)) } \ - > _region_ - -#define SECTION_text(_region_, _vma_, _lma_) \ - .text _vma_ : _lma_ \ - { _stext = ABSOLUTE(.); \ - *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ - > _region_ \ - _etext = .; PROVIDE (etext = .); - -#define SECTION_fini(_region_, _vma_, _lma_) \ - .fini _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.fini) } \ - > _region_ - -#define SECTION_rodata(_region_, _vma_, _lma_) \ - .rodata _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.rodata*) } \ - > _region_ - -#define SECTION_rodata1(_region_, _vma_, _lma_) \ - .rodata1 _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.rodata1) } \ - > _region_ - -#define SECTION_fixup(_region_, _vma_, _lma_) \ - .fixup _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.fixup) } \ - > _region_ - -#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ - .gcc_except_table _vma_ : _lma_ \ - { FORCE_OUTPUT; *(.gcc_except_table) } \ - > _region_ - -#define SECTION_data(_region_, _vma_, _lma_) \ - .data _vma_ : _lma_ \ - { __ram_data_start = ABSOLUTE (.); *(.data*) *(.data1) \ - . = ALIGN(4); \ - ___DEVTAB__ = ABSOLUTE (.); KEEP (*(SORT (.devtab*))) ___DEVTAB_END__ = ABSOLUTE (.); \ - _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ - _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ - . = ALIGN (4); \ - __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \ - __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \ - _GOT_START = ABSOLUTE (.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.) + 32768; _SDA_BASE_ = ABSOLUTE (.); \ - *(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \ - *(.dynamic) *(.sdata*) *(.sbss*) } \ - > _region_ \ - __rom_data_start = LOADADDR (.data); \ - __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); - -#define SECTION_bss(_region_, _vma_, _lma_) \ - .bss _vma_ : _lma_ \ - { __bss_start = ABSOLUTE (.); \ - *(.scommon) *(.dynbss) *(.bss) *(COMMON) \ - __bss_end = ABSOLUTE (.); } \ - > _region_ - -#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); - -#include CYGHWR_MEMORY_LAYOUT_LDI - -_mn10300_interrupt_control = 0x34000100; -_mn10300_interrupt_vectors = 0x20000000; - -#if (defined (CYG_HAL_STARTUP_RAM) && ! defined (CYGPKG_HAL_MN10300_SIM)) -#define VSR_BASE 0x48000000 -_hal_vsr_table = VSR_BASE; -_hal_virtual_vector_table = VSR_BASE + 0x80; -#endif
--- a/packages/hal/mn10300/arch/current/src/mn10300_stub.c +++ b/packages/hal/mn10300/arch/current/src/mn10300_stub.c @@ -27,14 +27,52 @@ #include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id #endif +/*---------------------------------------------------------------------- + * Asynchronous interrupt support + */ + +typedef unsigned char t_inst; + +static struct +{ + t_inst *targetAddr; + t_inst savedInstr; +} asyncBuffer; + +/* Called to asynchronously interrupt a running program. + Must be passed address of instruction interrupted. + This is typically called in response to a debug port + receive interrupt. +*/ + +void +install_async_breakpoint(void *pc) +{ + asyncBuffer.targetAddr = pc; + asyncBuffer.savedInstr = *(t_inst *)pc; + *(t_inst *)pc = (t_inst)HAL_BREAKINST; + __instruction_cache(CACHE_FLUSH); + __data_cache(CACHE_FLUSH); +} + +/*--------------------------------------------------------------------*/ /* Given a trap value TRAP, return the corresponding signal. */ int __computeSignal (unsigned int trap_number) { + if (asyncBuffer.targetAddr != NULL) + { + /* BP installed by serial driver to stop running program */ + *asyncBuffer.targetAddr = asyncBuffer.savedInstr; + __instruction_cache(CACHE_FLUSH); + __data_cache(CACHE_FLUSH); + asyncBuffer.targetAddr = NULL; + return SIGINT; + } return SIGTRAP; } - +/*--------------------------------------------------------------------*/ /* Return the trap number corresponding to the last-taken trap. */ int __get_trap_number (void) @@ -44,6 +82,7 @@ int __get_trap_number (void) return _hal_registers->vector; } +/*--------------------------------------------------------------------*/ /* Set the currently-saved pc register value to PC. This also updates NPC as needed. */
--- a/packages/hal/mn10300/arch/current/src/vectors.S +++ b/packages/hal/mn10300/arch/current/src/vectors.S @@ -49,52 +49,10 @@ #include <pkgconf/kernel.h> #endif - - .extern _cyg_instrument - -##----------------------------------------------------------------------------- -## Register addresses and initialization values +#include <cyg/hal/arch.inc> + - .equ IOBCTR ,0x32000010 - .equ MEMCTR0 ,0x32000020 - .equ MEMCTR1 ,0x32000022 - .equ MEMCTR2 ,0x32000024 - .equ MEMCTR3 ,0x32000026 - .equ MEMCTR4 ,0x32000028 - .equ MEMCTR5 ,0x3200002a - .equ MEMCTR6 ,0x3200002c - .equ MEMCTR7 ,0x3200002e - .equ DRAMCTR ,0x32000040 - .equ REFCNT ,0x32000042 - -#ifdef CYG_HAL_MN10300_STDEVAL1 - .equ INIT_MEMCTR0,0x1200 # 2wait - .equ INIT_MEMCTR1,0x0120 # 1wait-32bit- - .equ INIT_MEMCTR2,0x0065 - .equ INIT_DRAMCTR,0x0287 - .equ INIT_REFCNT,0x00eb -#endif - - .equ P2OUT ,0x36008004 - .equ P2MD ,0x36008024 - .equ P2SS ,0x36008044 - .equ P2DIR ,0x36008064 - - .equ INIT_P2MD,0xf0 - .equ INIT_P2DIR,0xff - -##----------------------------------------------------------------------------- - - .macro led val - movm [d2],(sp) - mov \val,d2 - asl 4,d2 - movbu d2,(P2OUT) - movm (sp),[d2] - .endm - - ##----------------------------------------------------------------------------- .file "vectors.S" @@ -125,8 +83,8 @@ reset_vector: .globl __nmi __nmi: add -4,sp # space for SP - movm [d2,d3,a2,a3,other],(sp) # push all registers - mov (_hal_vsr_table+28),a0 + hal_cpu_save_all # push all registers + mov (_hal_vsr_table+28),a0 jmp (a0) ##----------------------------------------------------------------------------- @@ -135,7 +93,7 @@ reset_vector: .globl __trap __trap: add -8,sp # space for SP and PSW - movm [d2,d3,a2,a3,other],(sp) # push all registers + hal_cpu_save_all # push all registers mov (_hal_vsr_table+32),a0 jmp (a0) @@ -146,7 +104,7 @@ reset_vector: .globl __hardware_vector_\name __hardware_vector_\name: add -4,sp # space for SP - movm [d2,d3,a2,a3,other],(sp) # push all registers + hal_cpu_save_all mov \name,d0 # d0 = vector id mov d0,(0,sp) # save in dummy stack loc mov _hal_vsr_table,a0 # a0 = vsr table @@ -175,44 +133,22 @@ reset_vector: .globl _start _start: -#if defined(CYG_HAL_MN10300_STDEVAL1) - mov INIT_MEMCTR0,d2 - movhu d2,(MEMCTR0) - - mov INIT_MEMCTR1,d2 - movhu d2,(MEMCTR1) - - mov INIT_MEMCTR2,d2 - movhu d2,(MEMCTR2) - - mov INIT_REFCNT,d2 - movhu d2,(REFCNT) - - mov INIT_DRAMCTR,d2 - movhu d2,(DRAMCTR) - - # Set up LED - - mov INIT_P2MD,d2 - movbu d2,(P2MD) - - mov INIT_P2DIR,d2 - movbu d2,(P2DIR) - - -#endif - - # Set up the PSW - - mov 0x0700,d0 - mov d0,psw - # set up stack mov __interrupt_stack,a0 sub 8,a0 mov a0,sp - + + # Initialize hardware + hal_cpu_init + hal_mmu_init + hal_memc_init + hal_diag_init + hal_intc_init + hal_cache_init + hal_timer_init + hal_mon_init + #ifdef CYG_HAL_STARTUP_ROM # Copy data from ROM to RAM @@ -247,60 +183,21 @@ 1: cmp a0,a1 bne 1b 8: - # Install interrupt vectors -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_MN10300_SIM) - mov _mn10300_interrupt_vectors,a0 - mov __hardware_vector_0,d0 - movhu d0,(0,a0) - mov __hardware_vector_1,d0 - movhu d0,(4,a0) - mov __hardware_vector_2,d0 - movhu d0,(8,a0) - mov __hardware_vector_3,d0 - movhu d0,(12,a0) - mov __hardware_vector_4,d0 - movhu d0,(16,a0) - mov __hardware_vector_5,d0 - movhu d0,(20,a0) - mov __hardware_vector_6,d0 - movhu d0,(24,a0) -#endif -#if defined(CYG_HAL_STARTUP_RAM) && !defined(CYG_HAL_MN10300_SIM) + # Call variant and platform HAL + # initialization routines. - # init vsr table in SRAM where the ROM - # vectors the interrupts. + .extern _hal_variant_init + call _hal_variant_init,[],0 - mov _hal_vsr_table,a0 - mov __default_interrupt_vsr,d0 - mov d0,(0,a0) - mov d0,(4,a0) - mov d0,(8,a0) -#ifndef CYG_HAL_USE_ROM_MONITOR_CYGMON - # When using Cygmon, leave level 3 for GDB - # Ctrl-C interrupts. - mov d0,(12,a0) -#endif - mov d0,(16,a0) - mov d0,(20,a0) - mov d0,(24,a0) - mov __default_nmi_vsr,d0 - mov d0,(28,a0) - mov __default_trap_vsr,d0 - mov d0,(32,a0) -#endif + .extern _hal_platform_init + call _hal_platform_init,[],0 # Call constructors .extern _cyg_hal_invoke_constructors call _cyg_hal_invoke_constructors,[],0 - .extern _cyg_hal_enable_caches - call _cyg_hal_enable_caches,[],0 - - .extern _cyg_hal_debug_init - call _cyg_hal_debug_init,[],0 - #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS .extern _initialize_stub call _initialize_stub,[],0 @@ -309,44 +206,14 @@ 8: # Call cyg_start clr d0 mov d0,(4,sp) - + .extern _cyg_start call _cyg_start,[],0 -9: +9: bra 9b # Loop if we return ##----------------------------------------------------------------------------- -## Debug code to count interrupts on the led. - -#ifdef CYG_HAL_MN10300_STDEVAL1 - - .macro show_interrupts - mov (led_count),d1 - inc d1 -# cmp 20000,d1 -# ble 2f - mov 0,d1 - movbu (led_value),d0 - movbu d0,(P2OUT) - add 16,d0 - cmp 0x90,d0 - bne 1f - mov 0,d0 -1: - movbu d0,(led_value) -2: - mov d1,(led_count) - .endm - -#else - - .macro show_interrupts - .endm - -#endif - -##----------------------------------------------------------------------------- ## The following macros are defined depending on whether the HAL is configured ## to support the kernel or not. @@ -370,82 +237,6 @@ 2: #endif ##----------------------------------------------------------------------------- -## The following macros are defined depending on whether the Interrupt -## system is using isr tables or chaining. - -#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN - -#if defined(CYG_HAL_MN10300_MN103000) - -#define CYG_ISR_TABLE_SIZE 7 - - # decode the interrupt - .macro decode_interrupt dreg,areg,dreg1 - mov _mn10300_interrupt_control,\areg - movhu (0x100,\areg),\dreg # dreg = IAGR - movhu (\dreg,\areg),\dreg1 # dreg1 = IGR[dreg] - and 0xf,\dreg1 # dreg1 = ID0..3 - mov hal_lsbit_table,\areg # areg = ls bit table - movbu (\dreg1,\areg),\dreg1 # dreg1 = ls bit index - add \dreg,\dreg1 # dreg1 = word index of isr - mov (0,a2),\dreg # dreg = vector priority - mov \dreg1,(0,a2) # store real vector in saved state - asl 2,\dreg # dreg = byte index of isr - .endm - -#elif defined(CYG_HAL_MN10300_MN103002) - -#define CYG_ISR_TABLE_SIZE 10 - - # decode the interrupt - .macro decode_interrupt dreg,areg,dreg1 - mov _mn10300_interrupt_control,\areg - movhu (0x100,\areg),\dreg1 # dreg1 = IAGR - mov (0,a2),\dreg # dreg = vector priority - mov \dreg1,(0,a2) # store real vector in saved state - asl 2,\dreg # dreg = byte index of isr - add 12,\dreg # skip NMI vectors - .endm - -#endif - -#else - -#if defined(CYG_HAL_MN10300_MN103000) - -#define CYG_ISR_TABLE_SIZE 100 - - # decode the interrupt - .macro decode_interrupt dreg,areg,dreg1 - mov _mn10300_interrupt_control,\areg - movhu (0x100,\areg),\dreg # dreg = IAGR - movhu (\dreg,\areg),\dreg1 # dreg1 = IGR[dreg] - and 0xf,\dreg1 # dreg1 = ID0..3 - mov hal_lsbit_table,\areg # areg = ls bit table - movbu (\dreg1,\areg),\dreg1 # dreg1 = ls bit index - add \dreg1,\dreg # dreg = word index of isr - mov \dreg,(0,a2) # store real vector in saved state - asl 2,\dreg # dreg = byte index of isr - .endm - - -#elif defined(CYG_HAL_MN10300_MN103002) - -#define CYG_ISR_TABLE_SIZE 34 - - # decode the interrupt - .macro decode_interrupt dreg,areg,dreg1 - mov _mn10300_interrupt_control,\areg - movhu (0x100,\areg),\dreg # dreg = IAGR - mov \dreg,(0,a2) # store real vector in saved state - add 12,\dreg # skip NMI vectors - .endm - -#endif - -#endif - -##----------------------------------------------------------------------------- ## Default interrupt VSR .text @@ -455,6 +246,8 @@ 2: # We come here with all the registers pushed # onto the stack. + hal_diag_intr_start + increment_sched_lock #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK @@ -478,17 +271,16 @@ 8: # stack. We will be executing either on the same stack # or on the interrupt stack, depending on config options. - decode_interrupt d3,a3,d0 + hal_intc_decode d3,a3,d0 # Here D3 contains the table byte offset of the vector to - # call. On the MN103000 this needs to be shifted right by - # two to derive the vector. On the MN103002 this correponds - # exactly to the vector used to attach it. + # call. #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) # Call cyg_instrument to record that this interrupt is being raised. - + + .extern _cyg_instrument add -16,sp # make space for return link + args mov 0x0301,d0 # d0 = type = INTR,RAISE mov (0,a2),d1 # d1 = arg1 = vector @@ -521,7 +313,18 @@ 8: or 0x0800,psw -#endif +#endif +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + + # If we have Ctrl-C support enabled, save a pointer to the + # saved CPU state here so we can plant a breakpoint there if + # this is a ^C. + + .extern _hal_saved_interrupt_state + mov a2,(_hal_saved_interrupt_state) + +#endif + mov _hal_interrupt_handlers,a0 # a0 = isr table mov (d3,a0),a0 # a0 = isr @@ -530,9 +333,7 @@ 8: mov (0,a2),d0 # d0 = vector. (d3 is... # ...adjusted for table reads) -#if defined(CYG_HAL_MN10300_MN103000) - lsr 2,d0 # d0 = vector number -#endif + add -16,sp # make space for return link calls (a0) # call isr @@ -580,14 +381,6 @@ 2: # _interrupt_end() to post the DSR and decrement the scheduler # lock. - # interrupt_end must be called with interrupts enabled. - # At this point we restore the PSW of the code we interrupted - # to get the IPL bits back. By definition this PSW must have - # interrupts enabled. - mov (52,a2),d2 - - mov d2,psw - mov a2,(12,sp) # arg3 = saved state. calls _interrupt_end # call interrupt end fn @@ -595,26 +388,46 @@ 2: add 16,sp # pop return link - show_interrupts +# show_interrupts + + hal_diag_restore - movm (sp),[d2,d3,a2,a3,other] # pop regs + hal_cpu_load_all add 4,sp rti # and return -hal_lsbit_table: - .byte 0, 0, 1, 0 - .byte 2, 0, 1, 0 - .byte 3, 0, 1, 0 - .byte 2, 0, 1, 0 +##----------------------------------------------------------------------------- +## Execute pending DSRs on the interrupt stack with interrupts enabled. +## Note: this can only be called from code running on a thread stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .extern _cyg_interrupt_call_pending_DSRs + .global _hal_interrupt_stack_call_pending_DSRs +_hal_interrupt_stack_call_pending_DSRs: + movm [d2,a2],(sp) # save some work regs + mov __interrupt_stack,a0 # interrupt stack pointer + mov sp,a2 # save current SP + mov a0,sp # set SP to interrupt stack + hal_cpu_get_psw d2 # save PSW + hal_cpu_int_enable # enable interrupts + # Call kernel code to invoke DSRs. + calls _cyg_interrupt_call_pending_DSRs + + # On return the old SP in a2 and the old PSW in d2 will + # have been preserved by the calling conventions. + + hal_cpu_int_merge d2 # Restore previous PSW + mov a2,sp # restore old SP + movm (sp),[d2,a2] # Retrieve old work regs + ret [],0 # and return + +#endif + ##----------------------------------------------------------------------------- ## Default NMI VSR -#define NMICR 0x34000100 -#define DCR 0x20000030 -#define ISR 0x20000034 - .globl _cyg_hal_exception_handler .text @@ -624,6 +437,8 @@ hal_lsbit_table: # We come here with all the registers saved # on the stack. + hal_diag_excpt_start + # Decode the cause of the NMI and cancel all the bits in all # the registers. We need to clear any bits set in the ISR and # then clear any bits set in the NMICR. Note that we can only @@ -634,8 +449,8 @@ hal_lsbit_table: movhu (DCR),d1 # D1 = Debug Control Register mov d1,d2 # D2 = copy of DCR movhu (ISR),d3 # D3 = Interrupt Status Register - - or 0x0010,d1 # Set DE bit + + or DCR_DE,d1 # Set DE bit movhu d1,(DCR) movhu d3,(ISR) # clear ISR bits @@ -651,35 +466,33 @@ hal_lsbit_table: ## 1 = Watchdog ## 2 = System Error + add 9,d1 # offset into exception number space - # It appears that there is an undocumented extra bit - # in the PSW that masks the delivery of NMIs. It is in - # the upper 16 bits of the register that we cannot access - # directly. So, to clear it, we must set up a fake interrupt - # state and do an RTI to load the PSW. We need to do this if - # we are going to be able to set breakpoints in NMI handlers. - # Note that the AM33 has a documented NMID at bit 17 of the - # extended PSW (along with instructions to access it). - - mov PSW,d3 # D3 = PSW - and 0xFFFF,d3 - mov 1f,d2 # D2 = Next PC - movm [d2,d3],(sp) # Push - rti # and load into CPU -1: - + hal_cpu_clear_nmid + mov sp,a1 # a1 = saved state mov a1,d0 # d0 = arg1 = saved state add -16,sp # return link + args - mov d1,(16,sp) # save in spare save slot + mov d1,(16,sp) # save initial vector in spare save slot + mov d3,d1 # d1 = arg2 = ISR value calls _cyg_hal_exception_handler # call C code + add 16,sp # pop args - movm (sp),[d2,d3,a2,a3,other] # pop all registers + + hal_cpu_load_all + add 4,sp rti + .globl hal_lsbit_table +hal_lsbit_table: + .byte 0, 0, 1, 0 + .byte 2, 0, 1, 0 + .byte 3, 0, 1, 0 + .byte 2, 0, 1, 0 + ##----------------------------------------------------------------------------- ## Default TRAP VSR @@ -695,16 +508,16 @@ 1: mov d1,(0,sp) # save in spare save slot calls _cyg_hal_exception_handler # call C code add 8,sp # pop args - movm (sp),[d2,d3,a2,a3,other] # pop all registers + hal_cpu_load_all add 4,sp rets - + ##----------------------------------------------------------------------------- ## VSR table. The VSRs pointed to by this table are called from the stubs ## connected to the hardware. -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_MN10300_SIM) - +#ifndef CYG_HAL_MN10300_VSR_TABLE_DEFINED + .data .globl _hal_vsr_table @@ -719,17 +532,39 @@ 1: .long __default_nmi_vsr .long __default_trap_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr + .long __default_nmi_vsr #endif - + ##----------------------------------------------------------------------------- ## Interrupt tables - .section ".bss" + .data + .extern _hal_default_isr + .globl _hal_interrupt_handlers _hal_interrupt_handlers: .rept CYG_ISR_TABLE_SIZE - .long 0 + .long _hal_default_isr .endr .globl _hal_interrupt_data @@ -765,16 +600,9 @@ 1: .long 0,0,0,0,0,0,0,0 ##----------------------------------------------------------------------------- - -#ifdef CYG_HAL_MN10300_STDEVAL1 + .data -## Keep alignment to work around compiler/linker bug -led_count: .long 0 -led_value: .byte 0x40 -led_foo1: .byte 0x00 -led_foo2: .byte 0x00 -led_foo3: .byte 0x00 -#endif + hal_diag_data ##----------------------------------------------------------------------------- ## end of vectors.S
--- a/packages/hal/mn10300/stdeval1/current/ChangeLog +++ b/packages/hal/mn10300/stdeval1/current/ChangeLog @@ -1,3 +1,69 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal_mn10300_am32_stdeval1.h: + Rename to include/pkgconf/hal_mn10300_am31_stdeval1.h, changing + all mentions of am32 to am31 + + * include/pkgconf/mlt_mn10300_am32_stdeval1_ram.ldi: + * include/pkgconf/mlt_mn10300_am32_stdeval1_rom.ldi: + * include/pkgconf/mlt_mn10300_am32_stdeval1_ram.mlt: + * include/pkgconf/mlt_mn10300_am32_stdeval1_rom.mlt: + Rename to: + include/pkgconf/mlt_mn10300_am31_stdeval1_ram.ldi: + include/pkgconf/mlt_mn10300_am31_stdeval1_rom.ldi: + include/pkgconf/mlt_mn10300_am31_stdeval1_ram.mlt: + include/pkgconf/mlt_mn10300_am31_stdeval1_rom.mlt: + + * src/PKGconf.mak: + Rename package name from hal_mn10300_am32_stdeval1 to + hal_mn10300_am31_stdeval1 + + * src/hal_diag.c: + Rename all mentions of am32 to am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c: Tidied up cyg_hal_user_break(). + + * src/hal_diag.c: Added interrupt acknowledgements to serial line + read routines. Tidied up Ctrl-C detection when reading O packet + ack. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal_mn10300_am32_stdeval1.h: + Rename all mn10300_stdeval1 -> mn10300_am32_stdeval1 + Ensure CYGPKG_HAL_MN10300_AM32_STDEVAL1 requires CYGPKG_HAL_MN10300_AM32 + + 1999-06-29 Nick Garnett <nickg@cygnus.co.uk> + + * include/platform.inc: + * include/plf_intr.h: + * src/plf_misc.c: + Added these files to contain platform specific code for the HAL. + + * src/hal_diag.c + Modified to work with new naming conventions. + + * include/pkgconf/hal_mn10300_stdeval1.h: + * include/pkgconf/mlt_mn10300_stdeval1_ram.ldi: + * include/pkgconf/mlt_mn10300_stdeval1_ram.mlt: + * include/pkgconf/mlt_mn10300_stdeval1_rom.ldi: + * include/pkgconf/mlt_mn10300_stdeval1_rom.mlt: + * include/pkgconf/hal_mn10300_am32_stdeval1.h: + * include/pkgconf/mlt_mn10300_am32_stdeval1_ram.ldi: + * include/pkgconf/mlt_mn10300_am32_stdeval1_ram.mlt: + * include/pkgconf/mlt_mn10300_am32_stdeval1_rom.ldi: + * include/pkgconf/mlt_mn10300_am32_stdeval1_rom.mlt: + Renamed these files to match new target naming conventions. + + * src/stdeval1.S: + Removed, since it is no longer needed. + 1999-05-20 Gary Thomas <gthomas@cygnus.co.uk> * include/pkgconf/hal_mn10300_stdeval1.h: Move RTC setup here.
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/pkgconf/hal_mn10300_am31_stdeval1.h @@ -0,0 +1,92 @@ +#ifndef CYGONCE_PKGCONF_HAL_MN10300_AM31_STDEVAL1_H +#define CYGONCE_PKGCONF_HAL_MN10300_AM31_STDEVAL1_H +// ==================================================================== +// +// pkgconf/hal_mn10300_am31_stdeval1.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Contributors: bartv +// Date: 1998-09-02 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_MN10300_AM31_STDEVAL1 { + display "stdeval1 evaluation board" + type radio + parent CYGPKG_HAL_MN10300 + requires CYGPKG_HAL_MN10300_AM31 + platform stdeval1 + description " + The stdeval1 HAL package should be used when targetting the + actual hardware. The same package can also be used when + running on the full MN10300 simulator, since this provides + an accurate simulation of the full hardware including I/O + devices." + } + + cdl_option CYGHWR_HAL_MN10300_AM31_STDEVAL1_STARTUP { + display "Startup type" + parent CYGPKG_HAL_MN10300_AM31_STDEVAL1 + #type count + type enum + legal_values ram rom + startup + description " + When targetting the stdeval1 board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. The + former generally requires that the board is equipped with + ROMs containing the Cygmon ROM monitor or equivalent + software that allows gdb to download the eCos application + on to the board. The latter typically requires that the + eCos application be blown into EPROMs or equivalent + technology." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_MN10300_AM31_STDEVAL1_STARTUP ram + +// Real-time clock/counter specifics + +#define CYGNUM_HAL_RTC_NUMERATOR 1000000000 +#define CYGNUM_HAL_RTC_DENOMINATOR 100 +#define CYGNUM_HAL_RTC_PERIOD 150000 + + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_MN10300_AM31_STDEVAL1_H */ +/* EOF hal_mn10300_am31_stdeval1.h */
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/include/pkgconf/hal_mn10300_stdeval1.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef CYGONCE_PKGCONF_HAL_MN10300_STDEVAL1_H -#define CYGONCE_PKGCONF_HAL_MN10300_STDEVAL1_H -// ==================================================================== -// -// pkgconf/hal_mn10300_stdeval1.h -// -// HAL configuration file -// -// ==================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -// ==================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): bartv -// Contributors: bartv -// Date: 1998-09-02 -// Purpose: To allow the user to edit HAL configuration options. -// Description: -// -//####DESCRIPTIONEND#### -// -// ==================================================================== - - -/* --------------------------------------------------------------------- - {{CFG_DATA - - cdl_package CYGPKG_HAL_MN10300_STDEVAL1 { - display "stdeval1 evaluation board" - type radio - parent CYGPKG_HAL_MN10300 - platform stdeval1 - description " - The stdeval1 HAL package should be used when targetting the - actual hardware. The same package can also be used when - running on the full MN10300 simulator, since this provides - an accurate simulation of the full hardware including I/O - devices." - } - - cdl_option CYGHWR_HAL_MN10300_STDEVAL1_STARTUP { - display "Startup type" - parent CYGPKG_HAL_MN10300_STDEVAL1 - #type count - type enum - legal_values ram rom - startup - description " - When targetting the stdeval1 board it is possible to build - the system for either RAM bootstrap or ROM bootstrap. The - former generally requires that the board is equipped with - ROMs containing the Cygmon ROM monitor or equivalent - software that allows gdb to download the eCos application - on to the board. The latter typically requires that the - eCos application be blown into EPROMs or equivalent - technology." - } - - }}CFG_DATA */ -#define CYGHWR_HAL_MN10300_STDEVAL1_STARTUP ram - -// Real-time clock/counter specifics - -#define CYGNUM_HAL_RTC_NUMERATOR 1000000000 -#define CYGNUM_HAL_RTC_DENOMINATOR 100 -#define CYGNUM_HAL_RTC_PERIOD 150000 - - -/* -------------------------------------------------------------------*/ -#endif /* CYGONCE_PKGCONF_HAL_MN10300_STDEVAL1_H */ -/* EOF hal_mn10300_stdeval1.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_am31_stdeval1_ram.ldi @@ -0,0 +1,47 @@ +//=========================================================================== +// +// MLT linker script export - Tue Jan 12 10:55:38 1999 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x48008000, LENGTH = 0x1f8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x48008000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_am31_stdeval1_ram.mlt @@ -0,0 +1,11 @@ +version 0 +region ram 48008000 1f8000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 48008000 48008000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_am31_stdeval1_rom.ldi @@ -0,0 +1,48 @@ +//=========================================================================== +// +// MLT linker script export - Tue Jan 13 10:14:27 1999 +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + rom : ORIGIN = 0x40000000, LENGTH = 0x80000 + ram : ORIGIN = 0x48000000, LENGTH = 0x200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x40000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x48000000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_am31_stdeval1_rom.mlt @@ -0,0 +1,12 @@ +version 0 +region rom 40000000 80000 1 ! +region ram 48000000 200000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 40000000 40000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data ! +section data 0 1 1 1 1 1 0 0 48000000 bss ! +section bss 0 4 0 1 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_stdeval1_ram.ldi +++ /dev/null @@ -1,47 +0,0 @@ -//=========================================================================== -// -// MLT linker script export - Tue Jan 12 10:55:38 1999 -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -MEMORY -{ - ram : ORIGIN = 0x48008000, LENGTH = 0x1f8000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (ram, 0x48008000, LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_stdeval1_ram.mlt +++ /dev/null @@ -1,11 +0,0 @@ -version 0 -region ram 48008000 1f8000 0 ! -section rom_vectors 0 1 0 1 1 1 1 1 48008000 48008000 text text ! -section text 0 1 0 1 0 1 0 1 fini fini ! -section fini 0 1 0 1 0 1 0 1 rodata rodata ! -section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! -section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 1 0 1 data data ! -section data 0 4 0 1 0 1 0 1 bss bss ! -section bss 0 4 0 1 0 0 0 0 !
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_stdeval1_rom.ldi +++ /dev/null @@ -1,48 +0,0 @@ -//=========================================================================== -// -// MLT linker script export - Tue Jan 13 10:14:27 1999 -// -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Cygnus eCos Public License -// Version 1.0 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://sourceware.cygnus.com/ecos -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Cygnus Operating System, released -// September 30, 1998. -// -// The Initial Developer of the Original Code is Cygnus. Portions created -// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//=========================================================================== - -MEMORY -{ - rom : ORIGIN = 0x40000000, LENGTH = 0x80000 - ram : ORIGIN = 0x48000000, LENGTH = 0x200000 -} - -SECTIONS -{ - SECTIONS_BEGIN - SECTION_rom_vectors (rom, 0x40000000, LMA_EQ_VMA) - SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) - SECTION_data (ram, 0x48000000, FOLLOWING (.gcc_except_table)) - SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) - SECTIONS_END -}
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/include/pkgconf/mlt_mn10300_stdeval1_rom.mlt +++ /dev/null @@ -1,12 +0,0 @@ -version 0 -region rom 40000000 80000 1 ! -region ram 48000000 200000 0 ! -section rom_vectors 0 1 0 1 1 1 1 1 40000000 40000000 text text ! -section text 0 1 0 1 0 1 0 1 fini fini ! -section fini 0 1 0 1 0 1 0 1 rodata rodata ! -section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! -section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! -section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! -section gcc_except_table 0 1 0 1 0 0 0 1 data ! -section data 0 1 1 1 1 1 0 0 48000000 bss ! -section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/platform.inc @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## Stdeval1 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: Stdeval1 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the stdeval1 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +##----------------------------------------------------------------------------- +## Debug code to count interrupts on the led. + + .macro show_interrupts + mov (led_count),d1 + inc d1 +# cmp 20000,d1 +# ble 2f + mov 0,d1 + movbu (led_value),d0 + movbu d0,(P2OUT) + add 16,d0 + cmp 0x90,d0 + bne 1f + mov 0,d0 +1: + movbu d0,(led_value) +2: + mov d1,(led_count) + .endm + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/include/plf_intr.h @@ -0,0 +1,71 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Stdeval1 Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the stdeval1 board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +// Control-C support. + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + +# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SERIAL_1_RX + +externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_CTRLC_ISR hal_ctrlc_isr + +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
--- a/packages/hal/mn10300/stdeval1/current/src/PKGconf.mak +++ b/packages/hal/mn10300/stdeval1/current/src/PKGconf.mak @@ -29,11 +29,11 @@ #=============================================================================== -PACKAGE := hal_mn10300_stdeval1 +PACKAGE := hal_mn10300_am31_stdeval1 include ../../../../../pkgconf/pkgconf.mak LIBRARY := libtarget.a -COMPILE := hal_diag.c stdeval1.S plf_stub.c +COMPILE := hal_diag.c plf_stub.c plf_misc.c OTHER_OBJS := OTHER_TARGETS := OTHER_CLEAN :=
--- a/packages/hal/mn10300/stdeval1/current/src/hal_diag.c +++ b/packages/hal/mn10300/stdeval1/current/src/hal_diag.c @@ -60,7 +60,7 @@ !defined(CYG_KERNEL_DIAG_SERIAL2) && \ !defined(CYG_KERNEL_DIAG_ROMART) -# if defined(CYG_HAL_MN10300_STDEVAL1) +# if defined(CYG_HAL_MN10300_AM31_STDEVAL1) # if defined(CYG_HAL_STARTUP_RAM) @@ -68,7 +68,7 @@ // If loaded into RAM via CYGMON we diag via // serial 2 using GDB protocol - + # define CYG_KERNEL_DIAG_SERIAL2 # define CYG_KERNEL_DIAG_GDB @@ -97,7 +97,7 @@ # endif // defined(CYG_HAL_STARTUP_RAM) -# endif // defined(CYG_HAL_MN10300_STDEVAL1) +# endif // defined(CYG_HAL_MN10300_AM31_STDEVAL1) #endif // if ... @@ -106,7 +106,7 @@ #if defined(CYG_HAL_MN10300_STDEVAL1_ROMART) || defined(CYG_KERNEL_DIAG_ROMART) -#ifdef CYG_HAL_MN10300_STDEVAL1 +#ifdef CYG_HAL_MN10300_AM31_STDEVAL1 #define PROMICE_AILOC 0x40008000 #endif @@ -282,6 +282,9 @@ void hal_diag_read_char_serial1(char *c) *c = *tty_rx; + // We must ack the interrupt caused by that read to avoid + // confusing cygmon. + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_1_RX ); } #if defined(CYG_KERNEL_DIAG_SERIAL1) @@ -295,7 +298,7 @@ void hal_diag_read_char_serial1(char *c) #endif -#if defined(CYG_HAL_MN10300_STDEVAL1) +#if defined(CYG_HAL_MN10300_AM31_STDEVAL1) void led(int x) { @@ -378,6 +381,10 @@ void hal_diag_read_char_serial2(char *c) while( (*tty_status & SIO2_LSTAT_RRDY) == 0 ) continue; *c = *tty_rx; + + // We must ack the interrupt caused by that read to avoid + // confusing cygmon. + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_2_RX ); } #if defined(CYG_KERNEL_DIAG_SERIAL2) @@ -443,41 +450,18 @@ void hal_diag_write_char(char c) hal_diag_write_char_serial(hex[(csum>>4)&0xF]); hal_diag_write_char_serial(hex[csum&0xF]); -#if 0 + { char c1; hal_diag_read_char_serial( &c1 ); - // We must ack the interrupt caused by that read to avoid - // confusing the GDB stub ROM. - HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_EXTERNAL_2 ); - if( c1 == '+' ) break; - ai_writes("hal_diag_read_char_serial("); - ai_write_char(c1); - ai_writes(")\r\n"); - ai_writes("retry\r\n"); - -#if defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) - if( c1 == 3 ) - { - // Ctrl-C: breakpoint. -// HAL_BREAKPOINT(_breakinst); - typedef void bpt_fn(); - bpt_fn *bfn = ((bpt_fn **)0x80000100)[61]; - - bfn(); - - break; - } -#endif + if( cyg_hal_is_break( &c1, 1 ) ) + cyg_hal_user_break( NULL ); } -#else - break; -#endif } pos = 0;
new file mode 100644 --- /dev/null +++ b/packages/hal/mn10300/stdeval1/current/src/plf_misc.c @@ -0,0 +1,149 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +/*------------------------------------------------------------------------*/ + +void hal_platform_init(void) +{ + // Note that the hardware seems to come up with the + // caches containing random data. Hence they must be + // invalidated before being enabled. + + HAL_ICACHE_INVALIDATE_ALL(); + HAL_ICACHE_ENABLE(); + HAL_DCACHE_INVALIDATE_ALL(); + HAL_DCACHE_ENABLE(); + +#if defined(CYGPKG_KERNEL) && \ + defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYG_HAL_USE_ROM_MONITOR) && \ + defined(CYG_HAL_USE_ROM_MONITOR_CYGMON) + { + extern CYG_ADDRESS hal_virtual_vector_table[32]; + extern void patch_dbg_syscalls(void * vector); + patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); + } +#endif +} + +/*------------------------------------------------------------------------*/ +/* Functions to support the detection and execution of a user provoked */ +/* program break. These are usually called from interrupt routines. */ + +cyg_bool cyg_hal_is_break(char *buf, int size) +{ + while( size ) + if( buf[--size] == 0x03 ) return true; + + return false; +} + +void cyg_hal_user_break( CYG_ADDRWORD *regs ) +{ + +#if defined(CYG_HAL_USE_ROM_MONITOR) && defined(CYG_HAL_USE_ROM_MONITOR_GDB_STUBS) + + { + extern CYG_ADDRESS hal_virtual_vector_table[64]; + typedef void install_bpt_fn(void *pc); + CYG_WORD32 retpc = ((CYG_WORD32 *)(®s))[-1]; + CYG_WORD32 pc; + HAL_SavedRegisters *sreg = (HAL_SavedRegisters *)regs; + install_bpt_fn *ibp = (install_bpt_fn *)hal_virtual_vector_table[35]; + + if( regs == NULL ) pc = retpc; + else pc = sreg->pc; + + if( ibp != NULL ) ibp((void *)pc); + } + +#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + + { + extern void breakpoint(void); + breakpoint(); + } + +#else + + HAL_BREAKPOINT(breakinst); + +#endif +} + +/*------------------------------------------------------------------------*/ +/* Control C ISR support */ + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + +struct Hal_SavedRegisters *hal_saved_interrupt_state; + +static void hal_ctrlc_isr_init(void) +{ +} + +cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + +// char c; + + HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR ); + + return 2; +} + +#endif + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */
deleted file mode 100644 --- a/packages/hal/mn10300/stdeval1/current/src/stdeval1.S +++ /dev/null @@ -1,40 +0,0 @@ -##============================================================================= -## -## stdeval1.S -## -## -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Cygnus eCos Public License -# Version 1.0 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://sourceware.cygnus.com/ecos -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Cygnus Operating System, released -# September 30, 1998. -# -# The Initial Developer of the Original Code is Cygnus. Portions created -# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): nickg -## Contributors: nickg -## Date: -## Purpose: -## Description: -## -## -######DESCRIPTIONEND#### -
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,8 @@ +1999-08-16 Bob Koninckx <bob.koninckx@mail.mech.kuleuven.ac.be> + + * src/ppc_stub.c (__clear_single_step): Clear irq_state to prevent + interrupt avalanche. + 1999-06-29 Hugo Tyson <hmt@cygnus.co.uk> * include/hal_intr.h (CYGNUM_HAL_EXCEPTION_DATA_ACCESS): Define
--- a/packages/hal/powerpc/arch/current/src/ppc_stub.c +++ b/packages/hal/powerpc/arch/current/src/ppc_stub.c @@ -149,7 +149,7 @@ void set_pc (target_register_t pc) This may be done by setting breakpoints or setting a single step flag in the saved user registers, for example. */ -static target_register_t irq_state; +static target_register_t irq_state = 0; void __single_step (void) { @@ -178,6 +178,13 @@ void __clear_single_step (void) // may result in a wrong EE. Not a very likely scenario though. msr |= irq_state; + // This function is called much more than its counterpart + // __single_step. Only re-enable interrupts if they where + // disabled during the previous cal to __single_step. Otherwise, + // this function only makes "extra sure" that no trace or branch + // exception will happen. + irq_state = 0; + put_register (PS, msr); }
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,34 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + 1999-07-08 Jesper Skov <jskov@cygnus.co.uk> * tests/ser_test_protocol.inl (change_config): Changed implementation.
--- a/packages/io/serial/current/src/PKGconf.mak +++ b/packages/io/serial/current/src/PKGconf.mak @@ -40,7 +40,7 @@ endif ifdef CYG_HAL_ARM_AEB EXTRAS_COMPILE += arm/aeb_serial.c endif -ifdef CYG_HAL_MN10300_STDEVAL1 +ifdef CYG_HAL_MN10300_AM31 EXTRAS_COMPILE += mn10300/mn10300_serial.c endif ifdef CYG_HAL_MIPS_TX39
--- a/packages/io/serial/current/src/mn10300/mn10300_serial.c +++ b/packages/io/serial/current/src/mn10300/mn10300_serial.c @@ -110,7 +110,12 @@ static void mn10300_serial_tx_DSR( #define LCR_WL8 0x80 // 8 bit chars #define LCR_RXE 0x4000 // receive enable #define LCR_TXE 0x8000 // transmit enable -#define LCR_TWE 0x0100 // interrupt enable (only on serial2) + +#if defined(CYG_HAL_MN10300_AM31) +#define LCR_TWE 0x0100 // interrupt enable (only on serial2/AM31) +#else +#define LCR_TWE 0x0000 // Bit does not exist in other variants +#endif //------------------------------------------------------------------------- // MN10300 timer registers: @@ -121,9 +126,49 @@ static void mn10300_serial_tx_DSR( #define TIMER_BR 0x10 //------------------------------------------------------------------------- -// IO Port: +// Serial and timer base registers: + +#if defined(CYG_HAL_MN10300_AM31) + +#define SERIAL0_BASE 0x34000800 +#define SERIAL1_BASE 0x34000810 +#define SERIAL2_BASE 0x34000820 + +#define TIMER0_BASE 0x34001000 +#define TIMER1_BASE 0x34001001 +#define TIMER2_BASE 0x34001002 + +#define SERIAL0_TIMER_SELECT 0x0004 // timer 0 +#define SERIAL1_TIMER_SELECT 0x0004 // timer 1 +#define SERIAL2_TIMER_SELECT 0x0001 // timer 2 + +#ifdef CYG_HAL_MN10300_AM31_STDEVAL1 +// The use of PORT3 to provide CTS/CTR is specific to +// the STDEVAL1 board only. +#define PORT3_MD 0x36008025 +#endif -#define PORT3_MD 0x36008025 +#define ENABLE_TRANSMIT_INTERRUPT(mn10300_chan) \ +CYG_MACRO_START \ + if( mn10300_chan->is_serial2 ) \ + cr |= LCR_TWE; \ + else \ + cr |= LCR_TXE; \ +CYG_MACRO_END + +#define DISABLE_TRANSMIT_INTERRUPT(mn10300_chan) \ +CYG_MACRO_START \ + if( mn10300_chan->is_serial2 ) \ + cr &= ~LCR_TWE; \ + else \ + cr &= ~LCR_TXE; \ +CYG_MACRO_END + +#else + +#error Unsupported MN10300 variant + +#endif //------------------------------------------------------------------------- // Tables to map input values to hardware settings @@ -150,6 +195,8 @@ static unsigned char select_parity[] = { LCR_PS, // Space parity }; +#if defined(CYG_HAL_MN10300_AM31) + static unsigned short select_baud_01[] = { 0, // Unused 0, // 50 @@ -208,6 +255,11 @@ static struct { 62, 0 }, // 230400 }; +#else + +#error Unsupported MN10300 variant + +#endif //------------------------------------------------------------------------- // Info for each serial device controlled @@ -215,6 +267,7 @@ static struct typedef struct mn10300_serial_info { CYG_ADDRWORD base; CYG_ADDRWORD timer_base; + CYG_WORD timer_select; CYG_WORD rx_int; CYG_WORD tx_int; cyg_bool is_serial2; @@ -241,8 +294,9 @@ static SERIAL_FUNS(mn10300_serial_funs, #ifndef CYG_HAL_MN10300_STDEVAL1 #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL0 static mn10300_serial_info mn10300_serial_info0 = { - 0x34000800, - 0x34001000, + SERIAL0_BASE, + TIMER0_BASE, + SERIAL0_TIMER_SELECT, CYGNUM_HAL_INTERRUPT_SERIAL_0_RX, CYGNUM_HAL_INTERRUPT_SERIAL_0_TX, false @@ -256,8 +310,9 @@ static unsigned char mn10300_serial_in_b #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL1 static mn10300_serial_info mn10300_serial_info1 = { - 0x34000810, - 0x34001001, + SERIAL1_BASE, + TIMER1_BASE, + SERIAL1_TIMER_SELECT, CYGNUM_HAL_INTERRUPT_SERIAL_1_RX, CYGNUM_HAL_INTERRUPT_SERIAL_1_TX, false @@ -270,8 +325,9 @@ static unsigned char mn10300_serial_in_b #ifdef CYGPKG_IO_SERIAL_MN10300_SERIAL2 static mn10300_serial_info mn10300_serial_info2 = { - 0x34000820, - 0x34001002, + SERIAL2_BASE, + TIMER2_BASE, + SERIAL2_TIMER_SELECT, CYGNUM_HAL_INTERRUPT_SERIAL_2_RX, CYGNUM_HAL_INTERRUPT_SERIAL_2_TX, true @@ -450,8 +506,8 @@ mn10300_serial_config_port(serial_channe mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; cyg_uint16 cr = 0; cyg_uint16 sr; - - // wait for the device to become acquiescent. This could take some time + + // wait for the device to become quiescent. This could take some time // if the device had been transmitting at a low baud rate. do { sr = mn10300_read_sr(mn10300_chan); @@ -470,7 +526,7 @@ mn10300_serial_config_port(serial_channe // baud rate is controlled. cyg_uint8 baud_divisor = select_baud_2[new_config->baud].timer2_val; - + if (baud_divisor == 0) return false; // Invalid baud rate selected @@ -482,23 +538,27 @@ mn10300_serial_config_port(serial_channe HAL_WRITE_UINT8(mn10300_chan->base+SERIAL_TIM, baud_divisor); - cr |= 0x0001; // Source clock from timer 2 + cr |= mn10300_chan->timer_select; } else { - cyg_uint8 baud_divisor = select_baud_01[new_config->baud]; - + cyg_uint16 baud_divisor = select_baud_01[new_config->baud]; + cyg_uint8 timer_mode = 0x80; + if (baud_divisor == 0) return false; // Invalid baud rate selected + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_BR, baud_divisor); - HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_MD, 0x80 ); + HAL_WRITE_UINT8(mn10300_chan->timer_base+TIMER_MD, timer_mode ); - cr |= 0x0004; // Source clock from timer 0 or 1 + cr |= mn10300_chan->timer_select; } +#ifdef PORT3_MD HAL_WRITE_UINT8( PORT3_MD, 0x01 ); +#endif // set up other config values: @@ -506,23 +566,21 @@ mn10300_serial_config_port(serial_channe cr |= select_stop_bits[new_config->stop]; cr |= select_parity[new_config->parity]; -#ifdef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE - // enable RX and TX - cr |= LCR_RXE | LCR_TXE; -#else - if( mn10300_chan->is_serial2 ) { - cr |= LCR_RXE | LCR_TXE; // enable Rx and TX - cr &= ~LCR_TWE; // disable transmit interrupts - } else { - // Enable RX only - cr |= LCR_RXE; + cr |= LCR_RXE | LCR_TXE; // enable Rx and Tx + +#ifdef CYG_HAL_MN10300_AM31 + if( mn10300_chan->is_serial2 ) + { + // AM31 has an extra TX interrupt enable bit for serial 2. + DISABLE_TRANSMIT_INTERRUPT(mn10300_chan); } -#endif - +#endif + // Write CR into hardware HAL_WRITE_UINT16(mn10300_chan->base+SERIAL_CTR, cr); - mn10300_read_sr(mn10300_chan); + sr = mn10300_read_sr(mn10300_chan); + if (new_config != &chan->config) { chan->config = *new_config; } @@ -644,10 +702,7 @@ mn10300_serial_start_xmit(serial_channel HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); - if( mn10300_chan->is_serial2 ) - cr |= LCR_TWE; // enable transmit interrupts - else - cr |= LCR_TXE; // enable TX + ENABLE_TRANSMIT_INTERRUPT(mn10300_chan); HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); @@ -678,11 +733,8 @@ mn10300_serial_stop_xmit(serial_channel HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); - if( mn10300_chan->is_serial2 ) - cr &= ~LCR_TWE; // disable transmit interrupts - else - cr &= ~LCR_TXE; // disable transmission - + DISABLE_TRANSMIT_INTERRUPT(mn10300_chan); + HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); cyg_drv_interrupt_mask(mn10300_chan->tx_int); @@ -700,7 +752,7 @@ mn10300_serial_rx_ISR(cyg_vector_t vecto { serial_channel *chan = (serial_channel *)data; mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; - + cyg_drv_interrupt_mask(mn10300_chan->rx_int); cyg_drv_interrupt_acknowledge(mn10300_chan->rx_int);
--- a/packages/io/serial/current/tests/ser_test_protocol.inl +++ b/packages/io/serial/current/tests/ser_test_protocol.inl @@ -98,7 +98,7 @@ # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV # endif #endif -#if defined(CYGPKG_HAL_MN10300_STDEVAL1) \ +#if defined(CYGPKG_HAL_MN10300_AM31_STDEVAL1) \ && defined(CYGPKG_IO_SERIAL_MN10300) \ && defined(CYGPKG_IO_SERIAL_MN10300_SERIAL2) # define TEST_SER_DEV CYGDAT_IO_SERIAL_MN10300_SERIAL2_NAME @@ -218,8 +218,11 @@ cyg_ser_cfg_t test_configs[] = { CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, #endif +#if !defined(CYGPKG_HAL_MN10300_AM31) && \ + 1 { CYGNUM_SERIAL_BAUD_14400, CYGNUM_SERIAL_WORD_LENGTH_8, CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, +#endif { CYGNUM_SERIAL_BAUD_19200, CYGNUM_SERIAL_WORD_LENGTH_8, CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, @@ -232,7 +235,8 @@ cyg_ser_cfg_t test_configs[] = { #if !defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && \ !defined(CYGPKG_HAL_ARM_AEB) && \ - !defined(CYGPKG_HAL_SPARCLITE_SLEB) + !defined(CYGPKG_HAL_SPARCLITE_SLEB) && \ + 1 { CYGNUM_SERIAL_BAUD_57600, CYGNUM_SERIAL_WORD_LENGTH_8, CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }, #endif @@ -466,7 +470,8 @@ change_config(cyg_io_handle_t handle, cy &old_cfg, &len); res = cyg_io_get_config(handle, CYG_IO_GET_CONFIG_SERIAL_INFO, &new_cfg, &len); - if (res != ENOERR) { + + if (res != ENOERR) { diag_printf("Can't get serial config - DEVIO error: %d\n", res); hang(); } @@ -561,7 +566,6 @@ change_config(cyg_io_handle_t handle, cy // was due to a framing or parity error. break; } - if ('R' == in_buf[0]) { // Resync - host didn't see our message. Try again. saw_host_sync = 0;
--- a/packages/io/serial/current/tests/serial5.c +++ b/packages/io/serial/current/tests/serial5.c @@ -70,15 +70,18 @@ serial_test( void ) // We need the filter for this test. test_ping(ser_handle); -#if defined(CYGPKG_HAL_ARM_AEB) + +#if defined(CYGPKG_HAL_MN10300) \ + || defined(CYGPKG_HAL_ARM_AEB) \ + || 0 { - // The AEB board is too slow to run the driver in interrupt mode + // Some boards are too slow to run the driver in interrupt mode // at the default 38400 baud when doing this test. - cyg_ser_cfg_t arm_aeb_cfg = { + cyg_ser_cfg_t cfg = { CYGNUM_SERIAL_BAUD_9600, CYGNUM_SERIAL_WORD_LENGTH_8, CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE }; - change_config(ser_handle, &arm_aeb_cfg); + change_config(ser_handle, &cfg); } #endif
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,12 @@ +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/sload/sload.c: Rename AM32 to AM31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/debug/dbg_gdb.cxx (dbg_make_threadref): Extended test for + uninitialized thread pointer. + 1999-07-29 Jesper Skov <jskov@cygnus.co.uk> * src/sync/mutex.cxx (lock): Removed assertion again. Not possible
--- a/packages/kernel/current/src/debug/dbg_gdb.cxx +++ b/packages/kernel/current/src/debug/dbg_gdb.cxx @@ -99,7 +99,12 @@ externC int dbg_thread_capabilities(stru static void dbg_make_threadref(Cyg_Thread *thread, threadref *ref ) { - if( thread == NULL ) + // The following test tries to avoid accessing uninitialized pointers. + // This can happen if we take a breakpoint before the data is copied + // or the BSS zeroed. We currently assume that RAM will reset to zero + // or 0xff. If it is random, we have no hope. + + if( (CYG_ADDRWORD)thread == 0 || (CYG_ADDRWORD)thread == 0xffffffff ) { ((unsigned long *)ref)[0] = 0; ((unsigned long *)ref)[1] = 0;
--- a/packages/packages +++ b/packages/packages @@ -182,7 +182,14 @@ package CYGPKG_HAL_MN10300 { hardware } -package CYGPKG_HAL_MN10300_STDEVAL1 { +package CYGPKG_HAL_MN10300_AM31 { + alias { "MN10300 AM31 variant HAL" hal_mn10300_am31 mn10300_am31_hal } + directory hal/mn10300/am31 + include_dir cyg/hal + hardware +} + +package CYGPKG_HAL_MN10300_AM31_STDEVAL1 { alias { "MN10300 stdeval1 support" hal_mn10300_stdeval1 mn10300_stdeval1_hal } directory hal/mn10300/stdeval1 include_dir cyg/hal @@ -275,6 +282,8 @@ package CYGPKG_IO_SERIAL { include_dir cyg/io } + + package CYGPKG_DEVICES_WALLCLOCK { alias { "Wallclock Device Code" wallclock devices_wallclock device_wallclock } directory devs/wallclock
--- a/packages/targets +++ b/packages/targets @@ -75,10 +75,10 @@ # argument to pkgconf. # -target mn10300 { - alias { MN10300 mn10300-elf am30 am30-elf am32 am32-elf } +target mn10300_am31 { + alias { MN10300 mn10300-elf am30 am30-elf am31 am31-elf } command_prefix mn10300-elf - packages CYGPKG_HAL_MN10300 + packages { CYGPKG_HAL_MN10300 CYGPKG_HAL_MN10300_AM31 } cflags { ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" @@ -93,9 +93,8 @@ target mn10300 { alias { "Evaluation board" } startup { ram rom } packages { - CYGPKG_HAL_MN10300_STDEVAL1 + CYGPKG_HAL_MN10300_AM31_STDEVAL1 } - } platform sim { alias { "Simulator" } @@ -107,6 +106,7 @@ target mn10300 { } + target mips_tx39 { alias { TX39 mips-tx39 mips-tx39-elf } command_prefix mips-tx39-elf