Mercurial > flash_v2
changeset 799:667f124c4406
Updates from Paul Fine <pfine@delcomsys.com>
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--- a/packages/devs/eth/powerpc/quicc2/current/ChangeLog +++ b/packages/devs/eth/powerpc/quicc2/current/ChangeLog @@ -1,3 +1,11 @@ +2003-03-04 Paul Fine <pfine@delcomsys.com> + + * src/EnetPHY.c : Added PHY reset function for the ts6 platform. + Changed delay to use HAL_DELAY_US instead of a nop for loop. + * src/if_fec.c : Invoke PHY reset function for ts6 platform, as + well as VADS platform. Remove unneeded and incorrect invocation + data cache macros. + 2002-12-12 Gary Thomas <gthomas@ecoscentric.com> 2002-12-12 Patrick Doyle <wpd@delcomsys.com>
--- a/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.c +++ b/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.c @@ -41,6 +41,7 @@ * Modified for the mpc8260 VADS board *--------------------------------------------------------------------*/ #include "types.h" +#include <cyg/hal/hal_intr.h> /* HAL_DELAY_US */ #include "EnetPHY.h" /* Internal functions */ @@ -69,11 +70,34 @@ VUINT32 * pPortData; void EnableResetPHY(volatile t_BCSR *pBCSR) { +#ifdef CYGPKG_HAL_POWERPC_TS6 +#define ETH_RST_MASK 0x20 + /* The FPGA control register on the TS6 board uses the same memory + * location as the BCSR register on the VADS board. + */ + volatile cyg_uint32 *fpga_ctrl = (cyg_uint32 *) pBCSR; + volatile cyg_uint32 *fpga_vers; + cyg_uint32 value; + fpga_vers = fpga_ctrl + 1; + value = *fpga_vers; + if(value >= 6){ /* version 06 of the FPGA added PHY reset control */ + value = *fpga_ctrl; + /* Set the PHY reset bit */ + value |= ETH_RST_MASK; + *fpga_vers = value; + + /* Give the PHY time to reset */ + HAL_DELAY_US(10000); + + /* Clear the reset bit */ + *fpga_vers = value & ~ETH_RST_MASK; + } +#else // active low FETHIEN on BSCR1, assert reset low pBCSR->bcsr1 &= ~(FETHIEN_ | FETHRST_); // de-assert reset pBCSR->bcsr1 |= FETHRST_; - +#endif } @@ -173,18 +197,12 @@ EthernetPHYInterruptHandler() UINT16 LinkTestPHY() { - UINT32 j, cnt; - UINT16 FrameValue; - - //for (j = 0; j < 10; j++) { - for (j = 0; j < 5; j++) { + UINT32 j; + UINT16 FrameValue = 0; - for (cnt = 0; cnt < 1000000; cnt ++) { - - asm("nop"); - asm("nop"); - asm("nop"); - } + for (j = 0; j < 50; j++) { + + HAL_DELAY_US(100000); FrameValue = MdioFrame(READ,0,CHIP_STAT_REG,0);
--- a/packages/devs/eth/powerpc/quicc2/current/src/if_fec.c +++ b/packages/devs/eth/powerpc/quicc2/current/src/if_fec.c @@ -184,24 +184,16 @@ fec_eth_init(struct cyg_netdevtab_entry volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET); volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e); -#ifdef CYGPKG_HAL_POWERPC_VADS +#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6) volatile t_BCSR *CSR = (t_BCSR *) 0x04500000; #endif - int cache_state; int i; bool esa_ok; bool fec_100; unsigned char *c_ptr; UINT16 link_speed; - // Ensure consistent state between cache and what the FEC sees - HAL_DCACHE_IS_ENABLED(cache_state); - if (cache_state) { - HAL_DCACHE_DISABLE(); - HAL_DCACHE_INVALIDATE_ALL(); - } - // Link the memory to the driver control memory qi->fcc_reg = & (IMM->fcc_regs[FCC2]); @@ -209,7 +201,7 @@ fec_eth_init(struct cyg_netdevtab_entry qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); // Via BCSR, (re)start LXT970 -#ifdef CYGPKG_HAL_POWERPC_VADS +#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6) EnableResetPHY(CSR); #endif @@ -409,9 +401,6 @@ fec_eth_init(struct cyg_netdevtab_entry while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); - if (cache_state) - HAL_DCACHE_ENABLE(); - // Initialize upper level driver for ecos (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
--- a/packages/hal/powerpc/mpc8260/current/ChangeLog +++ b/packages/hal/powerpc/mpc8260/current/ChangeLog @@ -1,3 +1,9 @@ +2003-03-04 Paul Fine <pfine@delcomsys.com> + + * include/var_cache.h: Modify the HAL_DCACHE_SYNC macro to look + like the MACRO defined in the PPC60x HAL. + + 2002-12-12 Gary Thomas <gthomas@ecoscentric.com> 2002-12-12 Patrick Doyle <wpd@delcomsys.com>
--- a/packages/hal/powerpc/mpc8260/current/include/var_cache.h +++ b/packages/hal/powerpc/mpc8260/current/include/var_cache.h @@ -137,35 +137,15 @@ // Synchronize the contents of the cache with memory. -// Use a brute force method until something better appears in my head -// By loading memory from 0x0 to HAL_DCACHE_SIZE, incremented by -// HAL_DCACHE_LINE_SIZE, it will ensure that the contents of the data -// cache is known. Then, I will traverse the loop again, this time -// flushing the address, not loading it. -#if 1 +// Use the macro defined in the PPC60x HAL as of January 2003. #define HAL_DCACHE_SYNC() \ CYG_MACRO_START \ - volatile cyg_uint32 tmp1,tmp2; \ - for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \ - tmp2 = *((cyg_uint32 *) tmp1); \ - HAL_DCACHE_FLUSH(0x0, HAL_DCACHE_SIZE); \ + cyg_int32 i; \ + cyg_uint32 *__base = (cyg_uint32 *) (0); \ + for(i=0;i< (HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \ + asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \ + } \ CYG_MACRO_END -#else -#define HAL_DCACHE_SYNC() \ - CYG_MACRO_START \ - cyg_uint32 __base = 0x0, _tmp; \ - cyg_int32 __size = HAL_DCACHE_SIZE; \ - while (__size > 0) { \ - asm volatile ( \ - "lwz %0,0(%1);" \ - :"=r" (_tmp) : "r" (__base) \ - ); \ - __base += HAL_DCACHE_LINE_SIZE; \ - __size -= HAL_DCACHE_LINE_SIZE; \ - } \ - HAL_DCACHE_FLUSH( 0x0 , HAL_DCACHE_SIZE ); \ - CYG_MACRO_END -#endif // Query the state of the data cache #define HAL_DCACHE_IS_ENABLED(_state_) \ @@ -307,10 +287,13 @@ asm volatile ("sync;" \ "mfspr %0, %2;" \ "ori %1, %0, 0x8000;" \ - "isync;" \ "mtspr %2, %1;" \ - "ori %1, %0, 0x0800;" \ + "isync;" \ + "sync;" \ + "ori %1, %1, 0x0800;" \ "mtspr %2, %1;" \ + "isync;" \ + "sync;" \ "mtspr %2, %0;" \ "isync;" \ "sync;" \
--- a/packages/hal/powerpc/ts6/current/ChangeLog +++ b/packages/hal/powerpc/ts6/current/ChangeLog @@ -1,3 +1,18 @@ +2003-03-04 Paul Fine <pfine@delcomsys.com> + + * cdl/hal_powerpc_ts6.cdl: Now that the cache control macros + are correct and quicc2 ethernet driver has been fixed with respect + to caching operations, allow the cache to be enabled at startup. + * src/ts6.S: Make SDRAM test global, so that RedBoot (for ROM) + can invoke the test. + * src/hal_aux.c : Add RedBoot command to test SDRAM. Also modify + the initialization of the Serial Periphial Interface (SPI) + controller in the CPM. Also removed some debug code. + * redboot_RAM.ecm: + * redboot_ROM.ecm: + * redboot_ROMRAM.ecm: Bumped DCS version to 1.17, added + REDBOOT_BACKUP option. + 2002-12-12 Gary Thomas <gthomas@ecoscentric.com> 2002-12-12 Patrick Doyle <wpd@delcomsys.com>
--- a/packages/hal/powerpc/ts6/current/cdl/hal_powerpc_ts6.cdl +++ b/packages/hal/powerpc/ts6/current/cdl/hal_powerpc_ts6.cdl @@ -67,9 +67,6 @@ cdl_package CYGPKG_HAL_POWERPC_TS6 { implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT - requires { CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP == 0 } - requires { CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP == 0 } - define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8260.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts6.h>"
--- a/packages/hal/powerpc/ts6/current/misc/redboot_RAM.ecm +++ b/packages/hal/powerpc/ts6/current/misc/redboot_RAM.ecm @@ -56,7 +56,7 @@ cdl_component CYGBLD_BUILD_REDBOOT { }; cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { - user_value 1 "DCS Version 1.16" + user_value 1 "DCS Version 1.17" }; cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { @@ -71,6 +71,10 @@ cdl_option CYGNUM_REDBOOT_FLASH_RESERVED user_value 1 }; +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + cdl_option CYGBLD_ISO_STRTOK_R_HEADER { inferred_value 1 <cyg/libc/string/string.h> };
--- a/packages/hal/powerpc/ts6/current/misc/redboot_ROM.ecm +++ b/packages/hal/powerpc/ts6/current/misc/redboot_ROM.ecm @@ -60,7 +60,7 @@ cdl_component CYGBLD_BUILD_REDBOOT { }; cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { - user_value 1 "DCS Version 1.16" + user_value 1 "DCS Version 1.17" }; cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { @@ -75,6 +75,10 @@ cdl_option CYGNUM_REDBOOT_FLASH_RESERVED user_value 0x40000 }; +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + cdl_option CYGBLD_ISO_STRTOK_R_HEADER { inferred_value 1 <cyg/libc/string/string.h> };
--- a/packages/hal/powerpc/ts6/current/misc/redboot_ROMRAM.ecm +++ b/packages/hal/powerpc/ts6/current/misc/redboot_ROMRAM.ecm @@ -78,6 +78,10 @@ cdl_option CYGNUM_REDBOOT_FLASH_RESERVED user_value 1 }; +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP { + user_value 1 +}; + cdl_option CYGBLD_ISO_STRTOK_R_HEADER { inferred_value 1 <cyg/libc/string/string.h> };
--- a/packages/hal/powerpc/ts6/current/src/hal_aux.c +++ b/packages/hal/powerpc/ts6/current/src/hal_aux.c @@ -64,6 +64,36 @@ #include <cyg/hal/hal_intr.h> #include <cyg/hal/mpc8260.h> // Needed for IMMR structure +#ifdef CYG_HAL_STARTUP_ROM +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#include <redboot.h> +// Exported CLI function +RedBoot_cmd("sdram_test", + "test the sdram", + "", + do_sdram_test + ); + +void +do_sdram_test(int argc, char *argv[]) +{ + unsigned long oldints; + + diag_printf("Starting test for SDRAM.\n"); + diag_printf("D18 will indicate PASS/FAIL (Green/Red).\n"); + diag_printf("Resetting board will be necessary after test completion.\n"); + HAL_DISABLE_INTERRUPTS(oldints); + memory_test(); +} +#endif +#endif +// For Baud Rate Calculation, see MPC8260 PowerQUICC II User's Manual +// 16.3 UART Baud Rate Examples, page 16-5. +#define UART_BIT_RATE(n) \ + (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64)) +#define UART_BAUD_RATE CYGNUM_HAL_TS6_DIAG_BAUD + // The memory map is weakly defined, allowing the application to redefine // it if necessary. The regions defined below are the minimum requirements. CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = { @@ -87,12 +117,6 @@ CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK volatile t_PQ2IMM *IMM; /* IMM base pointer */ -// Define some space in high SDRAM that I can use for debugging -#define nPFDEBUG -#ifdef PFDEBUG -cyg_uint32 *dbg_values = (cyg_uint32 *) 0x00FFFF00; -#endif - //-------------------------------------------------------------------------- // Platform init code. void @@ -159,17 +183,20 @@ hal_platform_init(void) IMM->io_regs[PORT_D].podr |= 0x00000800; IMM->io_regs[PORT_D].pdat |= 0x09800000; +#ifdef USE_CPM_SPI_CONTROLLER // Dedicated Pin assignments for SPI IMM->io_regs[PORT_D].ppar |= 0x0000F000; IMM->io_regs[PORT_D].podr &= 0xFFFF0FFF; IMM->io_regs[PORT_D].pdir |= 0x0000F000; - +#else + // The ts6 board does not use the SPI controller provided by the CPM, + // instead it is left up to the application to control the SPI. + // Therefore, initialize the SPI specific pins as General Purpose I/O + // and Bi-directional. + IMM->io_regs[PORT_D].ppar &= 0xFFFF0FFF; /* General Purpose I/O */ + IMM->io_regs[PORT_D].pdir &= 0xFFFF0FFF; /* input or Bi-directional */ +#endif -#ifdef PFDEBUG - int i; - for(i = 0; i < 20;i++) - dbg_values[i] = 0; -#endif #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT hal_if_init(); #endif
--- a/packages/hal/powerpc/ts6/current/src/ts6.S +++ b/packages/hal/powerpc/ts6/current/src/ts6.S @@ -1476,6 +1476,7 @@ count_done: # # Use two loops, the outer loop goes from 0 to 0x3ff and counts # by 1. The inner loop goes from 0 to 0xfffc and counts by 4. + .globl memory_test memory_test: #Turn on Green Led @@ -1527,6 +1528,14 @@ memwrite_loop2: add r6,r3,r5 stwx r6,r5,r3 # Store the value at r6 in the memory addressed # by the sum of r3 and r5 + nop + nop + nop +# lwzx r10,r5,r3 # Read the value into r10 from the memory addressed + # by the sum of r3 and r5 +# cmpw r6,r10 # compare values to confirm write +# bne mem_error + cmpi 0,0,r5,0 bne memwrite_loop2 # branch if r5 != 0 @@ -1557,10 +1566,10 @@ memread_loop1: memread_loop2: addi r5,r5,-4 # subtract 1 from r5 - add r6,r3,r5 - lwzx r10,r5,r3 # Read the value into r10 from the memory addressed + add r16,r3,r5 + lwzx r20,r5,r3 # Read the value into r20 from the memory addressed # by the sum of r3 and r5 - cmpw r6,r10 # compare values + cmpw r16,r20 # compare values bne mem_error cmpi 0,0,r5,0
--- a/packages/hal/powerpc/vads/current/ChangeLog +++ b/packages/hal/powerpc/vads/current/ChangeLog @@ -1,3 +1,10 @@ +2003-03-04 Paul Fine <pfine@delcomsys.com> + + * cdl/hal_powerpc_vads.cdl: Now that the cache control macros + are correct and quicc2 ethernet driver has been fixed with respect + to caching operations, allow the cache, and MMU, to be enabled at + startup. + 2002-12-12 Gary Thomas <gthomas@ecoscentric.com> 2002-12-12 Patrick Doyle <wpd@delcomsys.com>
--- a/packages/hal/powerpc/vads/current/cdl/hal_powerpc_vads.cdl +++ b/packages/hal/powerpc/vads/current/cdl/hal_powerpc_vads.cdl @@ -124,7 +124,7 @@ cdl_package CYGPKG_HAL_POWERPC_VADS { cdl_option CYGHWR_HAL_POWERPC_DISABLE_MMU { display "DISABLE MMU" flavor bool - default_value 1 + default_value 0 # calculated 1 description " This option will disable the MMU enabled."