Mercurial > flash_v2
changeset 1152:74ebd002d7bd
New package for the Samsung ARM9/SMDK2410 development
board.
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new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/ChangeLog @@ -0,0 +1,24 @@ +2003-08-06 Michael Anburaj <embeddedeng@hotmail.com> + + * cdl/hal_arm_arm9_smdk2410.cdl: + * include/hal_diag.h: + * include/hal_platform_ints.h: + * include/hal_platform_setup.h: + * include/memcfg.h: + * include/pkgconf/mlt_arm_arm9_smdk2410_ram.h: + * include/pkgconf/mlt_arm_arm9_smdk2410_ram.ldi: + * include/pkgconf/mlt_arm_arm9_smdk2410_rom.h: + * include/pkgconf/mlt_arm_arm9_smdk2410_rom.ldi: + * include/pkgconf/mlt_arm_arm9_smdk2410_romram.h: + * include/pkgconf/mlt_arm_arm9_smdk2410_romram.ldi: + * include/plf_io.h: + * include/plf_stub.h: + * include/s3c2410x.h: + * misc/smdk2410_redboot_RAM.ecm: + * misc/smdk2410_redboot_ROMRAM.ecm: + * src/hal_diag.c: + * src/smdk2410_misc.c: + New package for the Samsung ARM9/SMDK2410 development + board. + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/cdl/hal_arm_arm9_smdk2410.cdl @@ -0,0 +1,422 @@ +# ==================================================================== +# +# hal_arm_arm9_smdk2410.cdl +# +# Samsung ARM9/SMDK2410 evaluation board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): michael anburaj <michaelanburaj@hotmail.com> +# Contributors: michael anburaj <michaelanburaj@hotmail.com> +# Date: 2003-08-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_ARM9_SMDK2410 { + display "Samsung ARM9/SMDK2410 development board" + parent CYGPKG_HAL_ARM_ARM9 + requires CYGPKG_HAL_ARM_ARM9_ARM920T + hardware + include_dir cyg/hal + define_header hal_arm_arm9_smdk2410.h + description " + The SMDK2410 HAL package provides the support needed to run eCos on Samsung + S3C2410X (ARM920T) based boards." + + compile smdk2410_misc.c hal_diag.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_arm9.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_arm9_smdk2410.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM9\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"SMDK2410 system\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 106" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values { "RAM" "ROM" "ROMRAM" } + default_value { "RAM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the SMDK2410 evaluation board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using eCos GDB stubs. + Select 'rom' when building a stand-alone application which will be + put into ROM, or for the special case of building the eCos GDB stubs + themselves." + } + + # Both PLLs are in bypass mode on startup. + # FIXME: Add proper configury + cdl_option CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK { + display "CPU speed" + flavor data + legal_values 176000000 180000000 184000000 192000000 200000000 + default_value { 184000000 } + description " + This is the actual CPU operating frequency (FCLK)." + } + + cdl_option CYGNUM_HAL_ARM_SMDK2410_BUS_CLOCK { + display "ARM920T bus speed" + flavor data + calculated { CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK / 2 } + description " + This is the ARM920T AHB bus operating frequency (HCLK)." + } + + cdl_option CYGNUM_HAL_ARM_SMDK2410_PERIPHERAL_CLOCK { + display "Peripheral bus speed" + flavor data + calculated { CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK / 4 } + description " + This is the peripheral (APB) bus operating frequency (PCLK)." + } + + cdl_option CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE { + display "Timer prescale" + flavor data + legal_values 0 to 255 + default_value 16 + description " + This is the prescale value used on the clock used to drive + the kernel counter. Note that some parts of the code may fail + if this is changed due to over/underflows of expressions." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated ((CYGNUM_HAL_ARM_SMDK2410_PERIPHERAL_CLOCK/CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE/2)/CYGNUM_HAL_RTC_DENOMINATOR) + description " + Assuming 1/2 post prescale divider." + } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The SMDK2410 boards have two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The SMDK2410 boards have two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "--no-target-default-spec -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + + cdl_component CYGPKG_HAL_ARM_ARM9_SMDK2410_OPTIONS { + display "ARM9/SMDK2410 build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_ARM9_SMDK2410_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the ARM9 SMDK2410 HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_ARM9_SMDK2410_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the ARM9 SMDK2410 HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGPKG_HAL_ARM_ARM9_SMDK2410_TESTS { + display "ARM9/SMDK2410 tests" + flavor data + no_define + calculated { "" } + description " + This option specifies the set of tests for the ARM9/SMDK2410 HAL." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_arm9_smdk2410_ram" : \ + CYG_HAL_STARTUP == "ROM" ? "arm_arm9_smdk2410_rom" : \ + "arm_arm9_smdk2410_romram" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated {CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_arm9_smdk2410_ram.ldi>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_arm9_smdk2410_rom.ldi>" : \ + "<pkgconf/mlt_arm_arm9_smdk2410_romram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_arm9_smdk2410_ram.h>" : \ + CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_arm9_smdk2410_rom.h>" : \ + "<pkgconf/mlt_arm_arm9_smdk2410_romram.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { (CYG_HAL_STARTUP == "ROM") || (CYG_HAL_STARTUP == "ROMRAM") } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + # The backup image is not needed, since ROMRAM is the normal + # RedBoot startup type. + requires {!CYGPKG_REDBOOT_FLASH || CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP == 0} + + # RedBoot details + requires { CYGPKG_REDBOOT_ARM_LINUX_EXEC } + requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x00008000 } + define_proc { + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" + } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/hal_diag.h @@ -0,0 +1,76 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +// Not the best place for this, but ... +extern void hal_delay_us(cyg_int32 usecs); + +#define HAL_DELAY_US(n) hal_delay_us(n); + +#endif // CYGONCE_HAL_DIAG_H +//----------------------------------------------------------------------------- +// end of hal_diag.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/hal_platform_ints.h @@ -0,0 +1,121 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: Define Interrupt support +// Description: The interrupt details for the Samsung SMDK2410 are defined here. +// Usage: +// #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/s3c2410x.h> + +// These are interrupts on the SMDK2410 + +#define CYGNUM_HAL_INTERRUPT_EINT0 0 +#define CYGNUM_HAL_INTERRUPT_EINT1 1 +#define CYGNUM_HAL_INTERRUPT_EINT2 2 +#define CYGNUM_HAL_INTERRUPT_EINT3 3 +#define CYGNUM_HAL_INTERRUPT_EINT4_7 4 +#define CYGNUM_HAL_INTERRUPT_EINT8_23 5 +#define CYGNUM_HAL_INTERRUPT_NOTUSED6 6 +#define CYGNUM_HAL_INTERRUPT_BAT_FLT 7 +#define CYGNUM_HAL_INTERRUPT_TICK 8 +#define CYGNUM_HAL_INTERRUPT_WDT 9 +#define CYGNUM_HAL_INTERRUPT_TIMER0 10 +#define CYGNUM_HAL_INTERRUPT_TIMER1 11 +#define CYGNUM_HAL_INTERRUPT_TIMER2 12 +#define CYGNUM_HAL_INTERRUPT_TIMER3 13 +#define CYGNUM_HAL_INTERRUPT_TIMER4 14 +#define CYGNUM_HAL_INTERRUPT_UART2 15 +#define CYGNUM_HAL_INTERRUPT_LCD 16 +#define CYGNUM_HAL_INTERRUPT_DMA0 17 +#define CYGNUM_HAL_INTERRUPT_DMA1 18 +#define CYGNUM_HAL_INTERRUPT_DMA2 19 +#define CYGNUM_HAL_INTERRUPT_DMA3 20 +#define CYGNUM_HAL_INTERRUPT_SDI 21 +#define CYGNUM_HAL_INTERRUPT_SPI0 22 +#define CYGNUM_HAL_INTERRUPT_UART1 23 +#define CYGNUM_HAL_INTERRUPT_NOTUSED24 24 +#define CYGNUM_HAL_INTERRUPT_USBD 25 +#define CYGNUM_HAL_INTERRUPT_USBH 26 +#define CYGNUM_HAL_INTERRUPT_IIC 27 +#define CYGNUM_HAL_INTERRUPT_UART0 28 +#define CYGNUM_HAL_INTERRUPT_SPI1 29 +#define CYGNUM_HAL_INTERRUPT_RTCC 30 +#define CYGNUM_HAL_INTERRUPT_ADC 31 + +#define CYGNUM_HAL_INTERRUPT_NONE -1 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER4 + + + +//---------------------------------------------------------------------------- +// Reset. + +// Watchdog is started with a very small delay to Reset immediatly. +#define HAL_PLATFORM_RESET() \ +do { \ + HAL_WRITE_UINT32(WTCON, 0); \ + HAL_WRITE_UINT32(WTDAT, 1); \ + HAL_WRITE_UINT32(WTCON, (1<<0)|(0<<2)|(0<<3)|(1<<5)|(0<<8)); \ +} while(0) + +// Base of flash +#define HAL_PLATFORM_RESET_ENTRY 0x00000000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/hal_platform_setup.h @@ -0,0 +1,274 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H +//============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: ARM9/SMDK2410 platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include CYGHWR_MEMORY_LAYOUT_H +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/s3c2410x.h> // Platform specific hardware definitions +#include <cyg/hal/memcfg.h> // Platform specific memory configuration + + +#if (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 176000000) +#define M_MDIV 80 // Fin=12.0MHz Fout=176.0MHz +#define M_PDIV 1 +#define M_SDIV 1 +#elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 180000000) +#define M_MDIV 82 // Fin=12.0MHz Fout=180.0MHz +#define M_PDIV 1 +#define M_SDIV 1 +#elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 184000000) +#define M_MDIV 84 // Fin=12.0MHz Fout=184.0MHz +#define M_PDIV 1 +#define M_SDIV 1 +#elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 192000000) +#define M_MDIV 88 // Fin=12.0MHz Fout=192.0MHz +#define M_PDIV 1 +#define M_SDIV 1 +#elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 200000000) +#define M_MDIV 92 // Fin=12.0MHz Fout=200.0MHz +#define M_PDIV 1 +#define M_SDIV 1 +#else +#error CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK not set to the right value +#endif + + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU +#define CYGSEM_HAL_ROM_RESET_USES_JUMP + +// We need this here - can't rely on a translation table until MMU has +// been initialized + .macro RAW_LED_MACRO x + ldr r0,=GPFDAT + ldr r1,[r0] + bic r1,r1,#(0xf<<4) + orr r1,r1,#((0xf & ~(\x))<<4) + str r1, [r0] + .endm + + + // Configure GPF[4:7] as Output & pull-up turned off + .macro RAW_LED_PORT_INIT_MACRO + ldr r0,=GPFUP + ldr r1,[r0] + orr r1,r1,#((1<<7)|(1<<6)|(1<<5)|(1<<4)) + str r1,[r0] + + RAW_LED_MACRO 0 + + ldr r0,=GPFCON + ldr r1,[r0] + orr r1,r1,#((1<<14)|(1<<12)|(1<<10)|(1<<8)) + str r1,[r0] + .endm + +// This macro represents the initial startup code for the platform + .macro _platform_setup1 +#ifndef CYG_HAL_STARTUP_RAM + ldr r0,=WTCON // watch dog disable + ldr r1,=0x0 + str r1,[r0] +#endif + RAW_LED_PORT_INIT_MACRO + +#ifndef CYG_HAL_STARTUP_RAM + ldr r0,=INTMSK + ldr r1,=0xffffffff // all interrupt disable + str r1,[r0] + + ldr r0,=INTSUBMSK + ldr r1,=0x7ff // all sub interrupt disable + str r1,[r0] + + RAW_LED_MACRO 1 + + // Disable and clear caches + mrc p15,0,r0,c1,c0,0 + bic r0,r0,#0x1000 // disable ICache + bic r0,r0,#0x000f // disable DCache, write buffer, + // MMU and alignment faults + mcr p15,0,r0,c1,c0,0 + nop + nop + mov r0,#0 + mcr p15,0,r0,c7,c6,0 // clear data cache +#if 0 + mrc p15,0,r0,c15,c1,0 // disable streaming + orr r0,r0,#0x80 + mcr p15,0,r0,c15,c1,0 +#endif + + // To reduce PLL lock time, adjust the LOCKTIME register. + ldr r0,=LOCKTIME + ldr r1,=0xffffff + str r1,[r0] + + // We must set ratios, set memctl, then change FCLK. + ldr r0,=CLKDIVN // Set ratios 1:2:4 for FCLK:HCLK:PCLK + ldr r1,=(3) + str r1,[r0] + + // MMU_SetAsyncBusMode //Must select, since we're setting HDIVN=1 +#define R1_iA (1<<31) +#define R1_nF (1<<30) + mrc p15,0,r0,c1,c0,0 + orr r0,r0,#(R1_nF|R1_iA) + mcr p15,0,r0,c1,c0,0 + + + // Set memory control registers + adr r0,1f + ldr r1,=BWSCON // BWSCON Address + add r2, r0, #52 // End address of SMRDATA +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + b 2f + +1: +// Memory configuration should be optimized for best performance +// The following parameter is not optimized. +// Memory access cycle parameter strategy +// 1) The memory settings is safe parameters even at HCLK=75Mhz. +// 2) SDRAM refresh period is for HCLK=75Mhz. + + .long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) //GCS0 + .long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) //GCS1 + .long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) //GCS2 + .long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) //GCS3 + .long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) //GCS4 + .long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) //GCS5 + .long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) //GCS6 + .long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) //GCS7 + .long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + + .long 0x32 // SCLK power saving mode, BANKSIZE 128M/128M + + .long 0x30 // MRSR6 CL=3clk + .long 0x30 // MRSR7 +// .long 0x20 // MRSR6 CL=2clk +// .long 0x20 // MRSR7 + +2: + RAW_LED_MACRO 2 + + // Configure MPLL + ldr r0,=MPLLCON + ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) // Fin=12MHz,Fout=50MHz + str r1,[r0] + +#endif /* !CYG_HAL_STARTUP_RAM */ + + // Set up a stack [for calling C code] + ldr r1,=__startup_stack + ldr r2,=SMDK2410_SDRAM_PHYS_BASE + orr sp,r1,r2 + + // Create MMU tables + RAW_LED_MACRO 3 + bl hal_mmu_init + RAW_LED_MACRO 4 + + // Enable MMU + ldr r2,=10f +#ifdef CYG_HAL_STARTUP_ROMRAM + ldr r1,=__exception_handlers + ldr r9,=0x80000000 + sub r1,r2,r1 + add r2,r9,r1 // r9 has ROM offset +#endif + ldr r1,=MMU_Control_Init|MMU_Control_M + mcr MMU_CP,0,r1,MMU_Control,c0 + mov pc,r2 /* Change address spaces */ + nop + nop + nop +10: + RAW_LED_MACRO 5 + +#ifdef CYG_HAL_STARTUP_ROMRAM + mov r0,r9 // Relocate FLASH/ROM to RAM + ldr r1,=__exception_handlers // ram base & length + ldr r2,=__rom_data_end +20: ldr r3,[r0],#4 + str r3,[r1],#4 + cmp r1,r2 + bne 20b + ldr r0,=30f + mov pc,r0 + nop + nop + nop + nop +30: +#endif + RAW_LED_MACRO 6 + .endm + +#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 +#endif + +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h +#endif // CYGONCE_HAL_PLATFORM_SETUP_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/memcfg.h @@ -0,0 +1,173 @@ +#ifndef MEMCFG_H +#define MEMCFG_H +//============================================================================= +// +// memcfg.h +// +// Samsung SMDK2410 specific memory configuration +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: ARM9/SMDK2410 platform specific memory configuration +// Description: +// Usage: #include <cyg/hal/memcfg.h> +// Only used by "hal_platform_setup.h" +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Bus width +#define BUSWIDTH 32 + +//Memory Area +//GCS6 16bit(16MB) SDRAM(0x0c000000-0x0cffffff) +//GCS7 16bit(16MB) SDRAM(0x0d000000-0x0dffffff) +// or +//GCS6 32bit(32MB) SDRAM(0x0c000000-0x0dffffff) + + +//BWSCON +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#ifndef BUSWIDTH +#error BUSWIDTH not defined +#endif +#if (BUSWIDTH == 16) +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW16) +#define B7_BWSCON (DW16) +#else //BUSWIDTH=32 +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) +#endif + +//BANK0CON + +#define B0_Tacs 0x0 //0clk +#define B0_Tcos 0x0 //0clk +#define B0_Tacc 0x7 //14clk +#define B0_Tcoh 0x0 //0clk +#define B0_Tah 0x0 //0clk +#define B0_Tacp 0x0 +#define B0_PMC 0x0 //normal + +//BANK1CON +#define B1_Tacs 0x0 //0clk +#define B1_Tcos 0x0 //0clk +#define B1_Tacc 0x7 //14clk +#define B1_Tcoh 0x0 //0clk +#define B1_Tah 0x0 //0clk +#define B1_Tacp 0x0 +#define B1_PMC 0x0 //normal + +//Bank 2 parameter +#define B2_Tacs 0x0 //0clk +#define B2_Tcos 0x0 //0clk +#define B2_Tacc 0x7 //14clk +#define B2_Tcoh 0x0 //0clk +#define B2_Tah 0x0 //0clk +#define B2_Tacp 0x0 +#define B2_PMC 0x0 //normal + +//Bank 3 parameter +#define B3_Tacs 0x0 //0clk +#define B3_Tcos 0x0 //0clk +#define B3_Tacc 0x7 //14clk +#define B3_Tcoh 0x0 //0clk +#define B3_Tah 0x0 //0clk +#define B3_Tacp 0x0 +#define B3_PMC 0x0 //normal + +//Bank 4 parameter +#define B4_Tacs 0x0 //0clk +#define B4_Tcos 0x0 //0clk +#define B4_Tacc 0x7 //14clk +#define B4_Tcoh 0x0 //0clk +#define B4_Tah 0x0 //0clk +#define B4_Tacp 0x0 +#define B4_PMC 0x0 //normal + +//Bank 5 parameter +#define B5_Tacs 0x0 //0clk +#define B5_Tcos 0x0 //0clk +#define B5_Tacc 0x7 //14clk +#define B5_Tcoh 0x0 //0clk +#define B5_Tah 0x0 //0clk +#define B5_Tacp 0x0 +#define B5_PMC 0x0 //normal + +//Bank 6 parameter +#define B6_MT 0x3 //SDRAM +//#define B6_Trcd 0x0 //2clk +#define B6_Trcd 0x1 //3clk +#define B6_SCAN 0x1 //9bit + +//Bank 7 parameter +#define B7_MT 0x3 //SDRAM +//#define B7_Trcd 0x0 //2clk +#define B7_Trcd 0x1 //3clk +#define B7_SCAN 0x1 //9bit + +//REFRESH parameter +#define REFEN 0x1 //Refresh enable +#define TREFMD 0x0 //CBR(CAS before RAS)/Auto refresh +#define Trp 0x0 //2clk +#define Trc 0x3 //7clk + +#define Tchr 0x2 //3clk +#define REFCNT 1113 //period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) + +//----------------------------------------------------------------------------- +// end of memcfg.h +#endif // MEMCFG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_ram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x40000000) +#define CYGMEM_REGION_sram_SIZE (0x1000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_ram.ldi @@ -0,0 +1,30 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x4000000 + sram : ORIGIN = 0x40000000, LENGTH = 0x1000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x40000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_rom.h @@ -0,0 +1,23 @@ +// eCos memory layout - Fri Oct 20 05:42:50 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x40000000) +#define CYGMEM_REGION_sram_SIZE (0x1000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x80000000) +#define CYGMEM_REGION_rom_SIZE (0x4000000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_rom.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 05:42:50 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x4000000 + sram : ORIGIN = 0x40000000, LENGTH = 0x1000 + rom : ORIGIN = 0x80000000, LENGTH = 0x4000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x80000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_RELOCS (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_romram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x40000000) +#define CYGMEM_REGION_sram_SIZE (0x1000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/pkgconf/mlt_arm_arm9_smdk2410_romram.ldi @@ -0,0 +1,30 @@ +// eCos memory layout - Fri Oct 20 05:43:59 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x4000000 + sram : ORIGIN = 0x40000000, LENGTH = 0x1000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x8000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/plf_io.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_ARM_ARM9_SMDK2410_PLF_IO_H +#define CYGONCE_HAL_ARM_ARM9_SMDK2410_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: Platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/s3c2410x.h> + +#define CYGARC_PHYSICAL_ADDRESS(x) (x) + +#endif // CYGONCE_HAL_ARM_ARM9_SMDK2410_PLF_IO_H +// EOF plf_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/plf_stub.h @@ -0,0 +1,84 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: Platform HAL stub support for Innovator boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/arm_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/include/s3c2410x.h @@ -0,0 +1,522 @@ +#ifndef CYGONCE_SMDK2410_H +#define CYGONCE_SMDK2410_H + +//============================================================================= +// +// s3c2410x.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: SMDK2410 platform specific support definitions +// Description: +// Usage: #include <cyg/hal/s3c2410x.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_arm_arm9_smdk2410.h> + +// Memory layout details needed by conversion macro +#define SMDK2410_SDRAM_PHYS_BASE 0x30000000 +#define SMDK2410_SDRAM_VIRT_BASE 0x00000000 + +#define SMDK2410_FLASH_PHYS_BASE 0x00000000 +#define SMDK2410_FLASH_VIRT_BASE 0x80000000 + + +// Internal clocks +#define FCLK CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK +#define HCLK CYGNUM_HAL_ARM_SMDK2410_BUS_CLOCK +#define PCLK CYGNUM_HAL_ARM_SMDK2410_PERIPHERAL_CLOCK +#define UCLK 48000000 + + +// Memory control +#define BWSCON 0x48000000 //Bus width & wait status +#define BANKCON0 0x48000004 //Boot ROM control +#define BANKCON1 0x48000008 //BANK1 control +#define BANKCON2 0x4800000c //BANK2 cControl +#define BANKCON3 0x48000010 //BANK3 control +#define BANKCON4 0x48000014 //BANK4 control +#define BANKCON5 0x48000018 //BANK5 control +#define BANKCON6 0x4800001c //BANK6 control +#define BANKCON7 0x48000020 //BANK7 control +#define REFRESH 0x48000024 //DRAM/SDRAM refresh +#define BANKSIZE 0x48000028 //Flexible Bank Size +#define MRSRB6 0x4800002c //Mode register set for SDRAM +#define MRSRB7 0x48000030 //Mode register set for SDRAM + + +// USB Host + + +// INTERRUPT +#define SRCPND 0x4a000000 //Interrupt request status +#define INTMOD 0x4a000004 //Interrupt mode control +#define INTMSK 0x4a000008 //Interrupt mask control +#define PRIORITY 0x4a00000a //IRQ priority control +#define INTPND 0x4a000010 //Interrupt request status + +// PENDING BIT +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_NOTUSED6 (0x1<<6) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_NOTUSED24 (0x1<<24) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTCC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xffffffff) + +#define INTOFFSET 0x4a000014 //Interruot request source offset +#define SUBSRCPND 0x4a000018 //Sub source pending +#define INTSUBMSK 0x4a00001c //Interrupt sub mask + +#define BIT_SUB_ALLMSK (0x7ff) +#define BIT_SUB_ADC (0x1<<10) +#define BIT_SUB_TC (0x1<<9) +#define BIT_SUB_ERR2 (0x1<<8) +#define BIT_SUB_TXD2 (0x1<<7) +#define BIT_SUB_RXD2 (0x1<<6) +#define BIT_SUB_ERR1 (0x1<<5) +#define BIT_SUB_TXD1 (0x1<<4) +#define BIT_SUB_RXD1 (0x1<<3) +#define BIT_SUB_ERR0 (0x1<<2) +#define BIT_SUB_TXD0 (0x1<<1) +#define BIT_SUB_RXD0 (0x1<<0) + + +// DMA +#define DISRC0 0x4b000000 //DMA 0 Initial source +#define DISRCC0 0x4b000004 //DMA 0 Initial source control +#define DIDST0 0x4b000008 //DMA 0 Initial Destination +#define DIDSTC0 0x4b00000c //DMA 0 Initial Destination control +#define DCON0 0x4b000010 //DMA 0 Control +#define DSTAT0 0x4b000014 //DMA 0 Status +#define DCSRC0 0x4b000018 //DMA 0 Current source +#define DCDST0 0x4b00001c //DMA 0 Current destination +#define DMASKTRIG0 0x4b000020 //DMA 0 Mask trigger + +#define DISRC1 0x4b000040 //DMA 1 Initial source +#define DISRCC1 0x4b000044 //DMA 1 Initial source control +#define DIDST1 0x4b000048 //DMA 1 Initial Destination +#define DIDSTC1 0x4b00004c //DMA 1 Initial Destination control +#define DCON1 0x4b000050 //DMA 1 Control +#define DSTAT1 0x4b000054 //DMA 1 Status +#define DCSRC1 0x4b000058 //DMA 1 Current source +#define DCDST1 0x4b00005c //DMA 1 Current destination +#define DMASKTRIG1 0x4b000060 //DMA 1 Mask trigger + +#define DISRC2 0x4b000080 //DMA 2 Initial source +#define DISRCC2 0x4b000084 //DMA 2 Initial source control +#define DIDST2 0x4b000088 //DMA 2 Initial Destination +#define DIDSTC2 0x4b00008c //DMA 2 Initial Destination control +#define DCON2 0x4b000090 //DMA 2 Control +#define DSTAT2 0x4b000094 //DMA 2 Status +#define DCSRC2 0x4b000098 //DMA 2 Current source +#define DCDST2 0x4b00009c //DMA 2 Current destination +#define DMASKTRIG2 0x4b0000a0 //DMA 2 Mask trigger + +#define DISRC3 0x4b0000c0 //DMA 3 Initial source +#define DISRCC3 0x4b0000c4 //DMA 3 Initial source control +#define DIDST3 0x4b0000c8 //DMA 3 Initial Destination +#define DIDSTC3 0x4b0000cc //DMA 3 Initial Destination control +#define DCON3 0x4b0000d0 //DMA 3 Control +#define DSTAT3 0x4b0000d4 //DMA 3 Status +#define DCSRC3 0x4b0000d8 //DMA 3 Current source +#define DCDST3 0x4b0000dc //DMA 3 Current destination +#define DMASKTRIG3 0x4b0000e0 //DMA 3 Mask trigger + + +// CLOCK & POWER MANAGEMENT +#define LOCKTIME 0x4c000000 //PLL lock time counter +#define MPLLCON 0x4c000004 //MPLL Control +#define UPLLCON 0x4c000008 //UPLL Control +#define CLKCON 0x4c00000c //Clock generator control +#define CLKSLOW 0x4c000010 //Slow clock control +#define CLKDIVN 0x4c000014 //Clock divider control + + +// LCD CONTROLLER +#define LCDCON1 0x4d000000 //LCD control 1 +#define LCDCON2 0x4d000004 //LCD control 2 +#define LCDCON3 0x4d000008 //LCD control 3 +#define LCDCON4 0x4d00000c //LCD control 4 +#define LCDCON5 0x4d000010 //LCD control 5 +#define LCDSADDR1 0x4d000014 //STN/TFT Frame buffer start address 1 +#define LCDSADDR2 0x4d000018 //STN/TFT Frame buffer start address 2 +#define LCDSADDR3 0x4d00001c //STN/TFT Virtual screen address set +#define REDLUT 0x4d000020 //STN Red lookup table +#define GREENLUT 0x4d000024 //STN Green lookup table +#define BLUELUT 0x4d000028 //STN Blue lookup table +#define DITHMODE 0x4d00004c //STN Dithering mode +#define TPAL 0x4d000050 //TFT Temporary palette +#define LCDINTPND 0x4d000054 //LCD Interrupt pending +#define LCDSRCPND 0x4d000058 //LCD Interrupt source +#define LCDINTMSK 0x4d00005c //LCD Interrupt mask +#define LPCSEL 0x4d000060 //LPC3600 Control +#define PALETTE 0x4d000400 //Palette start address + + +// NAND flash +#define NFCONF 0x4e000000 //NAND Flash configuration +#define NFCMD 0x4e000004 //NADD Flash command +#define NFADDR 0x4e000008 //NAND Flash address +#define NFDATA 0x4e00000c //NAND Flash data +#define NFSTAT 0x4e000010 //NAND Flash operation status +#define NFECC 0x4e000014 //NAND Flash ECC +#define NFECC0 0x4e000014 +#define NFECC1 0x4e000015 +#define NFECC2 0x4e000016 + + +// UART +#define ULCON0 0x50000000 //UART 0 Line control +#define UCON0 0x50000004 //UART 0 Control +#define UFCON0 0x50000008 //UART 0 FIFO control +#define UMCON0 0x5000000c //UART 0 Modem control +#define UTRSTAT0 0x50000010 //UART 0 Tx/Rx status +#define UERSTAT0 0x50000014 //UART 0 Rx error status +#define UFSTAT0 0x50000018 //UART 0 FIFO status +#define UMSTAT0 0x5000001c //UART 0 Modem status +#define UBRDIV0 0x50000028 //UART 0 Baud rate divisor + +#define ULCON1 0x50004000 //UART 1 Line control +#define UCON1 0x50004004 //UART 1 Control +#define UFCON1 0x50004008 //UART 1 FIFO control +#define UMCON1 0x5000400c //UART 1 Modem control +#define UTRSTAT1 0x50004010 //UART 1 Tx/Rx status +#define UERSTAT1 0x50004014 //UART 1 Rx error status +#define UFSTAT1 0x50004018 //UART 1 FIFO status +#define UMSTAT1 0x5000401c //UART 1 Modem status +#define UBRDIV1 0x50004028 //UART 1 Baud rate divisor + +#define ULCON2 0x50008000 //UART 2 Line control +#define UCON2 0x50008004 //UART 2 Control +#define UFCON2 0x50008008 //UART 2 FIFO control +#define UMCON2 0x5000800c //UART 2 Modem control +#define UTRSTAT2 0x50008010 //UART 2 Tx/Rx status +#define UERSTAT2 0x50008014 //UART 2 Rx error status +#define UFSTAT2 0x50008018 //UART 2 FIFO status +#define UMSTAT2 0x5000801c //UART 2 Modem status +#define UBRDIV2 0x50008028 //UART 2 Baud rate divisor + +#define UTXH0 0x50000020 //UART 0 Transmission Hold +#define URXH0 0x50000024 //UART 0 Receive buffer +#define UTXH1 0x50004020 //UART 1 Transmission Hold +#define URXH1 0x50004024 //UART 1 Receive buffer +#define UTXH2 0x50008020 //UART 2 Transmission Hold +#define URXH2 0x50008024 //UART 2 Receive buffer + +#define OFS_ULCON (ULCON0-ULCON0) //UART Line control +#define OFS_UCON (UCON0-ULCON0) //UART Control +#define OFS_UFCON (UFCON0-ULCON0) //UART FIFO control +#define OFS_UMCON (UMCON0-ULCON0) //UART Modem control +#define OFS_UTRSTAT (UTRSTAT0-ULCON0)//UART Tx/Rx status +#define OFS_UERSTAT (UERSTAT0-ULCON0)//UART Rx error status +#define OFS_UFSTAT (UFSTAT0-ULCON0) //UART FIFO status +#define OFS_UMSTAT (UMSTAT0-ULCON0) //UART Modem status +#define OFS_UBRDIV (UBRDIV0-ULCON0) //UART Baud rate divisor +#define OFS_UTXH (UTXH0-ULCON0) //UART Transmission Hold +#define OFS_URXH (URXH0-ULCON0) //UART Receive buffer + +// ULCON bits +#define SHF_ULCON_WL 0 +#define MSK_ULCON_WL (0x3<<SHF_ULCON_WL) +#define VAL_ULCON_WL_5 (0x0<<SHF_ULCON_WL) +#define VAL_ULCON_WL_6 (0x1<<SHF_ULCON_WL) +#define VAL_ULCON_WL_7 (0x2<<SHF_ULCON_WL) +#define VAL_ULCON_WL_8 (0x3<<SHF_ULCON_WL) + +#define SHF_ULCON_SB 2 +#define MSK_ULCON_SB (0x1<<SHF_ULCON_SB) +#define VAL_ULCON_SB_1 (0x0<<SHF_ULCON_SB) +#define VAL_ULCON_SB_2 (0x1<<SHF_ULCON_SB) + +#define SHF_ULCON_PM 3 +#define MSK_ULCON_PM (0x7<<SHF_ULCON_PM) +#define VAL_ULCON_PM_N (0x0<<SHF_ULCON_PM) +#define VAL_ULCON_PM_O (0x4<<SHF_ULCON_PM) +#define VAL_ULCON_PM_E (0x5<<SHF_ULCON_PM) +#define VAL_ULCON_PM_FC1 (0x6<<SHF_ULCON_PM) +#define VAL_ULCON_PM_FC0 (0x7<<SHF_ULCON_PM) + +#define SHF_ULCON_IRM 6 +#define MSK_ULCON_IRM (0x1<<SHF_ULCON_IRM) +#define VAL_ULCON_IRM_N (0x0<<SHF_ULCON_IRM) +#define VAL_ULCON_IRM_IR (0x1<<SHF_ULCON_IRM) + + +// PWM TIMER +#define TCFG0 0x51000000 //Timer 0 configuration +#define TCFG1 0x51000004 //Timer 1 configuration +#define TCON 0x51000008 //Timer control +#define TCNTB0 0x5100000c //Timer count buffer 0 +#define TCMPB0 0x51000010 //Timer compare buffer 0 +#define TCNTO0 0x51000014 //Timer count observation 0 +#define TCNTB1 0x51000018 //Timer count buffer 1 +#define TCMPB1 0x5100001c //Timer compare buffer 1 +#define TCNTO1 0x51000020 //Timer count observation 1 +#define TCNTB2 0x51000024 //Timer count buffer 2 +#define TCMPB2 0x51000028 //Timer compare buffer 2 +#define TCNTO2 0x5100002c //Timer count observation 2 +#define TCNTB3 0x51000030 //Timer count buffer 3 +#define TCMPB3 0x51000034 //Timer compare buffer 3 +#define TCNTO3 0x51000038 //Timer count observation 3 +#define TCNTB4 0x5100003c //Timer count buffer 4 +#define TCNTO4 0x51000040 //Timer count observation 4 + + +// USB DEVICE +#define FUNC_ADDR_REG 0x52000140 //Function address +#define PWR_REG 0x52000144 //Power management +#define EP_INT_REG 0x52000148 //EP Interrupt pending and clear +#define USB_INT_REG 0x52000158 //USB Interrupt pending and clear +#define EP_INT_EN_REG 0x5200015c //Interrupt enable +#define USB_INT_EN_REG 0x5200016c +#define FRAME_NUM1_REG 0x52000170 //Frame number lower byte +#define FRAME_NUM2_REG 0x52000174 //Frame number higher byte +#define INDEX_REG 0x52000178 //Register index +#define MAXP_REG 0x52000180 //Endpoint max packet +#define EP0_CSR 0x52000184 //Endpoint 0 status +#define IN_CSR1_REG 0x52000184 //In endpoint control status +#define IN_CSR2_REG 0x52000188 +#define OUT_CSR1_REG 0x52000190 //Out endpoint control status +#define OUT_CSR2_REG 0x52000194 +#define OUT_FIFO_CNT1_REG 0x52000198 //Endpoint out write count +#define OUT_FIFO_CNT2_REG 0x5200019c +#define EP0_FIFO 0x520001c0 //Endpoint 0 FIFO +#define EP1_FIFO 0x520001c4 //Endpoint 1 FIFO +#define EP2_FIFO 0x520001c8 //Endpoint 2 FIFO +#define EP3_FIFO 0x520001cc //Endpoint 3 FIFO +#define EP4_FIFO 0x520001d0 //Endpoint 4 FIFO +#define EP1_DMA_CON 0x52000200 //EP1 DMA interface control +#define EP1_DMA_UNIT 0x52000204 //EP1 DMA Tx unit counter +#define EP1_DMA_FIFO 0x52000208 //EP1 DMA Tx FIFO counter +#define EP1_DMA_TTC_L 0x5200020c //EP1 DMA total Tx counter +#define EP1_DMA_TTC_M 0x52000210 +#define EP1_DMA_TTC_H 0x52000214 +#define EP2_DMA_CON 0x52000218 //EP2 DMA interface control +#define EP2_DMA_UNIT 0x5200021c //EP2 DMA Tx unit counter +#define EP2_DMA_FIFO 0x52000220 //EP2 DMA Tx FIFO counter +#define EP2_DMA_TTC_L 0x52000224 //EP2 DMA total Tx counter +#define EP2_DMA_TTC_M 0x52000228 +#define EP2_DMA_TTC_H 0x5200022c +#define EP3_DMA_CON 0x52000240 //EP3 DMA interface control +#define EP3_DMA_UNIT 0x52000244 //EP3 DMA Tx unit counter +#define EP3_DMA_FIFO 0x52000248 //EP3 DMA Tx FIFO counter +#define EP3_DMA_TTC_L 0x5200024c //EP3 DMA total Tx counter +#define EP3_DMA_TTC_M 0x52000250 +#define EP3_DMA_TTC_H 0x52000254 +#define EP4_DMA_CON 0x52000258 //EP4 DMA interface control +#define EP4_DMA_UNIT 0x5200025c //EP4 DMA Tx unit counter +#define EP4_DMA_FIFO 0x52000260 //EP4 DMA Tx FIFO counter +#define EP4_DMA_TTC_L 0x52000264 //EP4 DMA total Tx counter +#define EP4_DMA_TTC_M 0x52000268 +#define EP4_DMA_TTC_H 0x5200026c + + +// WATCH DOG TIMER +#define WTCON 0x53000000 //Watch-dog timer mode +#define WTDAT 0x53000004 //Watch-dog timer data +#define WTCNT 0x53000008 //Eatch-dog timer count + + +// IIC +#define IICCON 0x54000000 //IIC control +#define IICSTAT 0x54000004 //IIC status +#define IICADD 0x54000008 //IIC address +#define IICDS 0x5400000c //IIC data shift + + +// IIS +#define IISCON 0x55000000 //IIS Control +#define IISMOD 0x55000004 //IIS Mode +#define IISPSR 0x55000008 //IIS Prescaler +#define IISFCON 0x5500000c //IIS FIFO control + +#define IISFIFO 0x55000010 //IIS FIFO entry + + +// I/O PORT +#define GPACON 0x56000000 //Port A control +#define GPADAT 0x56000004 //Port A data + +#define GPBCON 0x56000010 //Port B control +#define GPBDAT 0x56000014 //Port B data +#define GPBUP 0x56000018 //Pull-up control B + +#define GPCCON 0x56000020 //Port C control +#define GPCDAT 0x56000024 //Port C data +#define GPCUP 0x56000028 //Pull-up control C + +#define GPDCON 0x56000030 //Port D control +#define GPDDAT 0x56000034 //Port D data +#define GPDUP 0x56000038 //Pull-up control D + +#define GPECON 0x56000040 //Port E control +#define GPEDAT 0x56000044 //Port E data +#define GPEUP 0x56000048 //Pull-up control E + +#define GPFCON 0x56000050 //Port F control +#define GPFDAT 0x56000054 //Port F data +#define GPFUP 0x56000058 //Pull-up control F + +#define GPGCON 0x56000060 //Port G control +#define GPGDAT 0x56000064 //Port G data +#define GPGUP 0x56000068 //Pull-up control G + +#define GPHCON 0x56000070 //Port H control +#define GPHDAT 0x56000074 //Port H data +#define GPHUP 0x56000078 //Pull-up control H + +#define MISCCR 0x56000080 //Miscellaneous control +#define DCLKCON 0x56000084 //DCLK0/1 control +#define EXTINT0 0x56000088 //External interrupt control register 0 +#define EXTINT1 0x5600008c //External interrupt control register 1 +#define EXTINT2 0x56000090 //External interrupt control register 2 +#define EINTFLT0 0x56000094 //Reserved +#define EINTFLT1 0x56000098 //Reserved +#define EINTFLT2 0x5600009c //External interrupt filter control register 2 +#define EINTFLT3 0x560000a0 //External interrupt filter control register 3 +#define EINTMASK 0x560000a4 //External interrupt mask +#define EINTPEND 0x560000a8 //External interrupt pending +#define GSTATUS0 0x560000ac //External pin status +#define GSTATUS1 0x560000b0 //Chip ID(0x32410000) +#define GSTATUS2 0x560000b4 //Reset type +#define GSTATUS3 0x560000b8 //Saved data0(32-bit) before entering POWER_OFF mode +#define GSTATUS4 0x560000bc //Saved data0(32-bit) before entering POWER_OFF mode + + +// RTC +#define RTCCON 0x57000040 //RTC control +#define TICNT 0x57000044 //Tick time count +#define RTCALM 0x57000050 //RTC alarm control +#define ALMSEC 0x57000054 //Alarm second +#define ALMMIN 0x57000058 //Alarm minute +#define ALMHOUR 0x5700005c //Alarm Hour +#define ALMDAY 0x57000060 //Alarm day +#define ALMMON 0x57000064 //Alarm month +#define ALMYEAR 0x57000068 //Alarm year +#define RTCRST 0x5700006c //RTC round reset +#define BCDSEC 0x57000070 //BCD second +#define BCDMIN 0x57000074 //BCD minute +#define BCDHOUR 0x57000078 //BCD hour +#define BCDDAY 0x5700007c //BCD day +#define BCDDATE 0x57000080 //BCD date +#define BCDMON 0x57000084 //BCD month +#define BCDYEAR 0x57000088 //BCD year + + +// ADC +#define ADCCON 0x58000000 //ADC control +#define ADCTSC 0x58000004 //ADC touch screen control +#define ADCDLY 0x58000008 //ADC start or Interval Delay +#define ADCDAT0 0x5800000c //ADC conversion data 0 +#define ADCDAT1 0x58000010 //ADC conversion data 1 + + +// SPI +#define SPCON0 0x59000000 //SPI0 control +#define SPSTA0 0x59000004 //SPI0 status +#define SPPIN0 0x59000008 //SPI0 pin control +#define SPPRE0 0x5900000c //SPI0 baud rate prescaler +#define SPTDAT0 0x59000010 //SPI0 Tx data +#define SPRDAT0 0x59000014 //SPI0 Rx data + +#define SPCON1 0x59000020 //SPI1 control +#define SPSTA1 0x59000024 //SPI1 status +#define SPPIN1 0x59000028 //SPI1 pin control +#define SPPRE1 0x5900002c //SPI1 baud rate prescaler +#define SPTDAT1 0x59000030 //SPI1 Tx data +#define SPRDAT1 0x59000034 //SPI1 Rx data + + +// SD Interface +#define SDICON 0x5a000000 //SDI control +#define SDIPRE 0x5a000004 //SDI baud rate prescaler +#define SDICARG 0x5a000008 //SDI command argument +#define SDICCON 0x5a00000c //SDI command control +#define SDICSTA 0x5a000010 //SDI command status +#define SDIRSP0 0x5a000014 //SDI response 0 +#define SDIRSP1 0x5a000018 //SDI response 1 +#define SDIRSP2 0x5a00001c //SDI response 2 +#define SDIRSP3 0x5a000020 //SDI response 3 +#define SDIDTIMER 0x5a000024 //SDI data/busy timer +#define SDIBSIZE 0x5a000028 //SDI block size +#define SDIDCON 0x5a00002c //SDI data control +#define SDIDCNT 0x5a000030 //SDI data remain counter +#define SDIDSTA 0x5a000034 //SDI data status +#define SDIFSTA 0x5a000038 //SDI FIFO status +#define SDIIMSK 0x5a000040 //SDI interrupt mask + +#define SDIDAT 0x5a00003c //SDI data + + +#endif // CYGONCE_SMDK2410_H +//----------------------------------------------------------------------------- +// end of s3c2410x.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/misc/smdk2410_redboot_RAM.ecm @@ -0,0 +1,86 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware smdk2410_arm9 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_ARM9 current ; + package -hardware CYGPKG_HAL_ARM_ARM9_SMDK2410 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_SMDK2410 current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_SMDK2410 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_ARM_ARM9_ARM920T { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 { + inferred_value 1 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/misc/smdk2410_redboot_ROMRAM.ecm @@ -0,0 +1,85 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware smdk2410_arm9 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_ARM9 current ; + package -hardware CYGPKG_HAL_ARM_ARM9_SMDK2410 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_SMDK2410 current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_SMDK2410 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_ARM_ARM9_ARM920T { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 { + inferred_value 1 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/src/hal_diag.c @@ -0,0 +1,329 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // basic machine info +#include <cyg/hal/hal_intr.h> // interrupt macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/s3c2410x.h> // platform definitions + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint32 base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +static channel_data_t smdk_ser_channels[2] = { + {(cyg_uint32)ULCON0, 1000, CYGNUM_HAL_INTERRUPT_UART0}, + {(cyg_uint32)ULCON1, 1000, CYGNUM_HAL_INTERRUPT_UART1} +}; + + +#define __READ_UINT32( _register_ ) *((volatile CYG_WORD32 *)(_register_)) + + +//----------------------------------------------------------------------------- + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + + //UART FIFO control register + HAL_WRITE_UINT32(base+OFS_UFCON, (3<<6) | (3<<4) | (1<<2) | (1<<1) | (1<<0)); + + //UART modem control register + HAL_WRITE_UINT32(base+OFS_UMCON, 0); + + //UART line control register: Normal,No parity,1 stop,8 bits + HAL_WRITE_UINT32(base+OFS_ULCON, 0x3); + + //UART control register + HAL_WRITE_UINT32(base+OFS_UCON, 0x245); + + //UART baud divider register + HAL_WRITE_UINT32(base+OFS_UBRDIV, (cyg_uint32)((FCLK/4)/16./CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD+0.5) -1); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, char c) +{ + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 status; + CYGARC_HAL_SAVE_GP(); + + // Wait for Tx FIFO not full + do + { + HAL_READ_UINT32(base+OFS_UFSTAT, status); + } + while (status & 0x200) ; + + //UART TX data register + HAL_WRITE_UINT8(base+OFS_UTXH, c); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 status; + + HAL_READ_UINT32(base+OFS_UFSTAT, status); + if (status & 0x0f) + { + HAL_READ_UINT8(base+OFS_URXH, *ch); + return true; + } + + return false; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + char c; + cyg_uint32 lsr; + CYGARC_HAL_SAVE_GP(); + + cyg_drv_interrupt_acknowledge(chan->isr_vector); + + *__ctrlc = 0; + HAL_READ_UINT32(chan->base+OFS_UFSTAT, lsr); + if (lsr & 0x0f) + { + HAL_READ_UINT8(chan->base+OFS_URXH, c); + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Disable interrupts. + HAL_INTERRUPT_MASK(smdk_ser_channels[0].isr_vector); + HAL_INTERRUPT_MASK(smdk_ser_channels[1].isr_vector); + + //Unmask UART0/1 RX interrupt + HAL_WRITE_UINT32(INTSUBMSK, __READ_UINT32(INTSUBMSK) & ~(BIT_SUB_RXD0|BIT_SUB_RXD1)); + + // Init channels + cyg_hal_plf_serial_init_channel(&smdk_ser_channels[0]); + cyg_hal_plf_serial_init_channel(&smdk_ser_channels[1]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Set channel 1 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/smdk2410/current/src/smdk2410_misc.c @@ -0,0 +1,478 @@ +//========================================================================== +// +// smdk2410_misc.c +// +// HAL misc board support code for ARM9/SMDK2410 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): michael anburaj <michaelanburaj@hotmail.com> +// Contributors: michael anburaj <michaelanburaj@hotmail.com> +// Date: 2003-08-01 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/s3c2410x.h> // Platform specifics + +#include <cyg/infra/diag.h> // diag_printf + +#include <string.h> // memset + +// ------------------------------------------------------------------------- +// MMU initialization: +// +// These structures are laid down in memory to define the translation +// table. +// + +// ARM Translation Table Base Bit Masks +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +// ARM Domain Access Control Bit Masks +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + int id : 2; + int imp : 2; + int domain : 4; + int sbz : 1; + int base_address : 23; +}; +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + int id : 2; + int b : 1; + int c : 1; + int imp : 1; + int domain : 4; + int sbz0 : 1; + int ap : 2; + int sbz1 : 8; + int base_address : 12; +}; +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + CYG_MACRO_START \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.imp = 1; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + CYG_MACRO_END + +#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \ + { int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--,j++,k++) \ + { \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +void +hal_mmu_init(void) +{ + unsigned long ttb_base = SMDK2410_SDRAM_PHYS_BASE + 0x4000; + unsigned long i; + + // Set the TTB register + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + // Set the Domain Access Control Register + i = ARM_ACCESS_TYPE_MANAGER(0) | + ARM_ACCESS_TYPE_NO_ACCESS(1) | + ARM_ACCESS_TYPE_NO_ACCESS(2) | + ARM_ACCESS_TYPE_NO_ACCESS(3) | + ARM_ACCESS_TYPE_NO_ACCESS(4) | + ARM_ACCESS_TYPE_NO_ACCESS(5) | + ARM_ACCESS_TYPE_NO_ACCESS(6) | + ARM_ACCESS_TYPE_NO_ACCESS(7) | + ARM_ACCESS_TYPE_NO_ACCESS(8) | + ARM_ACCESS_TYPE_NO_ACCESS(9) | + ARM_ACCESS_TYPE_NO_ACCESS(10) | + ARM_ACCESS_TYPE_NO_ACCESS(11) | + ARM_ACCESS_TYPE_NO_ACCESS(12) | + ARM_ACCESS_TYPE_NO_ACCESS(13) | + ARM_ACCESS_TYPE_NO_ACCESS(14) | + ARM_ACCESS_TYPE_NO_ACCESS(15); + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + // First clear all TT entries - ie Set them to Faulting + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + // Memory layout after MMU is turned on + // + // SDRAM_BASE_ADDRESS: 0x00000000, 64M + // SRAM_BASE_ADDRESS: 0x40000000, 4K + // SFR_BASE_ADDRESS: 0x48000000, 512M + // FLASH_BASE_ADDRESS: 0x80000000, 2M + + // Actual Virtual Size Attributes Function + // Base Base MB cached? buffered? access permissions + // xxx00000 xxx00000 + X_ARM_MMU_SECTION(0x000, 0x800, 2, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Flash + X_ARM_MMU_SECTION(0x300, 0x000, 64, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SDRAM + X_ARM_MMU_SECTION(0x400, 0x400, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SRAM + X_ARM_MMU_SECTION(0x480, 0x480, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SFRs + X_ARM_MMU_SECTION(0x300, 0x300, 64, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Raw SDRAM +} + +//---------------------------------------------------------------------------- +// Platform specific initialization + +// This routine sets the default GPIO condition +static void port_init(void) +{ + // Note: Follow the configuration order for setting the ports. + // 1) Set data register (GPnDAT) + // 2) Set control register (GPnCON) + // 3) Configure pull-up's (GPnUP) + + //*** PORT A GROUP + //Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 + //Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 + //Binary : 1 1 1 1 1 1 1 1 1 1 1 + //----------------------------------------------------------------------------------------- + //Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 + //Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 + //Binary : 1 1 1 1 1 1 1 1 1 1 1 1 + HAL_WRITE_UINT32(GPACON, 0x7fffff); + + //**** PORT B GROUP + //Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 + //Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard + //Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT + //Binary : 00 01 00 01 00 01 01 01 01 01 01 + HAL_WRITE_UINT32(GPBCON, 0x044555); + HAL_WRITE_UINT32(GPBUP, 0x7ff); // The pull up function is disabled GPB[10:0] + + //*** PORT C GROUP + //Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 + //Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND + //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 + HAL_WRITE_UINT32(GPCCON, 0xaaaaaaaa); + HAL_WRITE_UINT32(GPCUP, 0xffff); // The pull up function is disabled GPC[15:0] + + //*** PORT D GROUP + //Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 + //Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 + //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 + HAL_WRITE_UINT32(GPDCON, 0xaaaaaaaa); + HAL_WRITE_UINT32(GPDUP, 0xffff); // The pull up function is disabled GPD[15:0] + + //*** PORT E GROUP + //Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 + //Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO + //Binary : 10 10 10 10 10 10 10 10 10 10 10 10 + //------------------------------------------------------------------------------------------------ + //Ports : GPE3 GPE2 GPE1 GPE0 + //Signal : I2SSDI CDCLK I2SSCLK I2SLRCK + //Binary : 10 10 10 10 + HAL_WRITE_UINT32(GPECON, 0xaaaaaaaa); + HAL_WRITE_UINT32(GPEUP, 0xffff); // The pull up function is disabled GPE[15:0] + + //*** PORT F GROUP + //Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 + //Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0 + //Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0 + //Binary : 01 01 01 01 10 10 10 10 + HAL_WRITE_UINT32(GPFCON, 0x55aa); + HAL_WRITE_UINT32(GPFUP, 0xff); // The pull up function is disabled GPF[7:0] + + //*** PORT G GROUP + //Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 + //Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI + //Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1 + //Binary : 11 11 11 11 10 01 01 01 11 11 + //----------------------------------------------------------------------------------------- + //Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 + //Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA + //Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8 + //Binary : 11 11 10 11 10 10 + HAL_WRITE_UINT32(GPGCON, 0xff95ffba); + HAL_WRITE_UINT32(GPGUP, 0xffff); // The pull up function is disabled GPG[15:0] + + //*** PORT H GROUP + //Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 + //Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0 + //Binary : 10 10 10 11 11 10 10 10 10 10 10 + HAL_WRITE_UINT32(GPHCON, 0x2afaaa); + HAL_WRITE_UINT32(GPHUP, 0x7ff); // The pull up function is disabled GPH[10:0] + + //External interrupts will be falling edge triggered. + HAL_WRITE_UINT32(EXTINT0, 0x22222222); // EINT[7:0] + HAL_WRITE_UINT32(EXTINT1, 0x22222222); // EINT[15:8] + HAL_WRITE_UINT32(EXTINT2, 0x22222222); // EINT[23:16] +} + +void +plf_hardware_init(void) +{ + HAL_WRITE_UINT32(INTMOD, 0x0); //All=IRQ mode + HAL_WRITE_UINT32(INTMSK, BIT_ALLMSK); //All interrupt is masked. + HAL_WRITE_UINT32(INTSUBMSK, BIT_SUB_ALLMSK); //All sub-interrupt is masked. + + port_init(); + + // Initialize real-time clock (for delays, etc, even if kernel doesn't use it) + hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD); +} + +// ------------------------------------------------------------------------- +// Use Timer4 for system clock +void +hal_clock_initialize(cyg_uint32 period) +{ + cyg_uint32 temp; + + // Configure the Prescaler1 + HAL_READ_UINT32(TCFG0, temp); + temp &= ~(0xff<<8); + temp |= (CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE<<8); + HAL_WRITE_UINT32(TCFG0, temp); + + // Configure the MUX to select the 1/2 divider + HAL_READ_UINT32(TCFG1, temp); + temp &= ~(0xf<<16); + temp |= (0x0<<16); + HAL_WRITE_UINT32(TCFG1, temp); + + // Set up the Timer4 for period + HAL_WRITE_UINT32(TCNTB4, period); + + // Start Timer4 + HAL_READ_UINT32(TCON, temp); + temp &= ~(0xf << 20); + HAL_WRITE_UINT32(TCON, (temp|(6<<20))); + HAL_WRITE_UINT32(TCON, (temp|(5<<20))); + + // Unmask Timer4 interrupt, need not be done here + //HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 ); + //HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC ); +} + +// This routine is called during a clock interrupt. +void +hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + // Do nothing +} + +// Read the current value of the clock, returning the number of hardware +// "ticks" that have occurred (i.e. how far away the current value is from +// the start) +void +hal_clock_read(cyg_uint32 *pvalue) +{ + cyg_int32 clock_val; + + // Read Timer4's current value + HAL_READ_UINT32(TCNTO4, clock_val); + + *pvalue = CYGNUM_HAL_RTC_PERIOD - (clock_val & 0xFFFF); // Note: counter is only 16 bits + // and decreases +} + + +// Delay for some number of micro-seconds +void +hal_delay_us(cyg_int32 usecs) +{ + cyg_uint32 ticks = 0; + // Divide by 1000000 in two steps to preserve precision. + cyg_uint32 wait_ticks = (((PCLK/100000)*usecs)/CYGNUM_HAL_ARM_SMDK2410_TIMER_PRESCALE/2/10); + cyg_int32 val, prev, diff; + + // Read Timer4's current value + HAL_READ_UINT32(TCNTO4, prev); + prev &= 0xFFFF; + + while (ticks < wait_ticks) { + while (true) { + // Read Timer4's current value + HAL_READ_UINT32(TCNTO4, val); + val &= 0xFFFF; + + diff = prev - val; + if (diff != 0) { + if(diff < 0) + diff += (CYGNUM_HAL_RTC_PERIOD+1); + + break; // atleast 1 tick has passed + } + } + prev = val; + ticks += diff; + } +} + +// ------------------------------------------------------------------------- + +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. +int +hal_IRQ_handler(void) +{ + cyg_uint32 ior; + + HAL_READ_UINT32(INTOFFSET, ior); + return (int)ior; +} + +//---------------------------------------------------------------------------- +// Interrupt control + +void +hal_interrupt_mask(int vector) +{ + cyg_uint32 imr; + + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_READ_UINT32(INTMSK, imr); + imr |= (1<<vector); + HAL_WRITE_UINT32(INTMSK, imr); +} + +void +hal_interrupt_unmask(int vector) +{ + cyg_uint32 imr; + + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_READ_UINT32(INTMSK, imr); + imr &= ~(1<<vector); + HAL_WRITE_UINT32(INTMSK, imr); +} + +void +hal_interrupt_acknowledge(int vector) +{ + cyg_uint32 ipr; + + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_WRITE_UINT32(SRCPND, (1<<vector)); + HAL_READ_UINT32(INTPND, ipr); + HAL_WRITE_UINT32(INTPND, ipr); +} + +void +hal_interrupt_configure(int vector, int level, int up) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); +} + +void hal_interrupt_set_level(int vector, int level) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); +} + + +//----------------------------------------------------------------------------- +// End of smdk2410_misc.c