Mercurial > flash_v2
changeset 183:9160a8005d76
Merge from eCos master repository on 2001-09-12-03:52:30-BST
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Nick Garnett <nickg@redhat.com> + + * ecos.db: + Added FLASH support for VRC437X based boards. + 2001-07-31 Bart Veer <bartv@redhat.com> * pkgconf/rules.mak:
--- a/packages/compat/posix/current/ChangeLog +++ b/packages/compat/posix/current/ChangeLog @@ -1,3 +1,20 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * include/pthread.h: Separate mutex and condvar API into separate + header file to fix configury problems. + * include/mutex.h: New file for the above. + * cdl/posix.cdl: provide the correct configury for the isoinfra + package to include the above file. + * cdl/pthread.cdl: Move _POSIX_PTHREAD_PRIO_INHERIT and + _POSIX_THREAD_PRIO_PROTECT to cdl/posix.cdl. + +2001-09-07 Jonathan Larmour <jlarmour@redhat.com> + + * src/sem.cxx (sem_trywait): Actually use the return value. + + * src/sched.cxx (sched_get_priority_max): Use MAX not MIN + (sched_get_priority_min): Use MIN not MAX. + 2001-09-06 Jesper Skov <jskov@redhat.com> * cdl/posix.cdl: Moved signal implements statements to the
--- a/packages/compat/posix/current/cdl/posix.cdl +++ b/packages/compat/posix/current/cdl/posix.cdl @@ -54,12 +54,37 @@ cdl_package CYGPKG_POSIX { implements CYGINT_ISO_SCHED_IMPL implements CYGINT_ISO_POSIX_LIMITS + implements CYGINT_ISO_PMUTEXTYPES + implements CYGINT_ISO_PTHREAD_MUTEX requires { CYGBLD_ISO_POSIX_LIMITS_HEADER == \ "<cyg/posix/limits.h>" } + requires { CYGBLD_ISO_PMUTEXTYPES_HEADER == \ + "<cyg/posix/muttypes.h>" } + requires { CYGBLD_ISO_PTHREAD_MUTEX_HEADER == \ + "<cyg/posix/mutex.h>" } compile mqueue.cxx mutex.cxx sem.cxx misc.cxx compile -library=libextras.a startup.cxx + cdl_option _POSIX_THREAD_PRIO_INHERIT { + display "POSIX mutex priority inheritance feature test macro" + flavor bool + default_value 1 + requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_INHERIT + description "This option defines the POSIX feature test macro + for supporting priority inheritance protocol in + mutexes." + } + + cdl_option _POSIX_THREAD_PRIO_PROTECT { + display "POSIX mutex priority ceiling feature test macro" + flavor bool + default_value 1 + requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_CEILING + description "This option defines the POSIX feature test macro + for supporting priority ceiling protocol in mutexes." + } + # ---------------------------------------------------------------- # Scheduling component
--- a/packages/compat/posix/current/cdl/pthread.cdl +++ b/packages/compat/posix/current/cdl/pthread.cdl @@ -60,24 +60,6 @@ cdl_option CYGPKG_POSIX_PTHREAD_REQUIREM } -cdl_option _POSIX_THREAD_PRIO_INHERIT { - display "POSIX mutex priority inheritance feature test macro" - flavor bool - default_value 1 - requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_INHERIT - description "This option defines the POSIX feature test macro - for supporting priority inheritance protocol in mutexes." -} - -cdl_option _POSIX_THREAD_PRIO_PROTECT { - display "POSIX mutex priority ceiling feature test macro" - flavor bool - default_value 1 - requires CYGSEM_KERNEL_SYNCH_MUTEX_PRIORITY_INVERSION_PROTOCOL_CEILING - description "This option defines the POSIX feature test macro - for supporting priority ceiling protocol in mutexes." -} - # ==================================================================== cdl_component CYGPKG_POSIX_PTHREAD_VALUES {
new file mode 100644 --- /dev/null +++ b/packages/compat/posix/current/include/mutex.h @@ -0,0 +1,163 @@ +#ifndef CYGONCE_POSIX_MUTEX_H +#define CYGONCE_POSIX_MUTEX_H +//============================================================================= +// +// mutex.h +// +// POSIX mutex and condition variable function definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg,jlarmour +// Contributors: +// Date: 2001-09-10 +// Purpose: POSIX mutex and condition variable function definitions +// Description: This header contains POSIX API definitions for mutexes +// and cond vars. +// +// Usage: #include <pthread.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/posix.h> + +#include <sys/types.h> // pthread_* types + +//============================================================================= +// Mutexes + +//----------------------------------------------------------------------------- +// Mutex attributes manipulation functions + +// Initialize attribute object +externC int pthread_mutexattr_init ( pthread_mutexattr_t *attr); + +// Destroy attribute object +externC int pthread_mutexattr_destroy ( pthread_mutexattr_t *attr); + +#if defined(_POSIX_THREAD_PRIO_INHERIT) || defined(_POSIX_THREAD_PRIO_PROTECT) + +// Set priority inversion protection protocol +externC int pthread_mutexattr_setprotocol ( pthread_mutexattr_t *attr, + int protocol); + +// Get priority inversion protection protocol +externC int pthread_mutexattr_getprotocol ( pthread_mutexattr_t *attr, + int *protocol); + +#if defined(_POSIX_THREAD_PRIO_PROTECT) + +// Set priority for priority ceiling protocol +externC int pthread_mutexattr_setprioceiling ( pthread_mutexattr_t *attr, + int prioceiling); + +// Get priority for priority ceiling protocol +externC int pthread_mutexattr_getprioceiling ( pthread_mutexattr_t *attr, + int *prioceiling); + +// Set priority ceiling of given thread, returning old ceiling. +externC int pthread_mutex_setprioceiling( pthread_mutex_t *mutex, + int prioceiling, + int *old_ceiling); + +// Get priority ceiling of given thread +externC int pthread_mutex_getprioceiling( pthread_mutex_t *mutex, + int *prioceiling); +#endif + +#endif + +//----------------------------------------------------------------------------- +// Mutex functions + +// Initialize mutex. If mutex_attr is NULL, use default attributes. +externC int pthread_mutex_init (pthread_mutex_t *mutex, + const pthread_mutexattr_t *mutex_attr); + +// Destroy mutex. +externC int pthread_mutex_destroy (pthread_mutex_t *mutex); + +// Lock mutex, waiting for it if necessary. +externC int pthread_mutex_lock (pthread_mutex_t *mutex); + +// Try to lock mutex. +externC int pthread_mutex_trylock (pthread_mutex_t *mutex); + + +// Unlock mutex. +externC int pthread_mutex_unlock (pthread_mutex_t *mutex); + + + +//============================================================================= +// Condition Variables + +//----------------------------------------------------------------------------- +// Attribute manipulation functions +// We do not actually support any attributes at present, so these do nothing. + +// Initialize condition variable attributes +externC int pthread_condattr_init (pthread_condattr_t *attr); + +// Destroy condition variable attributes +externC int pthread_condattr_destroy (pthread_condattr_t *attr); + +//----------------------------------------------------------------------------- +// Condition variable functions + +// Initialize condition variable. +externC int pthread_cond_init (pthread_cond_t *cond, + const pthread_condattr_t *attr); + +// Destroy condition variable. +externC int pthread_cond_destroy (pthread_cond_t *cond); + +// Wake up one thread waiting for condition variable +externC int pthread_cond_signal (pthread_cond_t *cond); + +// Wake up all threads waiting for condition variable +externC int pthread_cond_broadcast (pthread_cond_t *cond); + +// Block on condition variable until signalled. The mutex is +// assumed to be locked before this call, will be unlocked +// during the wait, and will be re-locked on wakeup. +externC int pthread_cond_wait (pthread_cond_t *cond, + pthread_mutex_t *mutex); + +// Block on condition variable until signalled, or the timeout expires. +externC int pthread_cond_timedwait (pthread_cond_t *cond, + pthread_mutex_t *mutex, + const struct timespec *abstime); + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_POSIX_MUTEX_H +// End of mutex.h
--- a/packages/compat/posix/current/include/pthread.h +++ b/packages/compat/posix/current/include/pthread.h @@ -190,114 +190,6 @@ externC int pthread_getschedparam (pthre //============================================================================= -// Mutexes - -//----------------------------------------------------------------------------- -// Mutex attributes manipulation functions - -// Initialize attribute object -externC int pthread_mutexattr_init ( pthread_mutexattr_t *attr); - -// Destroy attribute object -externC int pthread_mutexattr_destroy ( pthread_mutexattr_t *attr); - -#if defined(_POSIX_THREAD_PRIO_INHERIT) || defined(_POSIX_THREAD_PRIO_PROTECT) - -// Set priority inversion protection protocol -externC int pthread_mutexattr_setprotocol ( pthread_mutexattr_t *attr, - int protocol); - -// Get priority inversion protection protocol -externC int pthread_mutexattr_getprotocol ( pthread_mutexattr_t *attr, - int *protocol); - -#if defined(_POSIX_THREAD_PRIO_PROTECT) - -// Set priority for priority ceiling protocol -externC int pthread_mutexattr_setprioceiling ( pthread_mutexattr_t *attr, - int prioceiling); - -// Get priority for priority ceiling protocol -externC int pthread_mutexattr_getprioceiling ( pthread_mutexattr_t *attr, - int *prioceiling); - -// Set priority ceiling of given thread, returning old ceiling. -externC int pthread_mutex_setprioceiling( pthread_mutex_t *mutex, - int prioceiling, - int *old_ceiling); - -// Get priority ceiling of given thread -externC int pthread_mutex_getprioceiling( pthread_mutex_t *mutex, - int *prioceiling); -#endif - -#endif - -//----------------------------------------------------------------------------- -// Mutex functions - -// Initialize mutex. If mutex_attr is NULL, use default attributes. -externC int pthread_mutex_init (pthread_mutex_t *mutex, - const pthread_mutexattr_t *mutex_attr); - -// Destroy mutex. -externC int pthread_mutex_destroy (pthread_mutex_t *mutex); - -// Lock mutex, waiting for it if necessary. -externC int pthread_mutex_lock (pthread_mutex_t *mutex); - -// Try to lock mutex. -externC int pthread_mutex_trylock (pthread_mutex_t *mutex); - - -// Unlock mutex. -externC int pthread_mutex_unlock (pthread_mutex_t *mutex); - - - -//============================================================================= -// Condition Variables - -//----------------------------------------------------------------------------- -// Attribute manipulation functions -// We do not actually support any attributes at present, so these do nothing. - -// Initialize condition variable attributes -externC int pthread_condattr_init (pthread_condattr_t *attr); - -// Destroy condition variable attributes -externC int pthread_condattr_destroy (pthread_condattr_t *attr); - -//----------------------------------------------------------------------------- -// Condition variable functions - -// Initialize condition variable. -externC int pthread_cond_init (pthread_cond_t *cond, - const pthread_condattr_t *attr); - -// Destroy condition variable. -externC int pthread_cond_destroy (pthread_cond_t *cond); - -// Wake up one thread waiting for condition variable -externC int pthread_cond_signal (pthread_cond_t *cond); - -// Wake up all threads waiting for condition variable -externC int pthread_cond_broadcast (pthread_cond_t *cond); - -// Block on condition variable until signalled. The mutex is -// assumed to be locked before this call, will be unlocked -// during the wait, and will be re-locked on wakeup. -externC int pthread_cond_wait (pthread_cond_t *cond, - pthread_mutex_t *mutex); - -// Block on condition variable until signalled, or the timeout expires. -externC int pthread_cond_timedwait (pthread_cond_t *cond, - pthread_mutex_t *mutex, - const struct timespec *abstime); - - - -//============================================================================= // Dynamic package initialization // Initializer for pthread_once_t instances
--- a/packages/compat/posix/current/src/sched.cxx +++ b/packages/compat/posix/current/src/sched.cxx @@ -174,7 +174,7 @@ int sched_get_priority_max (int policy) return -1; } - int pri = PTHREAD_POSIX_PRIORITY( CYG_THREAD_MIN_PRIORITY ); + int pri = PTHREAD_POSIX_PRIORITY( CYG_THREAD_MAX_PRIORITY ); CYG_REPORT_RETVAL( pri ); return pri; @@ -196,7 +196,7 @@ int sched_get_priority_min (int policy) return -1; } - int pri = PTHREAD_POSIX_PRIORITY( CYG_THREAD_MAX_PRIORITY ); + int pri = PTHREAD_POSIX_PRIORITY( CYG_THREAD_MIN_PRIORITY ); CYG_REPORT_RETVAL( pri ); return pri;
--- a/packages/compat/posix/current/src/sem.cxx +++ b/packages/compat/posix/current/src/sem.cxx @@ -165,7 +165,7 @@ externC int sem_trywait (sem_t *sem) if( !sema->trywait() ) retval = EAGAIN; - SEMA_RETURN(0); + SEMA_RETURN(retval); } // -------------------------------------------------------------------------
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/mips/vrc437x/current/ChangeLog @@ -0,0 +1,31 @@ +2001-09-10 Nick Garnett <nickg@redhat.com> + + * cdl/flash_mips_vrc437x.cdl: + * src/mips_vrc437x_flash.c: + Created by copying the ocelot package. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/mips/vrc437x/current/cdl/flash_mips_vrc437x.cdl @@ -0,0 +1,61 @@ +# ==================================================================== +# +# flash_mips_vrc437x.cdl +# +# FLASH memory - Hardware support for VRC437X board +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Contributors: jskov, nickg +# Date: 2001-19-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_MIPS_VRC437X { + display "Flash memory support for VRC437X board" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_MIPS_VR4300_VRC437X + + implements CYGHWR_IO_FLASH_DEVICE + + compile mips_vrc437x_flash.c + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED { + display "AMD AM29F040B driver required" + } + + implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED + requires CYGHWR_DEVS_FLASH_AMD_AM29F040B +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/mips/vrc437x/current/src/mips_vrc437x_flash.c @@ -0,0 +1,60 @@ +//========================================================================== +// +// mips_vrc437x_flash.c +// +// Flash programming for AMD device on NEC VRC437X board +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov, nickg +// Date: 2001-09-10 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Device properties + +#define CYGNUM_FLASH_INTERLEAVE (1) +#define CYGNUM_FLASH_SERIES (1) +#define CYGNUM_FLASH_WIDTH (8) +#define CYGNUM_FLASH_BASE (0xbfc00000u) + +//-------------------------------------------------------------------------- +// Platform specific extras + +//-------------------------------------------------------------------------- +// Now include the driver code. +#include "cyg/io/flash_am29xxxxx.inl" + +// ------------------------------------------------------------------------ +// EOF mips_vrc437x_flash.c
--- a/packages/devs/serial/arm/aeb/current/ChangeLog +++ b/packages/devs/serial/arm/aeb/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_aeb.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_arm_aeb.cdl: Moved testing parameters here.
--- a/packages/devs/serial/arm/aeb/current/cdl/ser_arm_aeb.cdl +++ b/packages/devs/serial/arm/aeb/current/cdl/ser_arm_aeb.cdl @@ -85,7 +85,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_AEB_S display "Baud rate for the ARM AEB-1 serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -125,7 +125,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_AEB_S display "Baud rate for the ARM AEB-1 serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/arm/at91/current/ChangeLog +++ b/packages/devs/serial/arm/at91/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_at91.cdl: + Fix 234000->230400 typo. + 2001-08-14 Jonathan Larmour <jlarmour@redhat.com> * src/at91_serial.c (at91_serial_stop_xmit): Write to IDR, not IER.
--- a/packages/devs/serial/arm/at91/current/cdl/ser_arm_at91.cdl +++ b/packages/devs/serial/arm/at91/current/cdl/ser_arm_at91.cdl @@ -84,7 +84,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_AT91_ display "Baud rate for the Atmel AT91 serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -124,7 +124,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_AT91_ display "Baud rate for the Atmel AT91 serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/arm/cma230/current/ChangeLog +++ b/packages/devs/serial/arm/cma230/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_cma230.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * src/cma230_serial.c: Fix typo.
--- a/packages/devs/serial/arm/cma230/current/cdl/ser_arm_cma230.cdl +++ b/packages/devs/serial/arm/cma230/current/cdl/ser_arm_cma230.cdl @@ -85,7 +85,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_CMA23 display "Baud rate for the Cogent ARM/CMA230 serial port A driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -125,7 +125,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_CMA23 display "Baud rate for the Cogent ARM/CMA230 serial port B driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/arm/ebsa285/current/ChangeLog +++ b/packages/devs/serial/arm/ebsa285/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_ebsa285.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_arm_ebsa285.cdl: Testing parameters moved here.
--- a/packages/devs/serial/arm/ebsa285/current/cdl/ser_arm_ebsa285.cdl +++ b/packages/devs/serial/arm/ebsa285/current/cdl/ser_arm_ebsa285.cdl @@ -84,7 +84,7 @@ cdl_package CYGPKG_IO_SERIAL_ARM_EBSA285 display "Baud rate for the Intel StrongARM/EBSA285 serial port" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 \ - 4800 7200 9600 14400 19200 38400 57600 115200 234000 } + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " This option specifies the default baud rate (speed) for the
--- a/packages/devs/serial/arm/edb7xxx/current/ChangeLog +++ b/packages/devs/serial/arm/edb7xxx/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_edb7xxx.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_arm_edb7xxx.cdl: Moved testing parameters here.
--- a/packages/devs/serial/arm/edb7xxx/current/cdl/ser_arm_edb7xxx.cdl +++ b/packages/devs/serial/arm/edb7xxx/current/cdl/ser_arm_edb7xxx.cdl @@ -86,7 +86,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_EDB7X display "Baud rate for the Cirrus Logic EDB7XXX serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -126,7 +126,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_EDB7X display "Baud rate for the Cirrus Logic EDB7XXX serial port 2 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/arm/pid/current/ChangeLog +++ b/packages/devs/serial/arm/pid/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_pid.cdl: + Fix 234000->230400 typo. + 2000-09-18 Jesper Skov <jskov@redhat.com> * src/pid_serial.h: [removed]
--- a/packages/devs/serial/arm/pid/current/cdl/ser_arm_pid.cdl +++ b/packages/devs/serial/arm/pid/current/cdl/ser_arm_pid.cdl @@ -99,7 +99,7 @@ cdl_package CYGPKG_IO_SERIAL_ARM_PID { flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 - 57600 115200 234000 } + 57600 115200 230400 } default_value 38400 description " This option specifies the default baud rate (speed) @@ -144,7 +144,7 @@ cdl_package CYGPKG_IO_SERIAL_ARM_PID { flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 - 57600 115200 234000 } + 57600 115200 230400 } default_value 38400 description " This option specifies the default baud rate (speed)
--- a/packages/devs/serial/arm/sa11x0/current/ChangeLog +++ b/packages/devs/serial/arm/sa11x0/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_arm_sa11x0.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_arm_sa11x0.cdl: Testing parameters moved here.
--- a/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl +++ b/packages/devs/serial/arm/sa11x0/current/cdl/ser_arm_sa11x0.cdl @@ -84,7 +84,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_SA11X display "Baud rate for the ARM SA11X0 serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -124,7 +124,7 @@ cdl_component CYGPKG_IO_SERIAL_ARM_SA11X display "Baud rate for the ARM SA11X0 serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/i386/pc/current/ChangeLog +++ b/packages/devs/serial/i386/pc/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_i386_pc.cdl: + Fix 234000->230400 typo. + 2001-06-08 Jonathan Larmour <jlarmour@redhat.com> * include/i386_pc_ser.inl: Use generic 16x5x driver now.
--- a/packages/devs/serial/i386/pc/current/cdl/ser_i386_pc.cdl +++ b/packages/devs/serial/i386/pc/current/cdl/ser_i386_pc.cdl @@ -91,7 +91,7 @@ cdl_component CYGPKG_IO_SERIAL_I386_PC_S display "Baud rate for the PC serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -161,7 +161,7 @@ cdl_component CYGPKG_IO_SERIAL_I386_PC_S display "Baud rate for the PC serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/loop/current/ChangeLog +++ b/packages/devs/serial/loop/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_loop.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_loop.cdl: Moved testing parameters here.
--- a/packages/devs/serial/loop/current/cdl/ser_loop.cdl +++ b/packages/devs/serial/loop/current/cdl/ser_loop.cdl @@ -86,7 +86,7 @@ cdl_package CYGPKG_IO_SERIAL_LOOP { flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 - 57600 115200 234000 + 57600 115200 230400 } default_value 38400 description " @@ -126,7 +126,7 @@ cdl_package CYGPKG_IO_SERIAL_LOOP { flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 - 57600 115200 234000 + 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/mips/atlas/current/ChangeLog +++ b/packages/devs/serial/mips/atlas/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_atlas.cdl: + Fix 234000->230400 typo. + 2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> * src/atlas_serial.c (atlas_serial_set_config): Now use keys to make
--- a/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl +++ b/packages/devs/serial/mips/atlas/current/cdl/ser_mips_atlas.cdl @@ -95,7 +95,7 @@ cdl_component CYGPKG_IO_SERIAL_MIPS_ATLA display "Baud rate for the MIPS ATLAS serial port driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/mips/jmr3904/current/ChangeLog +++ b/packages/devs/serial/mips/jmr3904/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_mips_jmr3904.cdl: Moved testing parameters here.
--- a/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl +++ b/packages/devs/serial/mips/jmr3904/current/cdl/ser_mips_jmr3904.cdl @@ -95,7 +95,7 @@ cdl_component CYGPKG_IO_SERIAL_TX39_JMR3 display "Baud rate for the TX39 JMR3904 serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -133,7 +133,7 @@ cdl_component CYGPKG_IO_SERIAL_TX39_JMR3 display "Baud rate for the TX39 JMR3904 serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
deleted file mode 100644 --- a/packages/devs/serial/mips/vrc4373/current/ChangeLog +++ /dev/null @@ -1,1183 +0,0 @@ -2000-10-12 Jesper Skov <jskov@redhat.com> - - * cdl/ser_mips_vrc4373.cdl: Moved testing parameters here. - -2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> - - * src/vrc4373_serial.c (vrc4373_serial_set_config): Now use keys - to make more flexible. - -2000-07-22 Jonathan Larmour <jlarmour@redhat.co.uk> - - * src/vrc4373_serial.c (vrc4373_serial_init): Add comment about broken - interrupt handling - -2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> - - * cdl/<yournamehere>.cdl: Remove the comment on the empty - include_files directive; the tools now support this correctly. - This keeps internal include files internal. - -2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> - - * cdl/ser_mips_vrc4373.cdl: Change the parent from CYGPKG_IO_SERIAL - (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES - (which is not...) thus allowing convenient control independent of - platform. Also enable all individual devices by default, now, so - that they can be enabled simply by enabling the above new parent. - -2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> - - * ecos.db: Re-organize device packages. This is a massive change - involving deleting all the sources for serial and ethernet drivers - from where they used to live in - packages/io/serial/current/src/ARCH/PLATFORM.[ch] - packages/net/drivers/eth/PLATFORM/current/src/... - and reinstating them in - packages/devs/serial/ARCH/PLATFORM/current/src/... - packages/devs/eth/ARCH/PLATFORM/current/src/... - - All these new packages are properly defined in ecos.db, and are - all of type "hardware" so that a "target" can grab them. - - This directory layout is descriptive of the devices we have right - now, arch and platform are separate levels just to make it easier - to navigate in the filesystem and similar to the HAL structure in - the filesystem. - - It is *not* prescriptive of future work; for example, the mythical - common highly-portable 16550 serial driver which works on many - targets would be called "devs/serial/s16550/current", or a serial - device for a particular board (cogent springs to mind) that can - work with different CPUs fitted is "devs/serial/cogent/current". - - Changelogs have been preserved and replicated over all the new - packages, so that no history is lost. - - The contents of individual source files are unchanged; they build - in just the same emvironment except for a very few cases where the - config file name changed in this movement. - - Targets in ecos.db have been redefined to bring in all relevant - hardware packages including net and serial drivers (but the newly - included packages are only active if their desired parent is - available.) - - The names of CDL options (and their #defines of course) stay the - same for the serial drivers, for backward compatibility. - - * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added - rather than it being in (almost) all target definitions. - -2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> - - * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r - (tty_write): Similarly - - * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and - CYG_TTY_IN_FLAGS_CRLF to match - -2000-03-31 Jesper Skov <jskov@redhat.com> - - * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. - * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired - constants. - -2000-03-28 John Dallaway <jld@cygnus.co.uk> - - * cdl/io_serial.cdl, - cdl/ser_arm_aeb.cdl, - cdl/ser_arm_cma230.cdl, - cdl/ser_arm_edb7xxx.cdl, - cdl/ser_arm_pid.cdl, - cdl/ser_i386_pc.cdl, - cdl/ser_mips_jmr3904.cdl, - cdl/ser_mips_vrc4373.cdl, - cdl/ser_mn10300.cdl, - cdl/ser_powerpc_cogent.cdl, - cdl/ser_quicc_smc.cdl, - cdl/ser_sh_edk7708.cdl, - cdl/ser_sparclite_sleb.cdl, - cdl/tty.cdl: - - Adjust documentation URLs. - -2000-03-07 Jesper Skov <jskov@redhat.com> - - * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. - -2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> - - * include/serialio.h: Correct baud rate typo: 230400 rather than - 234000. Thanks to Grant Edwards for the report. - -2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> - - * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. - -2000-02-28 Jesper Skov <jskov@redhat.com> - - * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent - again. Fixed interrupt problem. - -2000-02-22 Jesper Skov <jskov@redhat.com> - - * tests/ser_test_protocol.inl: Don't use 115200 baud on - Cogent. Our slower boards can't keep up. - -2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> - - * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. - -2000-02-16 Nick Garnett <nickg@cygnus.co.uk> - - * include/pkgconf/io_serial.h: - Added configury for PC serial device drivers. - - * cdl/ser_i386_pc.cdl: - * src/i386/pc_serial.c: - * src/i386/pc_serial.h: - Added these files to implement PC serial line drivers. - - * cdl/io_serial.cdl: - Added CYGPKG_IO_SERIAL_I386_PC. - - * tests/ser_test_protocol.inl: - Added support for PC serial line testing. - -2000-02-11 Jesper Skov <jskov@redhat.com> - - * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): - * src/sparclite/sleb_sdtr.c: - serial_devio => cyg_io_serial_devio - -2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> - - * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* - preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form - now. - -2000-02-03 Jesper Skov <jskov@redhat.com> - - * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... - -2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> - - * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper - case macros - - * src/arm/aeb_serial.c: Update to reflect above - -2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> - * cdl/*.cdl: - - Adjust help URLs in line with new doc layout. - -2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> - * cdl/*.cdl: - - Adjust help URLs in line with new doc layout. - -2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> - - * src/common/tty.c (tty_read): Fix problem with backspace at start - of line (size must be 'signed' for compare to work). - -2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> - - * cdl/*.cdl: Add descriptions to a number of options &c which were - lacking same, also tidied up other typos as noticed en passant. - -2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> - - * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at - start of line. - -2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> - - * src/common/serial.c (serial_write): Avoid potential deadlock if - transmit start actually sends enough characters to signal cond wait. - -2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> - - * include/serial.h: Fix namespace pollution - - serial_devio => cyg_io_serial_devio - serial_callbacks => cyg_io_serial_callbacks - - * src/mips/tx3904_serial.c: - * src/mips/vrc4373_serial.c: - * src/mn10300/mn10300_serial.c: - * src/powerpc/quicc_smc_serial.c: - * src/powerpc/cogent_serial_with_ints.c: - * src/sparclite/sleb_sdtr.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: - * src/arm/edb7xxx_serial.c: - * src/arm/cma230_serial.c: - * src/arm/ebsa285_serial.c: - * src/common/haldiag.c: - * src/common/serial.c: Fix namespace pollution - - serial_devio => cyg_io_serial_devio - -1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle - case where an interrupt represents multiple events. - -1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> - - * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. - -1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Remove mention of 7209/7212. - -1999-11-03 John Dallaway <jld@cygnus.co.uk> - - * cdl/io_serial.cdl: Define build options. - -1999-10-26 Jesper Skov <jskov@cygnus.co.uk> - * tests/serial5.c (serial_test): Reduce speed in thumb mode. - - * src/arm/pid_serial.h: Added BE support. - - * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what - needs to be compiled. - -1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/pid_serial.h (ISR_RxTO): Define - character received but - not handled "promptly". - - * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts - properly (can't ignore them even with TO bit set). - - * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all - input (empty input FIFO) otherwise characters get dropped. - -1999-10-15 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. - -1999-10-11 Nick Garnett <nickg@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added configury for VR4300 testing. - - * src/mips/vrc4373_serial.c: Added Bi-endian support. - - * include/pkgconf/io_serial.h: Adjusted default baud rates to - 38400. - -1999-10-06 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. - -1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> - - * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct - value supplied for interrupt priority - it may be unused, but it - is asserted for range. Initialize the diagnostic channel if on an - MBX and if NOT using SMC1 ourselves, to ensure that diag output - and built-in stubs work correctly; otherwise reset the quicc and - ignore SMC1 as before. Fix various warnings, mostly about - casting/arg-passing/assigning away volatile. - -1999-08-31 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Define dummy crash ID. - -1999-08-30 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added crash information which - should help track down repeating errors. - -1999-08-20 Jesper Skov <jskov@cygnus.co.uk> - - * tests/README: Added. - -1999-08-18 Jesper Skov <jskov@cygnus.co.uk> - - * tests/tty1.c: - * tests/tty2.c: - * tests/serial1.c: - * tests/serial2.c: - * tests/serial3.c: - * tests/serial4.c: - * tests/serial5.c: - * tests/PKGconf.mak: - Require kernel and kernel C API. - -1999-08-17 Nick Garnett <nickg@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c: Added a simple implementation of a - receive FIFO to try and reduce the overhead of receiving bytes. - -1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * src/PKGconf.mak: - * src/mn10300/mn10300_serial.c: - * tests/ser_test_protocol.inl: - Rename all am32 -> am31 - -1999-08-12 Nick Garnett <nickg@cygnus.co.uk> - - Imported following changes from development branch: - - 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> - - * tests/serial5.c: Modified config test for boards that need a lower - speed for this test. - - * tests/ser_test_protocol.inl: Removed 14400 baud tests for all - MN10300 variants. The MN10300 cannot currently do this speed. - - * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt - enable/disable code to be variant specific. - - * include/pkgconf/io_serial.h: Undid Jonathan's change, since the - same options are used for all MN10300 variants. - - 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * include/pkgconf/io_serial.h: - Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to - CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific - - 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> - - * tests/ser_test_protocol.inl: - Changed names of MN10300 defines tested. Added AM33 definitions. - - * src/mn10300/mn10300_serial.c: - Modified driver to work on am33 too. This simply requires some - alternate definitions of things like register addresses and some - bits in them plus some extra parameterization of some register - values. - - * src/PKGconf.mak: - Added am33 to list of architectures supporting serial lines. - -1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Update descriptions to be more - generic (CL7x11 instead of CL7211). - -1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Correct typos in CDL description - for serial port 2 driver - -1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> - - * src/arm/ebsa285_serial.c: New file: device driver for the serial - device of the Intel StrongARM EBSA-285 evaluation board. - - * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): - Config for it. - - * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. - - * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. - -1999-07-08 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl (change_config): Changed implementation. - -1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> - - * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust - initialization, with data cache disabled. This seems to fix the - random failures described below. - - * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. - Added some delays in the configuration change code to make QUICC - happy [didn't help much although the manual says they are required]. - - * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to - match what the Linux driver uses - still doesn't work well, though. - - * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the - serial driver working and robust. At this point it works quite well, - using the default buffer sizes. Changing from the defaults seem to - easily break it though, certainly on input. Also, changing the baud - rate seems to not work reliably. - - * src/common/serial.c: Add some tracing/debug info to try and debug - problems with QUICC serial driver. These are hard disabled with - "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information - about how/when data are delivered from the serial driver. - - * include/pkgconf/io_serial.h: Adjust limits and defaults on number and - size of buffers with values that seem to work. - -1999-06-21 Jesper Skov <jskov@cygnus.co.uk> - - * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit - to avoid compiler warnings. - -1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Fix CDL for number of buffers. - - * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. - -1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Some clean up (removed commented - obsolete CDL parenting structure). - Add support for Motorola PowerPC QUICC/SMC. - - * src/arm/cma230_serial.c: - * src/arm/cl7211_serial.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' - prototypes. - -1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which - cause xmitter to get stuck. - -1999-06-16 Jesper Skov <jskov@cygnus.co.uk> - - * src/sh/sh_serial.c: [removed] - * src/sh/sh_sci_serial.c: [added] - * src/sh/sh_sci_7708.inl: [added] - * include/pkgconf/io_serial.h: - * src/PKGconf.mak (EXTRAS_COMPILE): - * tests/ser_test_protocol.inl: - Renamed CDL options and restructered driver. - Fixed CDL typo. - -1999-06-04 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. - -1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Disable testing at 115200 - for Cogent CMA230 (ARM). - - * src/arm/cma230_serial.c: Fix interrupt for port B. - -1999-05-31 Jesper Skov <jskov@cygnus.co.uk> - - * src/sh/sh_serial.c: Fixed receive interrupts and added handler for - error interrupts. - -1999-05-28 Jesper Skov <jskov@cygnus.co.uk> - - * io/serial/current/src/PKGconf.mak: - * io/serial/current/tests/ser_test_protocol.inl: - * include/pkgconf/io_serial.h: - Renamed SH platform package to edk7708. - -1999-05-27 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added ability to change options in - host software. - -1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): - Wait for the serial device to become acquiescent before disabling - it. This prevents cygmon's outgoing characters getting corrupted - due to transmission being disabled. - Fix for PR 20047 - -1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: - * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. - - * src/arm/cma230_serial.c: Make names compatible with Cogent - PowerPC board. - -1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. -1999-05-26 Jesper Skov <jskov@cygnus.co.uk> - - * src/sh/sh_serial.c: Added more baud rate values. Disabled - interrupt driven receive. Fixed config_port to enable proper - interrupt flags. - -1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * tests/ser_test_protocol.inl: - Change all mentions of CYGPKG_HAL_TX39_JMR3904 to - CYGPKG_HAL_MIPS_TX39_JMR3904 - -1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to - CYG_HAL_MIPS_TX39 -1999-05-25 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added sh entry. - -1999-05-24 Jesper Skov <jskov@cygnus.co.uk> - - * src/PKGconf.mak: - * include/pkgconf/io_serial.h: - * src/sh/sh_serial.c: - Added sh driver. - -1999-05-18 Jesper Skov <jskov@cygnus.co.uk> - PR 19926 - * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if - there is one. - -1999-05-18 Jesper Skov <jskov@cygnus.co.uk> - PR 19926 - * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char - if there is one. - -1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/cl7211_serial.c: Clean up, first working version. - -1999-05-14 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Removed workaround for spurious - Cogent reads. - - * src/arm/aeb_serial.c: - * src/arm/aeb_serial.h: - * src/arm/pid_serial_with_ints.c: - * src/arm/pid_serial.h: - * src/powerpc/cogent_serial.h: - * src/powerpc/cogent_serial_with_ints.c: - Check for receive interrupt before reading. - -1999-05-13 Nick Garnett <nickg@cygnus.co.uk> - - The follow changes were made in a branch an have now been merged: - - 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> - - * src/mips/vrc4373_serial.c: Small changes to get working with - interrupts. - - 1999-04-20 John Dallaway <jld@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 - parent attribute. - -1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/cl7211_serial.c: Fix compile problems from merged code. - -1999-05-05 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Tidied up a bit and added - description of protocol. - -1999-05-05 Jesper Skov <jskov@cygnus.co.uk> - - * src/common/serial.c (serial_write, serial_read): Clear abort - flag at entry. - -1999-05-05 Jesper Skov <jskov@cygnus.co.uk> - - * tests/serial4.c (serial_test): Handle config fails correctly. - - * tests/ser_test_protocol.inl: Better change_config - handling. Simple recovery and negotiation isn't timing - dependant. - -1999-05-05 Jesper Skov <jskov@cygnus.co.uk> - - * tests/timeout.inl: Updated with the below changes. - -1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> - - * misc/timeout.inl (timeout): Timeouts are relative, but alarms - need absolute time values. - -1999-05-04 Jesper Skov <jskov@cygnus.co.uk> - PR 20018 - * tests/serial1.c (serial_test): Always PASS, regardless of - configuration. - -1999-05-04 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Reverse order of configurations - - run tests with slow baud rate first. - Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. - -1999-05-04 Jesper Skov <jskov@cygnus.co.uk> - * src/mn10300/mn10300_serial.c: - Use interrupt enable/disable feature of serial port2 to allow - coexistence with CygMon/hal_diag. - - * tests/ser_test_protocol.inl: Use port2 for MN10300. - -1999-04-28 Bart Veer <bartv@cygnus.co.uk> - - * src/PKGconf.mak (EXTRAS_COMPILE): - Use the new rules for generating libextras.a - -1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. - - -1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. -1999-04-20 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 - for SLEB. Only run test on SLEB if CygMon isn't used for diag - output. - -1999-04-15 Jesper Skov <jskov@cygnus.co.uk> - PR 19752 - * tests/serial3.c: - * tests/serial5.c: - Run these tests at a lower baud rate on ARM AEB. - -1999-04-14 Jesper Skov <jskov@cygnus.co.uk> - PR 19839 - * src/mn10300/mn10300_serial.c: - Fix compiler warnings. - -1999-04-14 Bart Veer <bartv@cygnus.co.uk> - - * include/pkgconf/io_serial.h: - Reparent the board-specific serial devices below the actual boards. - -1999-04-13 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: - NA when run from simulator. - -1999-04-12 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: - Disabled 115200 for MN10300. - Reclaim interrupt vectors from CygMon when testing on SLEB. - -1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> - - * include/serial.h: Change SERIAL_CHANNEL setup so all channels - have serial callbacks, regardless of buffering. - -1999-04-09 Jesper Skov <jskov@cygnus.co.uk> - - * src/common/tty.c: - * include/pkgconf/io_serial.h: - Added new ttydiag device layered on top of haldiag, so that tty0 - can be layered on top of ser0. - -1999-04-08 Jesper Skov <jskov@cygnus.co.uk> - - * tests/tty1.c: [added] - * tests/tty2.c: [added] - * tests/PKGconf.mak: - * tests/ser_test_protocol.inl: - Added two simple TTY tests. - -1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> - - * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O - macros instead of hal_diag.h where they had evolved before. - -1999-04-06 Jesper Skov <jskov@cygnus.co.uk> - - * tests/serial4.c (serial_test): - * tests/serial3.c (serial_test): - Reduce packet sizes. - -1999-03-31 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Added remaining targets to the - test. - -1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> - - * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race - when enabling xmit interrupts. - -1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> - - * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter - is now always enabled, just the interrupts are masked/unmasked to control it. - This lets the serial driver cooperate with Cygmon on the port used for GDB. - Note that currently serial input does not work for CON1 since Cygmon is - taking all of the receive interrupts for itself. - (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be - enabled - otherwise it can get enabled incorrectly and we get interrupted - to death! - -1999-03-26 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Send a DONE message after a no-echo - binary packet. - -1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> - - * tests/serial5.c: - * tests/serial4.c: - * tests/serial3.c: - * tests/serial2.c: - * tests/serial1.c: - Make these build when no kernel present; include of testcase - was the wrong side of the ifdef. - -1999-03-26 Jesper Skov <jskov@cygnus.co.uk> - - * tests/serial5.c: - * tests/serial4.c: - * tests/serial3.c: - * tests/serial2.c: - * tests/serial1.c: - Moved NOP check to ser_test_protocol open call. - - * tests/ser_test_protocol.inl: Make sure the proper device is - selected for testing. Do NOP check in open call. - -1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: - * misc/console.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: - * src/common/tty.c: - * src/mips/tx3904_serial.c: - * src/mn10300/mn10300_serial.c: - * src/powerpc/cogent_serial_with_ints.c: - * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. - - * src/mips/tx3904_serial.c (tx3904_serial_config_port): - Make sure port is enabled (CDL) before using it. - - * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): - * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): - * src/arm/aeb_serial.c (aeb_serial_config_port): - * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that - the physical port is not modified unless the provided configuration is valid. - - * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): - Using wrong config data. - - * include/serialio.h: Add macros to support baud rate from CDL. - - * include/pkgconf/io_serial.h: - * src/mn10300/mn10300_serial.c: - * src/mips/tx3904_serial.c (tx3904_serial_ISR): - * src/sparclite/sleb_sdtr.c: - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/pid_serial_with_ints.c: - * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. - -1999-03-24 Nick Garnett <nickg@cygnus.co.uk> - - * src/mips/tx3904_serial.c: - Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU - frequency. This is a little more accurate than using - CYGHWR_HAL_MIPS_CPU_FREQ. - -1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> - - * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. - - * src/arm/aeb_serial.c (aeb_serial_stop_xmit): - * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. - -1999-03-24 Jesper Skov <jskov@cygnus.co.uk> - - * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't - like. - - * src/powerpc/cogent_serial.h: - Added copyright header. - - * tests/ser_test_protocol.inl: - * tests/serial1.c: - * tests/serial2.c: - * tests/serial3.c: - * tests/serial4.c: - * tests/serial5.c: - Don't try to run tests when no IO device has been specified. - -1999-03-23 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, - * misc/serial5.c, misc/ser_test_protocol.inl - Deleted. - -1999-03-23 Jesper Skov <jskov@cygnus.co.uk> - - * misc/PKGconf.mak: - * tests/timeout.inl: - * tests/PKGconf.mak: - * tests/serial1.c: - * tests/serial2.c: - * tests/serial3.c: - * tests/serial4.c: - * tests/serial5.c: - * tests/ser_test_protocol.inl: - Moved the serial tests from the misc directory to the tests - directory. - -1999-03-23 Nick Garnett <nickg@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts - at initialization and unmask/remask in start/stop xmit - routines. This has no real effect on the hardware, but the - simulator does not implement the LCR_TXE bit properly, resulting - in spurious TX interrupts during diagnostic output. - This was the cause of the slow output reported in PR 19559. - -1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate - case - mostly lower case. - -1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> - - * misc/console.c: - * misc/serial.c: - * misc/serial1.c: - * misc/serial2.c: - * misc/serial3.c: - * misc/serial4.c: - * misc/serial5.c: - Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of - CYGNUM_HAL_MINIMUM_STACK_SIZE. - -1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c: - * src/mips/tx3904_serial.c: Add CDL configury. - - * include/pkgconf/io_serial.h: Update CDL to add device name - configurability for all devices. - - * src/sparclite/sleb_sdtr.c: - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: Use CDL configured device names. - -1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> - - * misc/serial1.c: - * misc/serial2.c: - * misc/serial3.c: - * misc/serial4.c: - * misc/serial5.c: - Requires kernel as well. - -1999-03-22 Jesper Skov <jskov@cygnus.co.uk> - - * src/sparclite/sleb_sdtr.c: - Moved include statement to avoid warnings. - -1999-03-19 Jesper Skov <jskov@cygnus.co.uk> - - * misc/ser_test_protocol.inl: - * misc/serial5.c: - * misc/PKGconf.mak: - Replace complex and not very stable duplex test with a simpler - test that works better. - Added serial5 using that test. - -1999-03-19 Jesper Skov <jskov@cygnus.co.uk> - - * misc/PKGconf.mak: - * misc/serial1.c: - * misc/serial2.c: - Added API test and made serial2 do simple string output. - -1999-03-19 Jesper Skov <jskov@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. - -1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: - Moved include statement to avoid warnings. - -1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: More CDL problems. - -1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. - - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/pid_serial_with_ints.c: - * src/arm/aeb_serial.c: Update device names to match CDL. - - * include/pkgconf/io_serial.h: Change names for serial ports to - be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. - -1999-03-18 Jesper Skov <jskov@cygnus.co.uk> - - * misc/ser_test_protocol.inl: - * misc/serial2.c: - First stab at the duplex binary test. Still much fun to be had... - -1999-03-18 Jesper Skov <jskov@cygnus.co.uk> - - * misc/ser_test_protocol.inl: Added timeout for PING. - -1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> - - * src/common/serial.c: Change ABORT functionality to be DSR safe. - (serial_get_config): Fix typo! - - * include/pkgconf/io_serial.h: Small change in CDL to make serial - devices tied to the platform and not the serial I/O package. This - means that only the devices appropriate to a given platform can be - enabled. - - * misc/serial.c: Better use of alarms - only trigger at the time of - the next timeout. Moved timeout functions to new file "timeout.inl". - - * src/common/serial.c (serial_get_config): Add support for - CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. - - * misc/serial.c: Add simple timeout mechanisms. - -1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. - - * include/pkgconf/io_serial.h: Add some CDL configury - not perfect - because of current ~CDL limitations. - -1999-03-17 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. - -1999-03-17 Jesper Skov <jskov@cygnus.co.uk> - - * misc/PKGconf.mak: - * misc/ser_test_protocol.inl: - * misc/serial2.c: - * misc/serial3.c: - * misc/serial4.c: - Put testing protocol implementation in a separate file. Split the - tests in serial2 into separate files. - -1999-03-16 Nick Garnett <nickg@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. - -1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Change default configurations. - No serial drivers enabled for PID port A or AEB. - - * src/sparclite/sleb_sdtr.c: - * src/powerpc/cogent_serial_with_ints.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: - * src/common/haldiag.c: - * src/common/tty.c: - * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init - messages. - - * src/powerpc/cogent_serial_with_ints.c: - * src/sparclite/sleb_sdtr.c: - * src/arm/aeb_serial.c: - * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> - -1999-03-15 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part - of binary protocol. - -1999-03-12 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c: Play a bit with timing. Think I broke it :( - Added DONE to BINARY packet. - Proper call to DRAIN. - -1999-03-12 Nick Garnett <nickg@cygnus.co.uk> - - * src/mips/tx3904_serial.c: Tidied away some debugging code. - -1999-03-12 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c: Removed bogus config changes. - -1999-03-12 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c (serial_test): Check for ser_filter on host (PING - packet). - -1999-03-11 Jesper Skov <jskov@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: Added note. - - * misc/serial2.c: - Added (almost) proper configuration handling. - Run tests on varying configurations. - -1999-03-11 Nick Garnett <nickg@cygnus.co.uk> - - * src/mips/tx3904_serial.c: - Many changes to get working. - - * misc/console.c (console_test): Fixed compiler warning. - - * misc/serial2.c: - Added device name for TX39 testing. - Fixed some bugs in Tcyg_io_write() macro. - -1999-03-10 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c: Added target specific test device name. - -1999-03-10 John Dallaway <jld@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Correct CDL description spelling. - -1999-03-10 Jesper Skov <jskov@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: - * misc/console.c: - Fixed compiler warnings. - -1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Improve CDL descriptions. - -1999-03-10 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c (serial_test): Do some more tests with changed - baud rates. - -1999-03-09 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c (serial_test): Added workaround for spurious byte - problem. Added a few more tests to run. - - * src/powerpc/cogent_serial_with_ints.c - (cogent_serial_config_port): Remove interrupt enabling. - -1999-03-09 Nick Garnett <nickg@cygnus.co.uk> - - * src/PKGconf.mak: - * src/mips/tx3904_serial.c: - Added initial version of TX39 device driver. Currently untested - but eliminates PR19445. - -1999-03-09 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c: DRAIN function works now. - -1999-03-09 Jesper Skov <jskov@cygnus.co.uk> - - * include/pkgconf/io_serial.h: Only enable one serial driver per - default. - -1999-03-08 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial2.c (serial_test): Be a bit more aggressive. - - * src/powerpc/cogent_serial_with_ints.c: Check that configuration - is sensible. - -1999-03-08 Jesper Skov <jskov@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: - Added support for both ports. - - * include/pkgconf/io_serial.h: Added simple defines for cogent - serial ports. No CDL yet. - -1999-03-08 Jesper Skov <jskov@cygnus.co.uk> - - * misc/serial.c: Removed PID references. Fixed compiler warnings. - -1999-03-08 Jesper Skov <jskov@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c: Cleaned up a - bit. Actually works now. - -1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> - - * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour - means DSR lock should be left alone. - -1999-03-08 Jesper Skov <jskov@cygnus.co.uk> - PR 19400 - * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set - valid interrupt priority. - -1999-03-05 Nick Garnett <nickg@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c (mn10300_serial_init): - Added extra test to avoid initializing serial 2 when CYGMON is - present. - Include hal_intr.h explicitly for use in non-kernel - configurations. - - * src/common/serial.c: - Added extra test before calls to cyg_drv_cond_wait() to avoid race - condition. This is not, however, a complete solution to this - problem. A better solution will be forthcoming. - - * include/serial.h: - Changed include files used to permit non-kernel configurations to - be built. - -1999-03-05 Jesper Skov <jskov@cygnus.co.uk> - - * src/common/haldiag.c: Removed diag_printf declaration. - -1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> - - * src/mn10300/mn10300_serial.c: - Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! - -1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> - - * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): - Fix renaming of interrupt vectors. - -1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> - - * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. - -1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> - - * serial/current/src/arm/pid_serial_with_ints.c: - New [somewhat] configurable drivers for PID. - -//=========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//===========================================================================
deleted file mode 100644 --- a/packages/devs/serial/mips/vrc4373/current/cdl/ser_mips_vrc4373.cdl +++ /dev/null @@ -1,195 +0,0 @@ -# ==================================================================== -# -# ser_mips_vrc4373.cdl -# -# eCos serial MIPS/VRC4373 configuration data -# -# ==================================================================== -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.1 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://www.redhat.com/ -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -# ==================================================================== -######DESCRIPTIONBEGIN#### -# -# Author(s): jskov -# Original data: gthomas -# Contributors: -# Date: 1999-07-14 -# -#####DESCRIPTIONEND#### -# -# ==================================================================== - - -cdl_package CYGPKG_IO_SERIAL_MIPS_VRC4373 { - display "VRC4373 serial device drivers" - - parent CYGPKG_IO_SERIAL_DEVICES - active_if CYGPKG_IO_SERIAL - active_if CYGPKG_HAL_MIPS_VR4300_VRC4373 - - requires CYGPKG_ERROR - include_dir cyg/io - include_files ; # none _exported_ whatsoever - description " - This option enables the serial device drivers for the - VRC4373." - doc redirect/ecos-device-drivers.html - - compile -library=libextras.a vrc4373_serial.c - - define_proc { - puts $::cdl_system_header "/***** serial driver proc output start *****/" - puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_vrc4373.h>" - puts $::cdl_system_header "/***** serial driver proc output end *****/" - } - -cdl_component CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 { - display "VRC4373 serial port 0 driver" - flavor bool - default_value 1 - description " - This option includes the serial device driver for the VRC4373 port 0." - - cdl_option CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME { - display "Device name for the VRC4373 serial port 0 driver" - flavor data - default_value {"\"/dev/ser0\""} - description " - This option sets the name of the serial device for the VRC4373 - port 0." - } - - cdl_option CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD { - display "Baud rate for the VRC4373 serial port 0 driver" - flavor data - legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 - } - default_value 9600 - description " - This option specifies the default baud rate (speed) for the - VRC4373 port 0." - } - - cdl_option CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE { - display "Buffer size for the VRC4373 serial port 0 driver" - flavor data - legal_values 0 to 8192 - default_value 128 - description " - This option specifies the size of the internal buffers used - for the VRC4373 port 0." - } -} -cdl_component CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 { - display "VRC4373 serial port 1 driver" - flavor bool - default_value 1 - description " - This option includes the serial device driver for the VRC4373 port 1." - - cdl_option CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL1_NAME { - display "Device name for the VRC4373 serial port 1 driver" - flavor data - default_value {"\"/dev/ser1\""} - description " - This option specifies the name of serial device for the - VRC4373 port 1." - } - - cdl_option CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD { - display "Baud rate for the VRC4373 serial port 1 driver" - flavor data - legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 - } - default_value 9600 - description " - This option specifies the default baud rate (speed) for the - VRC4373 port 1." - } - - cdl_option CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE { - display "Buffer size for the VRC4373 serial port 1 driver" - flavor data - legal_values 0 to 8192 - default_value 128 - description " - This option specifies the size of the internal buffers used for - the VRC4373 port 1." - } -} - - cdl_component CYGPKG_IO_SERIAL_MIPS_VRC4373_OPTIONS { - display "Serial device driver build options" - flavor none - description " - Package specific build options including control over - compiler flags used only in building this package, - and details of which tests are built." - - - cdl_option CYGPKG_IO_SERIAL_MIPS_VRC4373_CFLAGS_ADD { - display "Additional compiler flags" - flavor data - no_define - default_value { "" } - description " - This option modifies the set of compiler flags for - building these serial device drivers. These flags are used in addition - to the set of global flags." - } - - cdl_option CYGPKG_IO_SERIAL_MIPS_VRC4373_CFLAGS_REMOVE { - display "Suppressed compiler flags" - flavor data - no_define - default_value { "" } - description " - This option modifies the set of compiler flags for - building these serial device drivers. These flags are removed from - the set of global flags if present." - } - } - - cdl_component CYGPKG_IO_SERIAL_MIPS_VRC4373_TESTING { - display "Testing parameters" - flavor bool - calculated 1 - active_if CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 - - cdl_option CYGPRI_SER_TEST_SER_DEV { - display "Serial device used for testing" - flavor data - default_value { CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME } - } - - define_proc { - puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"vrc4373\"" - puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" - } - } -} - -# EOF ser_mips_vrc4373.cdl
deleted file mode 100644 --- a/packages/devs/serial/mips/vrc4373/current/src/vrc4373_serial.c +++ /dev/null @@ -1,485 +0,0 @@ -//========================================================================== -// -// io/serial/mips/vrc4373_serial.c -// -// Mips VRC4373 Serial I/O Interface Module (interrupt driven) -// -//========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): gthomas -// Contributors: gthomas -// Date: 1999-04-15 -// Purpose: VRC4373 Serial I/O module (interrupt driven version) -// Description: -// -//####DESCRIPTIONEND#### -// -//========================================================================== - -#include <pkgconf/system.h> -#include <pkgconf/io_serial.h> -#include <pkgconf/io.h> -#include <cyg/io/io.h> -#include <cyg/hal/hal_intr.h> -#include <cyg/io/devtab.h> -#include <cyg/io/serial.h> - -#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373 - -#include "vrc4373_serial.h" - -#if defined(CYGPKG_HAL_MIPS_LSBFIRST) -#define VRC4373_SCC_BASE 0xC1000000 -#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) -#define VRC4373_SCC_BASE 0xC1000003 -#else -#error MIPS endianness not defined by configuration -#endif - -#define VRC4373_SCC_INT CYGNUM_HAL_INTERRUPT_DUART -#define SCC_CHANNEL_A 4 -#define SCC_CHANNEL_B 0 - -extern void diag_printf(const char *fmt, ...); - -typedef struct vrc4373_serial_info { - CYG_ADDRWORD base; - unsigned char regs[16]; // Known register state (since hardware is write-only!) -} vrc4373_serial_info; - -static bool vrc4373_serial_init(struct cyg_devtab_entry *tab); -static bool vrc4373_serial_putc(serial_channel *chan, unsigned char c); -static Cyg_ErrNo vrc4373_serial_lookup(struct cyg_devtab_entry **tab, - struct cyg_devtab_entry *sub_tab, - const char *name); -static unsigned char vrc4373_serial_getc(serial_channel *chan); -static Cyg_ErrNo vrc4373_serial_set_config(serial_channel *chan, cyg_uint32 key, - const void *xbuf, cyg_uint32 *len); -static void vrc4373_serial_start_xmit(serial_channel *chan); -static void vrc4373_serial_stop_xmit(serial_channel *chan); - -static cyg_uint32 vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); -static void vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); - -static SERIAL_FUNS(vrc4373_serial_funs, - vrc4373_serial_putc, - vrc4373_serial_getc, - vrc4373_serial_set_config, - vrc4373_serial_start_xmit, - vrc4373_serial_stop_xmit - ); - -#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 -static vrc4373_serial_info vrc4373_serial_info0 = {VRC4373_SCC_BASE+SCC_CHANNEL_A}; -#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE > 0 -static unsigned char vrc4373_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE]; -static unsigned char vrc4373_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE]; - -static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel0, - vrc4373_serial_funs, - vrc4373_serial_info0, - CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), - CYG_SERIAL_STOP_DEFAULT, - CYG_SERIAL_PARITY_DEFAULT, - CYG_SERIAL_WORD_LENGTH_DEFAULT, - CYG_SERIAL_FLAGS_DEFAULT, - &vrc4373_serial_out_buf0[0], sizeof(vrc4373_serial_out_buf0), - &vrc4373_serial_in_buf0[0], sizeof(vrc4373_serial_in_buf0) - ); -#else -static SERIAL_CHANNEL(vrc4373_serial_channel0, - vrc4373_serial_funs, - vrc4373_serial_info0, - CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), - CYG_SERIAL_STOP_DEFAULT, - CYG_SERIAL_PARITY_DEFAULT, - CYG_SERIAL_WORD_LENGTH_DEFAULT, - CYG_SERIAL_FLAGS_DEFAULT - ); -#endif - -DEVTAB_ENTRY(vrc4373_serial_io0, - CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME, - 0, // Does not depend on a lower level interface - &cyg_io_serial_devio, - vrc4373_serial_init, - vrc4373_serial_lookup, // Serial driver may need initializing - &vrc4373_serial_channel0 - ); -#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 - -#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 -static vrc4373_serial_info vrc4373_serial_info1 = {VRC4373_SCC_BASE+SCC_CHANNEL_B}; -#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE > 0 -static unsigned char vrc4373_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE]; -static unsigned char vrc4373_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE]; - -static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel1, - vrc4373_serial_funs, - vrc4373_serial_info1, - CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), - CYG_SERIAL_STOP_DEFAULT, - CYG_SERIAL_PARITY_DEFAULT, - CYG_SERIAL_WORD_LENGTH_DEFAULT, - CYG_SERIAL_FLAGS_DEFAULT, - &vrc4373_serial_out_buf1[0], sizeof(vrc4373_serial_out_buf1), - &vrc4373_serial_in_buf1[0], sizeof(vrc4373_serial_in_buf1) - ); -#else -static SERIAL_CHANNEL(vrc4373_serial_channel1, - vrc4373_serial_funs, - vrc4373_serial_info1, - CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), - CYG_SERIAL_STOP_DEFAULT, - CYG_SERIAL_PARITY_DEFAULT, - CYG_SERIAL_WORD_LENGTH_DEFAULT, - CYG_SERIAL_FLAGS_DEFAULT - ); -#endif - -DEVTAB_ENTRY(vrc4373_serial_io1, - CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL1_NAME, - 0, // Does not depend on a lower level interface - &cyg_io_serial_devio, - vrc4373_serial_init, - vrc4373_serial_lookup, // Serial driver may need initializing - &vrc4373_serial_channel1 - ); -#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 - -static cyg_interrupt vrc4373_serial_interrupt; -static cyg_handle_t vrc4373_serial_interrupt_handle; - -// Table which maps hardware channels (A,B) to software ones -struct serial_channel *vrc4373_chans[] = { -#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 // Hardware channel A - &vrc4373_serial_channel0, -#else - 0, -#endif -#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 // Hardware channel B - &vrc4373_serial_channel1, -#else - 0, -#endif -}; - -// Support functions which access the serial device. Note that this chip requires -// a substantial delay after each access. - -#define SCC_DELAY 100 -inline static void -scc_delay(void) -{ - int i; - for (i = 0; i < SCC_DELAY; i++) ; -} - -inline static void -scc_write_reg(volatile unsigned char *reg, unsigned char val) -{ - scc_delay(); - *reg = val; -} - -inline static unsigned char -scc_read_reg(volatile unsigned char *reg) -{ - unsigned char val; - scc_delay(); - val = *reg; - return (val); -} - -inline static unsigned char -scc_read_ctl(volatile struct serial_port *port, int reg) -{ - if (reg != 0) { - scc_write_reg(&port->scc_ctl, reg); - } - return (scc_read_reg(&port->scc_ctl)); -} - -inline static void -scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val) -{ - if (reg != 0) { - scc_write_reg(&port->scc_ctl, reg); - } - scc_write_reg(&port->scc_ctl, val); -} - -inline static unsigned char -scc_read_dat(volatile struct serial_port *port) -{ - return (scc_read_reg(&port->scc_dat)); -} - -inline static void -scc_write_dat(volatile struct serial_port *port, unsigned char val) -{ - scc_write_reg(&port->scc_dat, val); -} - -// Internal function to actually configure the hardware to desired baud rate, etc. -static bool -vrc4373_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) -{ - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - cyg_int32 baud_rate = select_baud[new_config->baud]; - cyg_int32 baud_divisor; - unsigned char *regs = &vrc4373_chan->regs[0]; - if (baud_rate == 0) return false; - // Compute state of registers. The register/control state needs to be kept in - // the shadow variable 'regs' because the hardware registers can only be written, - // not read (in general). - if (init) { - // Insert appropriate resets? - if (chan->out_cbuf.len != 0) { - regs[R1] = WR1_IntAllRx; - regs[R9] = WR9_MIE | WR9_NoVector; - } else { - regs[R1] = 0; - regs[R9] = 0; - } - // Clocks are from the baud rate generator - regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR; - regs[R14] = WR14_BRenable | WR14_BRSRC; - regs[R10] = 0; // Unused in this [async] mode - regs[R15] = 0; - } - regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; - regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity]; - regs[R5] = WR5_TxEnable | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; - baud_divisor = BRTC(baud_rate); - regs[R12] = baud_divisor & 0xFF; - regs[R13] = baud_divisor >> 8; - // Now load the registers - scc_write_ctl(port, R4, regs[R4]); - scc_write_ctl(port, R10, regs[R10]); - scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable); - scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable); - scc_write_ctl(port, R1, regs[R1]); - scc_write_ctl(port, R9, regs[R9]); - scc_write_ctl(port, R11, regs[R11]); - scc_write_ctl(port, R12, regs[R12]); - scc_write_ctl(port, R13, regs[R13]); - scc_write_ctl(port, R14, regs[R14]); - scc_write_ctl(port, R15, regs[R15]); - scc_write_ctl(port, R3, regs[R3]); - scc_write_ctl(port, R5, regs[R5]); - // Update configuration - if (new_config != &chan->config) { - chan->config = *new_config; - } - return true; -} - -// Function to initialize the device. Called at bootstrap time. -static bool -vrc4373_serial_init(struct cyg_devtab_entry *tab) -{ - serial_channel *chan = (serial_channel *)tab->priv; - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - static bool init = false; -#ifdef CYGDBG_IO_INIT - diag_printf("VRC4373 SERIAL init '%s' - dev: %x\n", tab->name, vrc4373_chan->base); -#endif - (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices - if (!init && chan->out_cbuf.len != 0) { - init = true; -// Note that the hardware is rather broken. The interrupt status needs to -// be read using only channel A - cyg_drv_interrupt_create(VRC4373_SCC_INT, - 99, - (cyg_addrword_t)VRC4373_SCC_BASE+SCC_CHANNEL_A, - vrc4373_serial_ISR, - vrc4373_serial_DSR, - &vrc4373_serial_interrupt_handle, - &vrc4373_serial_interrupt); - cyg_drv_interrupt_attach(vrc4373_serial_interrupt_handle); - cyg_drv_interrupt_unmask(VRC4373_SCC_INT); - } - vrc4373_serial_config_port(chan, &chan->config, true); - return true; -} - -// This routine is called when the device is "looked" up (i.e. attached) -static Cyg_ErrNo -vrc4373_serial_lookup(struct cyg_devtab_entry **tab, - struct cyg_devtab_entry *sub_tab, - const char *name) -{ - serial_channel *chan = (serial_channel *)(*tab)->priv; - (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices - return ENOERR; -} - -// Send a character to the device output buffer. -// Return 'true' if character is sent to device -static bool -vrc4373_serial_putc(serial_channel *chan, unsigned char c) -{ - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - if (scc_read_ctl(port, R0) & RR0_TxEmpty) { -// Transmit buffer is empty - scc_write_dat(port, c); - return true; - } else { -// No space - return false; - } -} - -// Fetch a character from the device input buffer, waiting if necessary -static unsigned char -vrc4373_serial_getc(serial_channel *chan) -{ - unsigned char c; - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ; // Wait for char - c = scc_read_dat(port); - return c; -} - -// Set up the device characteristics; baud rate, etc. -static Cyg_ErrNo -vrc4373_serial_set_config(serial_channel *chan, cyg_uint32 key, - const void *xbuf, cyg_uint32 *len) -{ - switch (key) { - case CYG_IO_SET_CONFIG_SERIAL_INFO: - { - cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; - if ( *len < sizeof(cyg_serial_info_t) ) { - return -EINVAL; - } - *len = sizeof(cyg_serial_info_t); - if ( true != vrc4373_serial_config_port(chan, config, false) ) - return -EINVAL; - } - break; - default: - return -EINVAL; - } - return ENOERR; -} - -// Enable the transmitter on the device -static void -vrc4373_serial_start_xmit(serial_channel *chan) -{ - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) == 0) { - CYG_INTERRUPT_STATE old; - HAL_DISABLE_INTERRUPTS(old); - vrc4373_chan->regs[R1] |= WR1_TxIntEnab; // Enable Tx interrupt - scc_write_ctl(port, R1, vrc4373_chan->regs[R1]); - (chan->callbacks->xmt_char)(chan); // Send first character to start xmitter - HAL_RESTORE_INTERRUPTS(old); - } -} - -// Disable the transmitter on the device -static void -vrc4373_serial_stop_xmit(serial_channel *chan) -{ - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) != 0) { - CYG_INTERRUPT_STATE old; - HAL_DISABLE_INTERRUPTS(old); - vrc4373_chan->regs[R1] &= ~WR1_TxIntEnab; // Disable Tx interrupt - scc_write_ctl(port, R1, vrc4373_chan->regs[R1]); - HAL_RESTORE_INTERRUPTS(old); - } -} - -// Serial I/O - low level interrupt handler (ISR) -static cyg_uint32 -vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) -{ - cyg_drv_interrupt_mask(VRC4373_SCC_INT); - cyg_drv_interrupt_acknowledge(VRC4373_SCC_INT); - return CYG_ISR_CALL_DSR; // Cause DSR to be run -} - -inline static void -vrc4373_int(serial_channel *chan, unsigned char stat) -{ - vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; - volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; - // Note: 'stat' value is interrupt status register, shifted into "B" position - if (stat & RR3_BRxIP) { - // Receive interrupt - unsigned char c; - c = scc_read_dat(port); - (chan->callbacks->rcv_char)(chan, c); - } - if (stat & RR3_BTxIP) { - // Transmit interrupt - (chan->callbacks->xmt_char)(chan); - } - if (stat & RR3_BExt) { - // Status interrupt (parity error, framing error, etc) - } -} - -// Serial I/O - high level interrupt handler (DSR) -// Note: This device presents a single interrupt for both channels. Thus the -// interrupt handler has to query the device and decide which channel needs service. -// Additionally, more than one interrupt condition may be present so this needs to -// be done in a loop until all interrupt requests have been handled. -// Also note that the hardware is rather broken. The interrupt status needs to -// be read using only channel A (pointed to by 'data') -static void -vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) -{ - serial_channel *chan; - volatile struct serial_port *port = (volatile struct serial_port *)data; - unsigned char stat; - while (true) { - stat = scc_read_ctl(port, R3); - if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) { - chan = vrc4373_chans[0]; // Hardware channel A - vrc4373_int(chan, stat>>3); // Handle interrupt - } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) { - chan = vrc4373_chans[1]; // Hardware channel B - vrc4373_int(chan, stat); // Handle interrupt - } else { - // No more interrupts, all done - break; - } - } - cyg_drv_interrupt_unmask(VRC4373_SCC_INT); -} -#endif
deleted file mode 100644 --- a/packages/devs/serial/mips/vrc4373/current/src/vrc4373_serial.h +++ /dev/null @@ -1,335 +0,0 @@ -#ifndef CYGONCE_MIPS_VRC4373_SERIAL_H -#define CYGONCE_MIPS_VRC4373_SERIAL_H - -// ==================================================================== -// -// aeb_serial.h -// -// Device I/O - Description of Mips VRC4373 serial hardware -// -// ==================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -// ==================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): gthomas -// Contributors: gthomas -// Date: 1999-04-15 -// Purpose: Internal interfaces for serial I/O drivers -// Description: -// -//####DESCRIPTIONEND#### -// -// ==================================================================== - -// Description of serial ports on Mips VRC4373 -// Based on Zilog 85C30 SCC - -struct serial_port { - unsigned char _byte[16]; -}; - -#define scc_ctl _byte[0] -#define scc_dat _byte[8] - -#define R0 0 /* Register selects */ -#define R1 1 -#define R2 2 -#define R3 3 -#define R4 4 -#define R5 5 -#define R6 6 -#define R7 7 -#define R8 8 -#define R9 9 -#define R10 10 -#define R11 11 -#define R12 12 -#define R13 13 -#define R14 14 -#define R15 15 - -/* Write Register 0 */ -#define WR0_NullCode 0x00 /* Null Code */ -#define WR0_PointHigh 0x08 /* Select upper half of registers */ -#define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */ -#define WR0_SendAbort 0x18 /* HDLC Abort */ -#define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */ -#define WR0_ResTxP 0x28 /* Reset TxINT Pending */ -#define WR0_ErrReset 0x30 /* Error Reset */ -#define WR0_ResHiIUS 0x38 /* Reset highest IUS */ - -#define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */ -#define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */ -#define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */ - -/* Write Register 1 */ - -#define WR1_ExtIntEnab 0x01 /* Ext Int Enable */ -#define WR1_TxIntEnab 0x02 /* Tx Int Enable */ -#define WR1_ParSpec 0x04 /* Parity is special condition */ - -#define WR1_RxIntDisab 0x00 /* Rx Int Disable */ -#define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */ -#define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */ -#define WR1_IntErrRx 0x18 /* Int on error only */ - -#define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */ -#define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */ -#define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */ - -/* Write Register #2 (Interrupt Vector) */ - -/* Write Register 3 */ - -#define WR3_RxEnable 0x01 /* Rx Enable */ -#define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */ -#define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */ -#define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */ -#define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */ -#define WR3_AutoEnab 0x20 /* Auto Enables */ -#define WR3_Rx5 0x00 /* Rx 5 Bits/Character */ -#define WR3_Rx7 0x40 /* Rx 7 Bits/Character */ -#define WR3_Rx6 0x80 /* Rx 6 Bits/Character */ -#define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */ -#define WR3_RxNbitsMask 0xc0 - -/* Write Register 4 */ - -#define WR4_ParityEn 0x01 /* Parity Enable */ -#define WR4_ParityEven 0x02 /* Parity Even/Odd* */ - -#define WR4_SyncEnable 0x00 /* Sync Modes Enable */ -#define WR4_SB1 0x04 /* 1 stop bit/char */ -#define WR4_SB15 0x08 /* 1.5 stop bits/char */ -#define WR4_SB2 0x0c /* 2 stop bits/char */ -#define WR4_SB_MASK 0x0c - -#define WR4_Monsync 0x00 /* 8 Bit Sync character */ -#define WR4_Bisync 0x10 /* 16 bit sync character */ -#define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ -#define WR4_EXtSync 0x30 /* External Sync Mode */ - -#define WR4_X1CLK 0x00 /* x1 clock mode */ -#define WR4_X16CLK 0x40 /* x16 clock mode */ -#define WR4_X32CLK 0x80 /* x32 clock mode */ -#define WR4_X64CLK 0xC0 /* x64 clock mode */ -#define WR4_XCLK_MASK 0xC0 - -/* Write Register 5 */ - -#define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */ -#define WR5_RTS 0x02 /* RTS */ -#define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */ -#define WR5_TxEnable 0x08 /* Tx Enable */ -#define WR5_SendBreak 0x10 /* Send Break */ -#define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */ -#define WR5_Tx7 0x20 /* Tx 7 bits/character */ -#define WR5_Tx6 0x40 /* Tx 6 bits/character */ -#define WR5_Tx8 0x60 /* Tx 8 bits/character */ -#define WR5_TxNbitsMask 0x60 -#define WR5_DTR 0x80 /* DTR */ - -/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ - -/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ - -/* Write Register 8 (transmit buffer) */ - -/* Write Register 9 (Master interrupt control) */ -#define WR9_VIS 0x01 /* Vector Includes Status */ -#define WR9_NoVector 0x02 /* No Vector */ -#define WR9_DLC 0x04 /* Disable Lower Chain */ -#define WR9_MIE 0x08 /* Master Interrupt Enable */ -#define WR9_StatHi 0x10 /* Status high */ -#define WR9_NoReset 0x00 /* No reset on write to R9 */ -#define WR9_ResetB 0x40 /* Reset channel B */ -#define WR9_ResetA 0x80 /* Reset channel A */ -#define WR9_HwReset 0xc0 /* Force hardware reset */ - -/* Write Register 10 (misc control bits) */ -#define WR10_Bit6 0x01 /* 6 bit/8bit sync */ -#define WR10_LoopMode 0x02 /* SDLC Loop mode */ -#define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */ -#define WR10_MarkIdle 0x08 /* Mark/flag on idle */ -#define WR10_GAOP 0x10 /* Go active on poll */ -#define WR10_NRZ 0x00 /* NRZ mode */ -#define WR10_NRZI 0x20 /* NRZI mode */ -#define WR10_FM1 0x40 /* FM1 (transition = 1) */ -#define WR10_FM0 0x60 /* FM0 (transition = 0) */ -#define WR10_CRCPS 0x80 /* CRC Preset I/O */ - -/* Write Register 11 (Clock Mode control) */ -#define WR11_TRxCXT 0x00 /* TRxC = Xtal output */ -#define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */ -#define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */ -#define WR11_TRxCDP 0x03 /* TRxC = DPLL output */ -#define WR11_TRxCOI 0x04 /* TRxC O/I */ -#define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */ -#define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */ -#define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */ -#define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */ -#define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */ -#define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */ -#define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */ -#define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */ -#define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */ - -/* Write Register 12 (lower byte of baud rate generator time constant) */ - -/* Write Register 13 (upper byte of baud rate generator time constant) */ - -/* Write Register 14 (Misc control bits) */ -#define WR14_BRenable 0x01 /* Baud rate generator enable */ -#define WR14_BRSRC 0x02 /* Baud rate generator source */ -#define WR14_DTRreq 0x04 /* DTR/Request function */ -#define WR14_AutoEcho 0x08 /* Auto Echo */ -#define WR14_LoopBack 0x10 /* Local loopback */ -#define WR14_Search 0x20 /* Enter search mode */ -#define WR14_RMC 0x40 /* Reset missing clock */ -#define WR14_NoDPLL 0x60 /* Disable DPLL */ -#define WR14_SSBR 0x80 /* Set DPLL source = BR generator */ -#define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */ -#define WR14_SFMM 0xc0 /* Set FM mode */ -#define WR14_SNRZI 0xe0 /* Set NRZI mode */ - -/* Write Register 15 (external/status interrupt control) */ -#define WR15_ZCIE 0x02 /* Zero count IE */ -#define WR15_DCDIE 0x08 /* DCD IE */ -#define WR15_SYNCIE 0x10 /* Sync/hunt IE */ -#define WR15_CTSIE 0x20 /* CTS IE */ -#define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */ -#define WR15_BRKIE 0x80 /* Break/Abort IE */ - -/* Read Register 0 */ -#define RR0_RxAvail 0x01 /* Rx Character Available */ -#define RR0_Zcount 0x02 /* Zero count */ -#define RR0_TxEmpty 0x04 /* Tx Buffer empty */ -#define RR0_DCD 0x08 /* DCD */ -#define RR0_SyncHunt 0x10 /* Sync/hunt */ -#define RR0_CTS 0x20 /* CTS */ -#define RR0_TxEOM 0x40 /* Tx underrun */ -#define RR0_BrkAbort 0x80 /* Break/Abort */ - -/* Read Register 1 */ -#define RR1_AllSent 0x01 /* All sent */ -/* Residue Data for 8 Rx bits/char programmed */ -#define RR1_RES3 0x08 /* 0/3 */ -#define RR1_RES4 0x04 /* 0/4 */ -#define RR1_RES5 0x0c /* 0/5 */ -#define RR1_RES6 0x02 /* 0/6 */ -#define RR1_RES7 0x0a /* 0/7 */ -#define RR1_RES8 0x06 /* 0/8 */ -#define RR1_RES18 0x0e /* 1/8 */ -#define RR1_RES28 0x00 /* 2/8 */ -/* Special Rx Condition Interrupts */ -#define RR1_PariryError 0x10 /* Parity error */ -#define RR1_RxOverrun 0x20 /* Rx Overrun Error */ -#define RR1_FrameError 0x40 /* CRC/Framing Error */ -#define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */ - -/* Read Register 2 (channel b only) - Interrupt vector */ - -/* Read Register 3 (interrupt pending register) ch a only */ -#define RR3_BExt 0x01 /* Channel B Ext/Stat IP */ -#define RR3_BTxIP 0x02 /* Channel B Tx IP */ -#define RR3_BRxIP 0x04 /* Channel B Rx IP */ -#define RR3_AExt 0x08 /* Channel A Ext/Stat IP */ -#define RR3_ATxIP 0x10 /* Channel A Tx IP */ -#define RR3_ARxIP 0x20 /* Channel A Rx IP */ - -/* Read Register 8 (receive data register) */ - -/* Read Register 10 (misc status bits) */ -#define RR10_OnLoop 0x02 /* On loop */ -#define RR10_LoopSend 0x10 /* Loop sending */ -#define RR10_Clk2Mis 0x40 /* Two clocks missing */ -#define RR10_Clk1Mis 0x80 /* One clock missing */ - -/* Read Register 12 (lower byte of baud rate generator constant) */ - -/* Read Register 13 (upper byte of baud rate generator constant) */ - -/* Read Register 15 (value of WR 15) */ - -#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) -#define DUART_CLOCK 4915200 /* Z8530 duart */ -#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ - -static unsigned char select_word_length_WR3[] = { - WR3_Rx5, // 5 bits / word (char) - WR3_Rx6, - WR3_Rx7, - WR3_Rx8 -}; - -static unsigned char select_word_length_WR5[] = { - WR5_Tx5, // 5 bits / word (char) - WR5_Tx6, - WR5_Tx7, - WR5_Tx8 -}; - -static unsigned char select_stop_bits[] = { - 0, - WR4_SB1, // 1 stop bit - WR4_SB15, // 1.5 stop bit - WR4_SB2 // 2 stop bits -}; - -static unsigned char select_parity[] = { - 0, // No parity - WR4_ParityEn | WR4_ParityEven, // Even parity - WR4_ParityEn, // Odd parity - 0xFF, // Mark parity - 0xFF, // Space parity -}; - -static cyg_int32 select_baud[] = { - 0, // Unused - 50, // 50 - 75, // 75 - 110, // 110 - 0, // 134.5 - 150, // 150 - 200, // 200 - 300, // 300 - 600, // 600 - 1200, // 1200 - 1800, // 1800 - 2400, // 2400 - 3600, // 3600 - 4800, // 4800 - 7200, // 7200 - 9600, // 9600 - 14400, // 14400 - 19200, // 19200 - 38400, // 38400 - 0, // 57600 - 0, // 115200 - 0, // 230400 -}; - -#endif // CYGONCE_MIPS_VRC4373_SERIAL_H
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/vrc437x/current/ChangeLog @@ -0,0 +1,1196 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + Fix 234000->230400 typo. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * cdl/ser_mips_vrc437x.cdl: + * src/vrc437x_serial.h: + * src/vrc437x_serial.c: + Moved this entire tree over to vrc437x from vrc4373 to make it + generic to both kinds of board. + +2000-10-12 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_vrc4373.cdl: Moved testing parameters here. + +2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_set_config): Now use keys + to make more flexible. + +2000-07-22 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/vrc4373_serial.c (vrc4373_serial_init): Add comment about broken + interrupt handling + +2000-06-22 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/<yournamehere>.cdl: Remove the comment on the empty + include_files directive; the tools now support this correctly. + This keeps internal include files internal. + +2000-04-11 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ser_mips_vrc4373.cdl: Change the parent from CYGPKG_IO_SERIAL + (which is enabled most of the time) to CYGPKG_IO_SERIAL_DEVICES + (which is not...) thus allowing convenient control independent of + platform. Also enable all individual devices by default, now, so + that they can be enabled simply by enabling the above new parent. + +2000-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * ecos.db: Re-organize device packages. This is a massive change + involving deleting all the sources for serial and ethernet drivers + from where they used to live in + packages/io/serial/current/src/ARCH/PLATFORM.[ch] + packages/net/drivers/eth/PLATFORM/current/src/... + and reinstating them in + packages/devs/serial/ARCH/PLATFORM/current/src/... + packages/devs/eth/ARCH/PLATFORM/current/src/... + + All these new packages are properly defined in ecos.db, and are + all of type "hardware" so that a "target" can grab them. + + This directory layout is descriptive of the devices we have right + now, arch and platform are separate levels just to make it easier + to navigate in the filesystem and similar to the HAL structure in + the filesystem. + + It is *not* prescriptive of future work; for example, the mythical + common highly-portable 16550 serial driver which works on many + targets would be called "devs/serial/s16550/current", or a serial + device for a particular board (cogent springs to mind) that can + work with different CPUs fitted is "devs/serial/cogent/current". + + Changelogs have been preserved and replicated over all the new + packages, so that no history is lost. + + The contents of individual source files are unchanged; they build + in just the same emvironment except for a very few cases where the + config file name changed in this movement. + + Targets in ecos.db have been redefined to bring in all relevant + hardware packages including net and serial drivers (but the newly + included packages are only active if their desired parent is + available.) + + The names of CDL options (and their #defines of course) stay the + same for the serial drivers, for backward compatibility. + + * templates/*/current.ect: these have had CYGPKG_IO_SERIAL added + rather than it being in (almost) all target definitions. + +2000-04-05 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/common/tty.c (tty_read): CRLF conversion should use \r\n not \n\r + (tty_write): Similarly + + * include/ttyio.h: Update CYG_TTY_IN_FLAGS_CRLF and + CYG_TTY_IN_FLAGS_CRLF to match + +2000-03-31 Jesper Skov <jskov@redhat.com> + + * cdl/ser_sh_edk7708.cdl: Limit legal baud rate range. + * src/sh/sh_sci_serial.c: Use baud rate macro instead of hardwired + constants. + +2000-03-28 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl, + cdl/ser_arm_aeb.cdl, + cdl/ser_arm_cma230.cdl, + cdl/ser_arm_edb7xxx.cdl, + cdl/ser_arm_pid.cdl, + cdl/ser_i386_pc.cdl, + cdl/ser_mips_jmr3904.cdl, + cdl/ser_mips_vrc4373.cdl, + cdl/ser_mn10300.cdl, + cdl/ser_powerpc_cogent.cdl, + cdl/ser_quicc_smc.cdl, + cdl/ser_sh_edk7708.cdl, + cdl/ser_sparclite_sleb.cdl, + cdl/tty.cdl: + + Adjust documentation URLs. + +2000-03-07 Jesper Skov <jskov@redhat.com> + + * cdl/ser_mips_jmr3904.cdl: Rename devices to match CDL naming. + +2000-02-29 Jonathan Larmour <jlarmour@redhat.co.uk> + + * include/serialio.h: Correct baud rate typo: 230400 rather than + 234000. Thanks to Grant Edwards for the report. + +2000-02-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Use standard 'diag_dump_buf()'. + +2000-02-28 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Allow 115200 baud on Cogent + again. Fixed interrupt problem. + +2000-02-22 Jesper Skov <jskov@redhat.com> + + * tests/ser_test_protocol.inl: Don't use 115200 baud on + Cogent. Our slower boards can't keep up. + +2000-02-17 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/ser_powerpc_cogent.cdl: Fix incorrect dependency. + +2000-02-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Added configury for PC serial device drivers. + + * cdl/ser_i386_pc.cdl: + * src/i386/pc_serial.c: + * src/i386/pc_serial.h: + Added these files to implement PC serial line drivers. + + * cdl/io_serial.cdl: + Added CYGPKG_IO_SERIAL_I386_PC. + + * tests/ser_test_protocol.inl: + Added support for PC serial line testing. + +2000-02-11 Jesper Skov <jskov@redhat.com> + + * src/sh/sh_sci_7708.inl (DEVTAB_ENTRY): + * src/sparclite/sleb_sdtr.c: + serial_devio => cyg_io_serial_devio + +2000-02-10 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/mn10300/mn10300_serial.c: Ensure all CYG_HAL_MN10300_* + preprocessor conditionals use the correct CYGPKG_HAL_MN10300_AM3* form + now. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * src/powerpc/quicc_smc_serial.c: CYG_HAL_POWERPC_x->CYGPKG_... + +2000-02-02 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/arm/aeb_serial.h: Rename lower case register macros to REG_ upper + case macros + + * src/arm/aeb_serial.c: Update to reflect above + +2000-01-31 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Simon FitzMaurice <sdf@cygnus.co.uk> + * cdl/*.cdl: + + Adjust help URLs in line with new doc layout. + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Fix problem with backspace at start + of line (size must be 'signed' for compare to work). + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +2000-01-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/tty.c (tty_read): Avoid echoing "backspace/erase" at + start of line. + +2000-01-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c (serial_write): Avoid potential deadlock if + transmit start actually sends enough characters to signal cond wait. + +2000-01-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + serial_callbacks => cyg_io_serial_callbacks + + * src/mips/tx3904_serial.c: + * src/mips/vrc4373_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/quicc_smc_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/edb7xxx_serial.c: + * src/arm/cma230_serial.c: + * src/arm/ebsa285_serial.c: + * src/common/haldiag.c: + * src/common/serial.c: Fix namespace pollution - + serial_devio => cyg_io_serial_devio + +1999-12-06 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Add loop to handle + case where an interrupt represents multiple events. + +1999-11-19 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c: Channel select for SMC2 was wrong. + +1999-11-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Remove mention of 7209/7212. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/io_serial.cdl: Define build options. + +1999-10-26 Jesper Skov <jskov@cygnus.co.uk> + * tests/serial5.c (serial_test): Reduce speed in thumb mode. + + * src/arm/pid_serial.h: Added BE support. + + * src/PKGconf.mak: Use CYGPKG_<> instead of CYG_<> to control what + needs to be compiled. + +1999-10-25 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial.h (ISR_RxTO): Define - character received but + not handled "promptly". + + * src/arm/pid_serial_with_ints.c (pid_serial_DSR): Handle rcv interrupts + properly (can't ignore them even with TO bit set). + + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Need to handle all + input (empty input FIFO) otherwise characters get dropped. + +1999-10-15 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed AEB rev C change. Was bogus. + +1999-10-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added configury for VR4300 testing. + + * src/mips/vrc4373_serial.c: Added Bi-endian support. + + * include/pkgconf/io_serial.h: Adjusted default baud rates to + 38400. + +1999-10-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Run tests on AEB rev C as well. + +1999-09-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): Correct + value supplied for interrupt priority - it may be unused, but it + is asserted for range. Initialize the diagnostic channel if on an + MBX and if NOT using SMC1 ourselves, to ensure that diag output + and built-in stubs work correctly; otherwise reset the quicc and + ignore SMC1 as before. Fix various warnings, mostly about + casting/arg-passing/assigning away volatile. + +1999-08-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Define dummy crash ID. + +1999-08-30 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added crash information which + should help track down repeating errors. + +1999-08-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/README: Added. + +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + +1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mn10300/mn10300_serial.c: + * tests/ser_test_protocol.inl: + Rename all am32 -> am31 + +1999-08-12 Nick Garnett <nickg@cygnus.co.uk> + + Imported following changes from development branch: + + 1999-08-11 Nick Garnett <nickg@cygnus.co.uk> + + * tests/serial5.c: Modified config test for boards that need a lower + speed for this test. + + * tests/ser_test_protocol.inl: Removed 14400 baud tests for all + MN10300 variants. The MN10300 cannot currently do this speed. + + * src/mn10300/mn10300_serial.c: Tidied up the transmit interrupt + enable/disable code to be variant specific. + + * include/pkgconf/io_serial.h: Undid Jonathan's change, since the + same options are used for all MN10300 variants. + + 1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to + CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific + + 1999-08-04 Nick Garnett <nickg@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Changed names of MN10300 defines tested. Added AM33 definitions. + + * src/mn10300/mn10300_serial.c: + Modified driver to work on am33 too. This simply requires some + alternate definitions of things like register addresses and some + bits in them plus some extra parameterization of some register + values. + + * src/PKGconf.mak: + Added am33 to list of architectures supporting serial lines. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + +1999-07-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/arm/ebsa285_serial.c: New file: device driver for the serial + device of the Intel StrongARM EBSA-285 evaluation board. + + * include/pkgconf/io_serial.h (CYGPKG_IO_SERIAL_ARM_EBSA285): + Config for it. + + * src/PKGconf.mak (EXTRAS_COMPILE): Compile it. + + * tests/ser_test_protocol.inl (TEST_SER_DEV): Enable testing of it. + +1999-07-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl (change_config): Changed implementation. + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_sci_serial.c: Rearranged inclusion of .inl file a bit + to avoid compiler warnings. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + +1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Some clean up (removed commented + obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + + * src/arm/cma230_serial.c: + * src/arm/cl7211_serial.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' + prototypes. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + +1999-06-16 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: [removed] + * src/sh/sh_sci_serial.c: [added] + * src/sh/sh_sci_7708.inl: [added] + * include/pkgconf/io_serial.h: + * src/PKGconf.mak (EXTRAS_COMPILE): + * tests/ser_test_protocol.inl: + Renamed CDL options and restructered driver. + Fixed CDL typo. + +1999-06-04 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fixed CDL string for BAUD rate option. + +1999-06-04 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Disable testing at 115200 + for Cogent CMA230 (ARM). + + * src/arm/cma230_serial.c: Fix interrupt for port B. + +1999-05-31 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Fixed receive interrupts and added handler for + error interrupts. + +1999-05-28 Jesper Skov <jskov@cygnus.co.uk> + + * io/serial/current/src/PKGconf.mak: + * io/serial/current/tests/ser_test_protocol.inl: + * include/pkgconf/io_serial.h: + Renamed SH platform package to edk7708. + +1999-05-27 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added ability to change options in + host software. + +1999-05-27 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + Wait for the serial device to become acquiescent before disabling + it. This prevents cygmon's outgoing characters getting corrupted + due to transmission being disabled. + Fix for PR 20047 + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * tests/ser_test_protocol.inl: Add Cogent CMA230 setup. + + * src/arm/cma230_serial.c: Make names compatible with Cogent + PowerPC board. + +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. +1999-05-26 Jesper Skov <jskov@cygnus.co.uk> + + * src/sh/sh_serial.c: Added more baud rate values. Disabled + interrupt driven receive. Fixed config_port to enable proper + interrupt flags. + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Change all mentions of CYGPKG_HAL_TX39_JMR3904 to + CYGPKG_HAL_MIPS_TX39_JMR3904 + +1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): Change CYG_HAL_TX39 to + CYG_HAL_MIPS_TX39 +1999-05-25 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added sh entry. + +1999-05-24 Jesper Skov <jskov@cygnus.co.uk> + + * src/PKGconf.mak: + * include/pkgconf/io_serial.h: + * src/sh/sh_serial.c: + Added sh driver. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if + there is one. + +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + +1999-05-14 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Removed workaround for spurious + Cogent reads. + + * src/arm/aeb_serial.c: + * src/arm/aeb_serial.h: + * src/arm/pid_serial_with_ints.c: + * src/arm/pid_serial.h: + * src/powerpc/cogent_serial.h: + * src/powerpc/cogent_serial_with_ints.c: + Check for receive interrupt before reading. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + The follow changes were made in a branch an have now been merged: + + 1999-04-21 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mips/vrc4373_serial.c: Small changes to get working with + interrupts. + + 1999-04-20 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 + parent attribute. + +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Tidied up a bit and added + description of protocol. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/serial.c (serial_write, serial_read): Clear abort + flag at entry. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): Handle config fails correctly. + + * tests/ser_test_protocol.inl: Better change_config + handling. Simple recovery and negotiation isn't timing + dependant. + +1999-05-05 Jesper Skov <jskov@cygnus.co.uk> + + * tests/timeout.inl: Updated with the below changes. + +1999-05-05 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/timeout.inl (timeout): Timeouts are relative, but alarms + need absolute time values. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + PR 20018 + * tests/serial1.c (serial_test): Always PASS, regardless of + configuration. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Reverse order of configurations - + run tests with slow baud rate first. + Only check CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT for SLEB on RAM startup. + +1999-05-04 Jesper Skov <jskov@cygnus.co.uk> + * src/mn10300/mn10300_serial.c: + Use interrupt enable/disable feature of serial port2 to allow + coexistence with CygMon/hal_diag. + + * tests/ser_test_protocol.inl: Use port2 for MN10300. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS_COMPILE): + Use the new rules for generating libextras.a + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + + +1999-04-20 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Fix default baud rate if unbuffered. +1999-04-20 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added some comments. Disabled 38400 + for SLEB. Only run test on SLEB if CygMon isn't used for diag + output. + +1999-04-15 Jesper Skov <jskov@cygnus.co.uk> + PR 19752 + * tests/serial3.c: + * tests/serial5.c: + Run these tests at a lower baud rate on ARM AEB. + +1999-04-14 Jesper Skov <jskov@cygnus.co.uk> + PR 19839 + * src/mn10300/mn10300_serial.c: + Fix compiler warnings. + +1999-04-14 Bart Veer <bartv@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + Reparent the board-specific serial devices below the actual boards. + +1999-04-13 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + NA when run from simulator. + +1999-04-12 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: + Disabled 115200 for MN10300. + Reclaim interrupt vectors from CygMon when testing on SLEB. + +1999-04-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serial.h: Change SERIAL_CHANNEL setup so all channels + have serial callbacks, regardless of buffering. + +1999-04-09 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/tty.c: + * include/pkgconf/io_serial.h: + Added new ttydiag device layered on top of haldiag, so that tty0 + can be layered on top of ser0. + +1999-04-08 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: [added] + * tests/tty2.c: [added] + * tests/PKGconf.mak: + * tests/ser_test_protocol.inl: + Added two simple TTY tests. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.h: Include cyg/hal/hal_io.h for I/O + macros instead of hal_diag.h where they had evolved before. + +1999-04-06 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial4.c (serial_test): + * tests/serial3.c (serial_test): + Reduce packet sizes. + +1999-03-31 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Added remaining targets to the + test. + +1999-03-31 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_start_xmit): Fix timing race + when enabling xmit interrupts. + +1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: Change how the port is set up. The transmitter + is now always enabled, just the interrupts are masked/unmasked to control it. + This lets the serial driver cooperate with Cygmon on the port used for GDB. + Note that currently serial input does not work for CON1 since Cygmon is + taking all of the receive interrupts for itself. + (sleb_sdtr_tx_DSR): Need to keep track whether xmit interrupt should be + enabled - otherwise it can get enabled incorrectly and we get interrupted + to death! + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Send a DONE message after a no-echo + binary packet. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Make these build when no kernel present; include of testcase + was the wrong side of the ifdef. + +1999-03-26 Jesper Skov <jskov@cygnus.co.uk> + + * tests/serial5.c: + * tests/serial4.c: + * tests/serial3.c: + * tests/serial2.c: + * tests/serial1.c: + Moved NOP check to ser_test_protocol open call. + + * tests/ser_test_protocol.inl: Make sure the proper device is + selected for testing. Do NOP check in open call. + +1999-03-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: + * misc/console.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/tty.c: + * src/mips/tx3904_serial.c: + * src/mn10300/mn10300_serial.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: Update CDL to follow naming conventions. + + * src/mips/tx3904_serial.c (tx3904_serial_config_port): + Make sure port is enabled (CDL) before using it. + + * src/mn10300/mn10300_serial.c (mn10300_serial_config_port): + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + * src/arm/aeb_serial.c (aeb_serial_config_port): + * src/arm/pid_serial_with_ints.c (pid_serial_config_port): Change so that + the physical port is not modified unless the provided configuration is valid. + + * src/sparclite/sleb_sdtr.c (sleb_sdtr_config_port): + Using wrong config data. + + * include/serialio.h: Add macros to support baud rate from CDL. + + * include/pkgconf/io_serial.h: + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c (tx3904_serial_ISR): + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Add configury for baud rate and buffer size. + +1999-03-24 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Now uses CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL to get CPU + frequency. This is a little more accurate than using + CYGHWR_HAL_MIPS_CPU_FREQ. + +1999-03-24 Gary Thomas <gthomas@cygnus.co.uk> + + * include/serialio.h (CYGNUM_SERIAL_BAUD_MIN/MAX): Add for completeness. + + * src/arm/aeb_serial.c (aeb_serial_stop_xmit): + * src/arm/pid_serial_with_ints.c (pid_serial_stop_xmit): Fix typo in comment. + +1999-03-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Weeded out configs TX39 doesn't + like. + + * src/powerpc/cogent_serial.h: + Added copyright header. + + * tests/ser_test_protocol.inl: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + Don't try to run tests when no IO device has been specified. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial1.c, misc/serial2.c, misc/serial3.c, misc/serial4.c, + * misc/serial5.c, misc/ser_test_protocol.inl + Deleted. + +1999-03-23 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * tests/timeout.inl: + * tests/PKGconf.mak: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/ser_test_protocol.inl: + Moved the serial tests from the misc directory to the tests + directory. + +1999-03-23 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Now initially mask TX interrupts + at initialization and unmask/remask in start/stop xmit + routines. This has no real effect on the hardware, but the + simulator does not implement the LCR_TXE bit properly, resulting + in spurious TX interrupts during diagnostic output. + This was the cause of the slow output reported in PR 19559. + +1999-03-23 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix "display" strings to have appropriate + case - mostly lower case. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/console.c: + * misc/serial.c: + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + * src/mips/tx3904_serial.c: Add CDL configury. + + * include/pkgconf/io_serial.h: Update CDL to add device name + configurability for all devices. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Use CDL configured device names. + +1999-03-22 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * misc/serial1.c: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + * misc/serial5.c: + Requires kernel as well. + +1999-03-22 Jesper Skov <jskov@cygnus.co.uk> + + * src/sparclite/sleb_sdtr.c: + Moved include statement to avoid warnings. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial5.c: + * misc/PKGconf.mak: + Replace complex and not very stable duplex test with a simpler + test that works better. + Added serial5 using that test. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/serial1.c: + * misc/serial2.c: + Added API test and made serial2 do simple string output. + +1999-03-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Changed ToDo comment. + +1999-03-19 Jesper Skov <jskov@lassi.cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + Moved include statement to avoid warnings. + +1999-03-19 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: More CDL problems. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add CDL for SPARClite SLEB. + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/pid_serial_with_ints.c: + * src/arm/aeb_serial.c: Update device names to match CDL. + + * include/pkgconf/io_serial.h: Change names for serial ports to + be CYGPKG_IO_SERIAL_<arch>_<platform>_<port>. + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: + * misc/serial2.c: + First stab at the duplex binary test. Still much fun to be had... + +1999-03-18 Jesper Skov <jskov@cygnus.co.uk> + + * misc/ser_test_protocol.inl: Added timeout for PING. + +1999-03-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change ABORT functionality to be DSR safe. + (serial_get_config): Fix typo! + + * include/pkgconf/io_serial.h: Small change in CDL to make serial + devices tied to the platform and not the serial I/O package. This + means that only the devices appropriate to a given platform can be + enabled. + + * misc/serial.c: Better use of alarms - only trigger at the time of + the next timeout. Moved timeout functions to new file "timeout.inl". + + * src/common/serial.c (serial_get_config): Add support for + CYG_IO_GET_CONFIG_SERIAL_INPUT_FLUSH and CYG_IO_GET_CONFIG_SERIAL_ABORT. + + * misc/serial.c: Add simple timeout mechanisms. + +1999-03-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Conditionalize based on CDL. + + * include/pkgconf/io_serial.h: Add some CDL configury - not perfect + because of current ~CDL limitations. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Cleaned up a bit. Used for hacking new tests. + +1999-03-17 Jesper Skov <jskov@cygnus.co.uk> + + * misc/PKGconf.mak: + * misc/ser_test_protocol.inl: + * misc/serial2.c: + * misc/serial3.c: + * misc/serial4.c: + Put testing protocol implementation in a separate file. Split the + tests in serial2 into separate files. + +1999-03-16 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Fixed some compiler warnings. + +1999-03-15 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Change default configurations. + No serial drivers enabled for PID port A or AEB. + + * src/sparclite/sleb_sdtr.c: + * src/powerpc/cogent_serial_with_ints.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: + * src/common/haldiag.c: + * src/common/tty.c: + * src/common/serial.c: Add 'CYGDBG_IO_INIT' for control of init + messages. + + * src/powerpc/cogent_serial_with_ints.c: + * src/sparclite/sleb_sdtr.c: + * src/arm/aeb_serial.c: + * src/arm/pid_serial_with_ints.c: Don't include <cyg/kernel/kapi.h> + +1999-03-15 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Fix use of strlen. Fix DONE part + of binary protocol. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Play a bit with timing. Think I broke it :( + Added DONE to BINARY packet. + Proper call to DRAIN. + +1999-03-12 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: Tidied away some debugging code. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Removed bogus config changes. + +1999-03-12 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Check for ser_filter on host (PING + packet). + +1999-03-11 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Added note. + + * misc/serial2.c: + Added (almost) proper configuration handling. + Run tests on varying configurations. + +1999-03-11 Nick Garnett <nickg@cygnus.co.uk> + + * src/mips/tx3904_serial.c: + Many changes to get working. + + * misc/console.c (console_test): Fixed compiler warning. + + * misc/serial2.c: + Added device name for TX39 testing. + Fixed some bugs in Tcyg_io_write() macro. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: Added target specific test device name. + +1999-03-10 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct CDL description spelling. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + * misc/console.c: + Fixed compiler warnings. + +1999-03-10 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Improve CDL descriptions. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Do some more tests with changed + baud rates. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Added workaround for spurious byte + problem. Added a few more tests to run. + + * src/powerpc/cogent_serial_with_ints.c + (cogent_serial_config_port): Remove interrupt enabling. + +1999-03-09 Nick Garnett <nickg@cygnus.co.uk> + + * src/PKGconf.mak: + * src/mips/tx3904_serial.c: + Added initial version of TX39 device driver. Currently untested + but eliminates PR19445. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c: DRAIN function works now. + +1999-03-09 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Only enable one serial driver per + default. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial2.c (serial_test): Be a bit more aggressive. + + * src/powerpc/cogent_serial_with_ints.c: Check that configuration + is sensible. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: + Added support for both ports. + + * include/pkgconf/io_serial.h: Added simple defines for cogent + serial ports. No CDL yet. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * misc/serial.c: Removed PID references. Fixed compiler warnings. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c: Cleaned up a + bit. Actually works now. + +1999-03-08 Gary Thomas <gthomas@cygnus.co.uk> + + * src/common/serial.c: Change in cyg_drv_cond_wait() behaviour + means DSR lock should be left alone. + +1999-03-08 Jesper Skov <jskov@cygnus.co.uk> + PR 19400 + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_init): Set + valid interrupt priority. + +1999-03-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c (mn10300_serial_init): + Added extra test to avoid initializing serial 2 when CYGMON is + present. + Include hal_intr.h explicitly for use in non-kernel + configurations. + + * src/common/serial.c: + Added extra test before calls to cyg_drv_cond_wait() to avoid race + condition. This is not, however, a complete solution to this + problem. A better solution will be forthcoming. + + * include/serial.h: + Changed include files used to permit non-kernel configurations to + be built. + +1999-03-05 Jesper Skov <jskov@cygnus.co.uk> + + * src/common/haldiag.c: Removed diag_printf declaration. + +1999-03-05 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: + Change CYG_VECTOR_* to CYGNUM_HAL_INTERRUPT_* to get it to compile! + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/cogent_serial_with_ints.c (cogent_serial_config_port): + Fix renaming of interrupt vectors. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/pid_serial_with_ints.c: Fix interrupt vectors. + +1999-03-03 Gary Thomas <gthomas@cygnus.co.uk> + + * serial/current/src/arm/pid_serial_with_ints.c: + New [somewhat] configurable drivers for PID. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/vrc437x/current/cdl/ser_mips_vrc437x.cdl @@ -0,0 +1,195 @@ +# ==================================================================== +# +# ser_mips_vrc437x.cdl +# +# eCos serial MIPS/VRC437X configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: gthomas +# Contributors: +# Date: 1999-07-14 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_MIPS_VRC437X { + display "VRC437X serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_MIPS_VR4300_VRC437X + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + VRC4373." + doc redirect/ecos-device-drivers.html + + compile -library=libextras.a vrc437x_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_mips_vrc437x.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 { + display "VRC437X serial port 0 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 0." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME { + display "Device name for the VRC437X serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option sets the name of the serial device for the VRC437X + port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD { + display "Baud rate for the VRC437X serial port 0 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE { + display "Buffer size for the VRC437X serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the VRC437X port 0." + } +} +cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1 { + display "VRC437X serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the VRC437X port 1." + + cdl_option CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME { + display "Device name for the VRC437X serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD { + display "Baud rate for the VRC437X serial port 1 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + VRC437X port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE { + display "Buffer size for the VRC437X serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used for + the VRC437X port 1." + } +} + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_MIPS_VRC437X_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGPKG_IO_SERIAL_MIPS_VRC437X_TESTING { + display "Testing parameters" + flavor bool + calculated 1 + active_if CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0 + + cdl_option CYGPRI_SER_TEST_SER_DEV { + display "Serial device used for testing" + flavor data + default_value { CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME } + } + + define_proc { + puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"vrc437X\"" + puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty0\"" + } + } +} + +# EOF ser_mips_vrc437x.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.c @@ -0,0 +1,485 @@ +//========================================================================== +// +// io/serial/mips/vrc4373_serial.c +// +// Mips VRC4373 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: VRC4373 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373 + +#include "vrc4373_serial.h" + +#if defined(CYGPKG_HAL_MIPS_LSBFIRST) +#define VRC4373_SCC_BASE 0xC1000000 +#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) +#define VRC4373_SCC_BASE 0xC1000003 +#else +#error MIPS endianness not defined by configuration +#endif + +#define VRC4373_SCC_INT CYGNUM_HAL_INTERRUPT_DUART +#define SCC_CHANNEL_A 4 +#define SCC_CHANNEL_B 0 + +extern void diag_printf(const char *fmt, ...); + +typedef struct vrc4373_serial_info { + CYG_ADDRWORD base; + unsigned char regs[16]; // Known register state (since hardware is write-only!) +} vrc4373_serial_info; + +static bool vrc4373_serial_init(struct cyg_devtab_entry *tab); +static bool vrc4373_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo vrc4373_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char vrc4373_serial_getc(serial_channel *chan); +static Cyg_ErrNo vrc4373_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void vrc4373_serial_start_xmit(serial_channel *chan); +static void vrc4373_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(vrc4373_serial_funs, + vrc4373_serial_putc, + vrc4373_serial_getc, + vrc4373_serial_set_config, + vrc4373_serial_start_xmit, + vrc4373_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 +static vrc4373_serial_info vrc4373_serial_info0 = {VRC4373_SCC_BASE+SCC_CHANNEL_A}; +#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE > 0 +static unsigned char vrc4373_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE]; +static unsigned char vrc4373_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel0, + vrc4373_serial_funs, + vrc4373_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc4373_serial_out_buf0[0], sizeof(vrc4373_serial_out_buf0), + &vrc4373_serial_in_buf0[0], sizeof(vrc4373_serial_in_buf0) + ); +#else +static SERIAL_CHANNEL(vrc4373_serial_channel0, + vrc4373_serial_funs, + vrc4373_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc4373_serial_io0, + CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc4373_serial_init, + vrc4373_serial_lookup, // Serial driver may need initializing + &vrc4373_serial_channel0 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 + +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 +static vrc4373_serial_info vrc4373_serial_info1 = {VRC4373_SCC_BASE+SCC_CHANNEL_B}; +#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE > 0 +static unsigned char vrc4373_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE]; +static unsigned char vrc4373_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel1, + vrc4373_serial_funs, + vrc4373_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &vrc4373_serial_out_buf1[0], sizeof(vrc4373_serial_out_buf1), + &vrc4373_serial_in_buf1[0], sizeof(vrc4373_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(vrc4373_serial_channel1, + vrc4373_serial_funs, + vrc4373_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(vrc4373_serial_io1, + CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + vrc4373_serial_init, + vrc4373_serial_lookup, // Serial driver may need initializing + &vrc4373_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 + +static cyg_interrupt vrc4373_serial_interrupt; +static cyg_handle_t vrc4373_serial_interrupt_handle; + +// Table which maps hardware channels (A,B) to software ones +struct serial_channel *vrc4373_chans[] = { +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 // Hardware channel A + &vrc4373_serial_channel0, +#else + 0, +#endif +#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 // Hardware channel B + &vrc4373_serial_channel1, +#else + 0, +#endif +}; + +// Support functions which access the serial device. Note that this chip requires +// a substantial delay after each access. + +#define SCC_DELAY 100 +inline static void +scc_delay(void) +{ + int i; + for (i = 0; i < SCC_DELAY; i++) ; +} + +inline static void +scc_write_reg(volatile unsigned char *reg, unsigned char val) +{ + scc_delay(); + *reg = val; +} + +inline static unsigned char +scc_read_reg(volatile unsigned char *reg) +{ + unsigned char val; + scc_delay(); + val = *reg; + return (val); +} + +inline static unsigned char +scc_read_ctl(volatile struct serial_port *port, int reg) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + return (scc_read_reg(&port->scc_ctl)); +} + +inline static void +scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val) +{ + if (reg != 0) { + scc_write_reg(&port->scc_ctl, reg); + } + scc_write_reg(&port->scc_ctl, val); +} + +inline static unsigned char +scc_read_dat(volatile struct serial_port *port) +{ + return (scc_read_reg(&port->scc_dat)); +} + +inline static void +scc_write_dat(volatile struct serial_port *port, unsigned char val) +{ + scc_write_reg(&port->scc_dat, val); +} + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +vrc4373_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + cyg_int32 baud_rate = select_baud[new_config->baud]; + cyg_int32 baud_divisor; + unsigned char *regs = &vrc4373_chan->regs[0]; + if (baud_rate == 0) return false; + // Compute state of registers. The register/control state needs to be kept in + // the shadow variable 'regs' because the hardware registers can only be written, + // not read (in general). + if (init) { + // Insert appropriate resets? + if (chan->out_cbuf.len != 0) { + regs[R1] = WR1_IntAllRx; + regs[R9] = WR9_MIE | WR9_NoVector; + } else { + regs[R1] = 0; + regs[R9] = 0; + } + // Clocks are from the baud rate generator + regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR; + regs[R14] = WR14_BRenable | WR14_BRSRC; + regs[R10] = 0; // Unused in this [async] mode + regs[R15] = 0; + } + regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity]; + regs[R5] = WR5_TxEnable | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5]; + baud_divisor = BRTC(baud_rate); + regs[R12] = baud_divisor & 0xFF; + regs[R13] = baud_divisor >> 8; + // Now load the registers + scc_write_ctl(port, R4, regs[R4]); + scc_write_ctl(port, R10, regs[R10]); + scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable); + scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable); + scc_write_ctl(port, R1, regs[R1]); + scc_write_ctl(port, R9, regs[R9]); + scc_write_ctl(port, R11, regs[R11]); + scc_write_ctl(port, R12, regs[R12]); + scc_write_ctl(port, R13, regs[R13]); + scc_write_ctl(port, R14, regs[R14]); + scc_write_ctl(port, R15, regs[R15]); + scc_write_ctl(port, R3, regs[R3]); + scc_write_ctl(port, R5, regs[R5]); + // Update configuration + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +vrc4373_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + static bool init = false; +#ifdef CYGDBG_IO_INIT + diag_printf("VRC4373 SERIAL init '%s' - dev: %x\n", tab->name, vrc4373_chan->base); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (!init && chan->out_cbuf.len != 0) { + init = true; +// Note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A + cyg_drv_interrupt_create(VRC4373_SCC_INT, + 99, + (cyg_addrword_t)VRC4373_SCC_BASE+SCC_CHANNEL_A, + vrc4373_serial_ISR, + vrc4373_serial_DSR, + &vrc4373_serial_interrupt_handle, + &vrc4373_serial_interrupt); + cyg_drv_interrupt_attach(vrc4373_serial_interrupt_handle); + cyg_drv_interrupt_unmask(VRC4373_SCC_INT); + } + vrc4373_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +vrc4373_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +vrc4373_serial_putc(serial_channel *chan, unsigned char c) +{ + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + if (scc_read_ctl(port, R0) & RR0_TxEmpty) { +// Transmit buffer is empty + scc_write_dat(port, c); + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +vrc4373_serial_getc(serial_channel *chan) +{ + unsigned char c; + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ; // Wait for char + c = scc_read_dat(port); + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +vrc4373_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != vrc4373_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter on the device +static void +vrc4373_serial_start_xmit(serial_channel *chan) +{ + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) == 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc4373_chan->regs[R1] |= WR1_TxIntEnab; // Enable Tx interrupt + scc_write_ctl(port, R1, vrc4373_chan->regs[R1]); + (chan->callbacks->xmt_char)(chan); // Send first character to start xmitter + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Disable the transmitter on the device +static void +vrc4373_serial_stop_xmit(serial_channel *chan) +{ + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + if ((vrc4373_chan->regs[R1] & WR1_TxIntEnab) != 0) { + CYG_INTERRUPT_STATE old; + HAL_DISABLE_INTERRUPTS(old); + vrc4373_chan->regs[R1] &= ~WR1_TxIntEnab; // Disable Tx interrupt + scc_write_ctl(port, R1, vrc4373_chan->regs[R1]); + HAL_RESTORE_INTERRUPTS(old); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + cyg_drv_interrupt_mask(VRC4373_SCC_INT); + cyg_drv_interrupt_acknowledge(VRC4373_SCC_INT); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +inline static void +vrc4373_int(serial_channel *chan, unsigned char stat) +{ + vrc4373_serial_info *vrc4373_chan = (vrc4373_serial_info *)chan->dev_priv; + volatile struct serial_port *port = (volatile struct serial_port *)vrc4373_chan->base; + // Note: 'stat' value is interrupt status register, shifted into "B" position + if (stat & RR3_BRxIP) { + // Receive interrupt + unsigned char c; + c = scc_read_dat(port); + (chan->callbacks->rcv_char)(chan, c); + } + if (stat & RR3_BTxIP) { + // Transmit interrupt + (chan->callbacks->xmt_char)(chan); + } + if (stat & RR3_BExt) { + // Status interrupt (parity error, framing error, etc) + } +} + +// Serial I/O - high level interrupt handler (DSR) +// Note: This device presents a single interrupt for both channels. Thus the +// interrupt handler has to query the device and decide which channel needs service. +// Additionally, more than one interrupt condition may be present so this needs to +// be done in a loop until all interrupt requests have been handled. +// Also note that the hardware is rather broken. The interrupt status needs to +// be read using only channel A (pointed to by 'data') +static void +vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan; + volatile struct serial_port *port = (volatile struct serial_port *)data; + unsigned char stat; + while (true) { + stat = scc_read_ctl(port, R3); + if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) { + chan = vrc4373_chans[0]; // Hardware channel A + vrc4373_int(chan, stat>>3); // Handle interrupt + } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) { + chan = vrc4373_chans[1]; // Hardware channel B + vrc4373_int(chan, stat); // Handle interrupt + } else { + // No more interrupts, all done + break; + } + } + cyg_drv_interrupt_unmask(VRC4373_SCC_INT); +} +#endif
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mips/vrc437x/current/src/vrc437x_serial.h @@ -0,0 +1,335 @@ +#ifndef CYGONCE_MIPS_VRC4373_SERIAL_H +#define CYGONCE_MIPS_VRC4373_SERIAL_H + +// ==================================================================== +// +// aeb_serial.h +// +// Device I/O - Description of Mips VRC4373 serial hardware +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-15 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Mips VRC4373 +// Based on Zilog 85C30 SCC + +struct serial_port { + unsigned char _byte[16]; +}; + +#define scc_ctl _byte[0] +#define scc_dat _byte[8] + +#define R0 0 /* Register selects */ +#define R1 1 +#define R2 2 +#define R3 3 +#define R4 4 +#define R5 5 +#define R6 6 +#define R7 7 +#define R8 8 +#define R9 9 +#define R10 10 +#define R11 11 +#define R12 12 +#define R13 13 +#define R14 14 +#define R15 15 + +/* Write Register 0 */ +#define WR0_NullCode 0x00 /* Null Code */ +#define WR0_PointHigh 0x08 /* Select upper half of registers */ +#define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */ +#define WR0_SendAbort 0x18 /* HDLC Abort */ +#define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */ +#define WR0_ResTxP 0x28 /* Reset TxINT Pending */ +#define WR0_ErrReset 0x30 /* Error Reset */ +#define WR0_ResHiIUS 0x38 /* Reset highest IUS */ + +#define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */ +#define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */ +#define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */ + +/* Write Register 1 */ + +#define WR1_ExtIntEnab 0x01 /* Ext Int Enable */ +#define WR1_TxIntEnab 0x02 /* Tx Int Enable */ +#define WR1_ParSpec 0x04 /* Parity is special condition */ + +#define WR1_RxIntDisab 0x00 /* Rx Int Disable */ +#define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */ +#define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */ +#define WR1_IntErrRx 0x18 /* Int on error only */ + +#define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */ +#define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */ +#define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */ + +/* Write Register #2 (Interrupt Vector) */ + +/* Write Register 3 */ + +#define WR3_RxEnable 0x01 /* Rx Enable */ +#define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */ +#define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */ +#define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */ +#define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */ +#define WR3_AutoEnab 0x20 /* Auto Enables */ +#define WR3_Rx5 0x00 /* Rx 5 Bits/Character */ +#define WR3_Rx7 0x40 /* Rx 7 Bits/Character */ +#define WR3_Rx6 0x80 /* Rx 6 Bits/Character */ +#define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */ +#define WR3_RxNbitsMask 0xc0 + +/* Write Register 4 */ + +#define WR4_ParityEn 0x01 /* Parity Enable */ +#define WR4_ParityEven 0x02 /* Parity Even/Odd* */ + +#define WR4_SyncEnable 0x00 /* Sync Modes Enable */ +#define WR4_SB1 0x04 /* 1 stop bit/char */ +#define WR4_SB15 0x08 /* 1.5 stop bits/char */ +#define WR4_SB2 0x0c /* 2 stop bits/char */ +#define WR4_SB_MASK 0x0c + +#define WR4_Monsync 0x00 /* 8 Bit Sync character */ +#define WR4_Bisync 0x10 /* 16 bit sync character */ +#define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ +#define WR4_EXtSync 0x30 /* External Sync Mode */ + +#define WR4_X1CLK 0x00 /* x1 clock mode */ +#define WR4_X16CLK 0x40 /* x16 clock mode */ +#define WR4_X32CLK 0x80 /* x32 clock mode */ +#define WR4_X64CLK 0xC0 /* x64 clock mode */ +#define WR4_XCLK_MASK 0xC0 + +/* Write Register 5 */ + +#define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */ +#define WR5_RTS 0x02 /* RTS */ +#define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */ +#define WR5_TxEnable 0x08 /* Tx Enable */ +#define WR5_SendBreak 0x10 /* Send Break */ +#define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */ +#define WR5_Tx7 0x20 /* Tx 7 bits/character */ +#define WR5_Tx6 0x40 /* Tx 6 bits/character */ +#define WR5_Tx8 0x60 /* Tx 8 bits/character */ +#define WR5_TxNbitsMask 0x60 +#define WR5_DTR 0x80 /* DTR */ + +/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ + +/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ + +/* Write Register 8 (transmit buffer) */ + +/* Write Register 9 (Master interrupt control) */ +#define WR9_VIS 0x01 /* Vector Includes Status */ +#define WR9_NoVector 0x02 /* No Vector */ +#define WR9_DLC 0x04 /* Disable Lower Chain */ +#define WR9_MIE 0x08 /* Master Interrupt Enable */ +#define WR9_StatHi 0x10 /* Status high */ +#define WR9_NoReset 0x00 /* No reset on write to R9 */ +#define WR9_ResetB 0x40 /* Reset channel B */ +#define WR9_ResetA 0x80 /* Reset channel A */ +#define WR9_HwReset 0xc0 /* Force hardware reset */ + +/* Write Register 10 (misc control bits) */ +#define WR10_Bit6 0x01 /* 6 bit/8bit sync */ +#define WR10_LoopMode 0x02 /* SDLC Loop mode */ +#define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */ +#define WR10_MarkIdle 0x08 /* Mark/flag on idle */ +#define WR10_GAOP 0x10 /* Go active on poll */ +#define WR10_NRZ 0x00 /* NRZ mode */ +#define WR10_NRZI 0x20 /* NRZI mode */ +#define WR10_FM1 0x40 /* FM1 (transition = 1) */ +#define WR10_FM0 0x60 /* FM0 (transition = 0) */ +#define WR10_CRCPS 0x80 /* CRC Preset I/O */ + +/* Write Register 11 (Clock Mode control) */ +#define WR11_TRxCXT 0x00 /* TRxC = Xtal output */ +#define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */ +#define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */ +#define WR11_TRxCDP 0x03 /* TRxC = DPLL output */ +#define WR11_TRxCOI 0x04 /* TRxC O/I */ +#define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */ +#define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */ +#define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */ +#define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */ +#define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */ +#define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */ +#define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */ +#define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */ +#define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */ + +/* Write Register 12 (lower byte of baud rate generator time constant) */ + +/* Write Register 13 (upper byte of baud rate generator time constant) */ + +/* Write Register 14 (Misc control bits) */ +#define WR14_BRenable 0x01 /* Baud rate generator enable */ +#define WR14_BRSRC 0x02 /* Baud rate generator source */ +#define WR14_DTRreq 0x04 /* DTR/Request function */ +#define WR14_AutoEcho 0x08 /* Auto Echo */ +#define WR14_LoopBack 0x10 /* Local loopback */ +#define WR14_Search 0x20 /* Enter search mode */ +#define WR14_RMC 0x40 /* Reset missing clock */ +#define WR14_NoDPLL 0x60 /* Disable DPLL */ +#define WR14_SSBR 0x80 /* Set DPLL source = BR generator */ +#define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */ +#define WR14_SFMM 0xc0 /* Set FM mode */ +#define WR14_SNRZI 0xe0 /* Set NRZI mode */ + +/* Write Register 15 (external/status interrupt control) */ +#define WR15_ZCIE 0x02 /* Zero count IE */ +#define WR15_DCDIE 0x08 /* DCD IE */ +#define WR15_SYNCIE 0x10 /* Sync/hunt IE */ +#define WR15_CTSIE 0x20 /* CTS IE */ +#define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */ +#define WR15_BRKIE 0x80 /* Break/Abort IE */ + +/* Read Register 0 */ +#define RR0_RxAvail 0x01 /* Rx Character Available */ +#define RR0_Zcount 0x02 /* Zero count */ +#define RR0_TxEmpty 0x04 /* Tx Buffer empty */ +#define RR0_DCD 0x08 /* DCD */ +#define RR0_SyncHunt 0x10 /* Sync/hunt */ +#define RR0_CTS 0x20 /* CTS */ +#define RR0_TxEOM 0x40 /* Tx underrun */ +#define RR0_BrkAbort 0x80 /* Break/Abort */ + +/* Read Register 1 */ +#define RR1_AllSent 0x01 /* All sent */ +/* Residue Data for 8 Rx bits/char programmed */ +#define RR1_RES3 0x08 /* 0/3 */ +#define RR1_RES4 0x04 /* 0/4 */ +#define RR1_RES5 0x0c /* 0/5 */ +#define RR1_RES6 0x02 /* 0/6 */ +#define RR1_RES7 0x0a /* 0/7 */ +#define RR1_RES8 0x06 /* 0/8 */ +#define RR1_RES18 0x0e /* 1/8 */ +#define RR1_RES28 0x00 /* 2/8 */ +/* Special Rx Condition Interrupts */ +#define RR1_PariryError 0x10 /* Parity error */ +#define RR1_RxOverrun 0x20 /* Rx Overrun Error */ +#define RR1_FrameError 0x40 /* CRC/Framing Error */ +#define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */ + +/* Read Register 2 (channel b only) - Interrupt vector */ + +/* Read Register 3 (interrupt pending register) ch a only */ +#define RR3_BExt 0x01 /* Channel B Ext/Stat IP */ +#define RR3_BTxIP 0x02 /* Channel B Tx IP */ +#define RR3_BRxIP 0x04 /* Channel B Rx IP */ +#define RR3_AExt 0x08 /* Channel A Ext/Stat IP */ +#define RR3_ATxIP 0x10 /* Channel A Tx IP */ +#define RR3_ARxIP 0x20 /* Channel A Rx IP */ + +/* Read Register 8 (receive data register) */ + +/* Read Register 10 (misc status bits) */ +#define RR10_OnLoop 0x02 /* On loop */ +#define RR10_LoopSend 0x10 /* Loop sending */ +#define RR10_Clk2Mis 0x40 /* Two clocks missing */ +#define RR10_Clk1Mis 0x80 /* One clock missing */ + +/* Read Register 12 (lower byte of baud rate generator constant) */ + +/* Read Register 13 (upper byte of baud rate generator constant) */ + +/* Read Register 15 (value of WR 15) */ + +#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) +#define DUART_CLOCK 4915200 /* Z8530 duart */ +#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ + +static unsigned char select_word_length_WR3[] = { + WR3_Rx5, // 5 bits / word (char) + WR3_Rx6, + WR3_Rx7, + WR3_Rx8 +}; + +static unsigned char select_word_length_WR5[] = { + WR5_Tx5, // 5 bits / word (char) + WR5_Tx6, + WR5_Tx7, + WR5_Tx8 +}; + +static unsigned char select_stop_bits[] = { + 0, + WR4_SB1, // 1 stop bit + WR4_SB15, // 1.5 stop bit + WR4_SB2 // 2 stop bits +}; + +static unsigned char select_parity[] = { + 0, // No parity + WR4_ParityEn | WR4_ParityEven, // Even parity + WR4_ParityEn, // Odd parity + 0xFF, // Mark parity + 0xFF, // Space parity +}; + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 0, // 57600 + 0, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_MIPS_VRC4373_SERIAL_H
--- a/packages/devs/serial/mn10300/mn10300/current/ChangeLog +++ b/packages/devs/serial/mn10300/mn10300/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_mn10300.cdl: + Fix 234000->230400 typo. + 2000-08-01 Jonathan Larmour <jlarmour@redhat.co.uk> * src/mn10300_serial.c (mn10300_serial_set_config): Now use keys to make
--- a/packages/devs/serial/mn10300/mn10300/current/cdl/ser_mn10300.cdl +++ b/packages/devs/serial/mn10300/mn10300/current/cdl/ser_mn10300.cdl @@ -98,7 +98,7 @@ cdl_component CYGPKG_IO_SERIAL_MN10300_S display "Baud rate for the MN10300 serial port 0 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -137,7 +137,7 @@ cdl_component CYGPKG_IO_SERIAL_MN10300_S display "Baud rate for the MN10300 serial port 1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -175,7 +175,7 @@ cdl_component CYGPKG_IO_SERIAL_MN10300_S display "Baud rate for the MN10300 serial port 2 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/powerpc/cogent/current/ChangeLog +++ b/packages/devs/serial/powerpc/cogent/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_powerpc_cogent.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_powerpc_cogent.cdl: Moved testing parameters here.
--- a/packages/devs/serial/powerpc/cogent/current/cdl/ser_powerpc_cogent.cdl +++ b/packages/devs/serial/powerpc/cogent/current/cdl/ser_powerpc_cogent.cdl @@ -87,7 +87,7 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_C display "Baud rate for the Cogent PowerPC serial port A driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -126,7 +126,7 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_C display "Baud rate for the Cogent PowerPC serial port B driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/powerpc/quicc/current/ChangeLog +++ b/packages/devs/serial/powerpc/quicc/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_quicc_smc.cdl: + Fix 234000->230400 typo. + 2000-12-22 Björn Stenberg <bjorn@haxx.se> * src/quicc_smc_serial.c (quicc_smc_serial_init_info):
--- a/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl +++ b/packages/devs/serial/powerpc/quicc/current/cdl/ser_quicc_smc.cdl @@ -85,7 +85,7 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q display "Baud rate for the PowerPC QUICC/SMC serial port 1" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description " @@ -175,7 +175,7 @@ cdl_component CYGPKG_IO_SERIAL_POWERPC_Q display "Baud rate for the PowerPC QUICC/SMC serial port 2" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/devs/serial/sparclite/sleb/current/ChangeLog +++ b/packages/devs/serial/sparclite/sleb/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/ser_sparclite_sleb.cdl: + Fix 234000->230400 typo. + 2000-10-12 Jesper Skov <jskov@redhat.com> * cdl/ser_sparclite_sleb.cdl: Moved testing parameters here.
--- a/packages/devs/serial/sparclite/sleb/current/cdl/ser_sparclite_sleb.cdl +++ b/packages/devs/serial/sparclite/sleb/current/cdl/ser_sparclite_sleb.cdl @@ -84,7 +84,7 @@ cdl_component CYGPKG_IO_SERIAL_SPARCLITE display "Baud rate for the SPARClite SLEB serial CON1 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 19200 description " @@ -123,7 +123,7 @@ cdl_component CYGPKG_IO_SERIAL_SPARCLITE display "Baud rate for the SPARClite SLEB serial CON2 driver" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 19200 description "
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -172,6 +172,16 @@ package CYGPKG_DEVS_FLASH_MIPS_OCELOT { on the PMC-Sierra Ocelot platform." } +package CYGPKG_DEVS_FLASH_MIPS_VRC437X { + alias { "Support for flash memory on VRC437X boards" flash_vrc437x } + directory devs/flash/mips/vrc437x + script flash_mips_vrc437x.cdl + hardware + description " + This package contains hardware support for flash memory + on the VRC437X platform." +} + package CYGPKG_DEVS_FLASH_EBSA285 { alias { "FLASH memory support for StrongARM EBSA-285" flash_ebsa285 } directory devs/flash/arm/ebsa285 @@ -471,13 +481,13 @@ package CYGPKG_IO_SERIAL_MIPS_REF4955 { description "TX49 REF4955 serial device drivers" } -package CYGPKG_IO_SERIAL_MIPS_VRC4373 { - alias { "VRC4373 serial device drivers" - devs_serial_mips_vrc4373 vrc4373_serial_driver } +package CYGPKG_IO_SERIAL_MIPS_VRC437X { + alias { "VRC437X serial device drivers" + devs_serial_mips_vrc437x vrc437x_serial_driver } hardware - directory devs/serial/mips/vrc4373 - script ser_mips_vrc4373.cdl - description "VRC4373 serial device drivers" + directory devs/serial/mips/vrc437x + script ser_mips_vrc437x.cdl + description "VRC437X serial device drivers" } package CYGPKG_IO_SERIAL_MN10300 { @@ -1714,6 +1724,16 @@ package CYGPKG_HAL_MIPS_VR4300_VRC4373 { actual hardware." } +package CYGPKG_HAL_MIPS_VR4300_VRC437X { + alias { "NEC VRC437X support" hal_vrc437x vrc437x_hal } + directory hal/mips/vrc437x + script hal_mips_vr4300_vrc437x.cdl + hardware + description " + The VRC437X HAL package should be used when targetting harware + that contains either a VRC437X companion chip." +} + # -------------------------------------------------------------------------- # MN10300 packages @@ -2300,12 +2320,15 @@ target vrc4373 { packages { CYGPKG_HAL_MIPS CYGPKG_HAL_MIPS_VR4300 CYGPKG_HAL_MIPS_VR4300_VRC4373 - CYGPKG_IO_SERIAL_MIPS_VRC4373 - CYGPKG_IO_PCI + CYGPKG_HAL_MIPS_VR4300_VRC437X + CYGPKG_IO_SERIAL_MIPS_VRC437X + CYGPKG_DEVS_FLASH_MIPS_VRC437X + CYGPKG_DEVS_FLASH_AMD_AM29XXXXX + CYGPKG_IO_PCI } description " The vrc4373 target provides the packages needed to run -eCos on an NEC VRC4373 board." + eCos on an NEC VRC4373 board." } # --------------------------------------------------------------------------
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,25 @@ +2001-09-10 Nick Garnett <nickg@redhat.com> + + * include/hal_stub.h (strlen): Changed return type to size_t from + int so it matches <string.h>. For some reason the compiler has + suddenly started complaining about the type mismatch. Strange. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * src/hal_stub.c (put_register): Added kludge for VR4300 targets + to sign extent the PC when it is being set. This is due to the + age of the VR4300 toolchain and the fact that the VR4300 is the + only target to do full 64bit register saves/restores. + +2001-09-07 Jesper Skov <jskov@redhat.com> + + * include/hal_if.h: Fix typo in below change. + +2001-09-07 Jonathan Larmour <jlarmour@redhat.com> + + * include/hal_if.h (CYGACC_CALL_IF_DBG_SYSCALL): Define and call + with correct arguments. + 2001-08-24 Mark Salter <msalter@redhat.com> * src/generic-stub.c (__process_packet): Add support for 'D' packet.
--- a/packages/hal/common/current/include/hal_if.h +++ b/packages/hal/common/current/include/hal_if.h @@ -554,8 +554,9 @@ static __inline__ _rt_ #define CYGACC_CALL_IF_DBG_DATA_SET(_x_) \ hal_virtual_vector_table[CYGNUM_CALL_IF_DBG_DATA]=(CYG_ADDRWORD)(_x_) -#define CYGACC_CALL_IF_DBG_SYSCALL() \ - CYGACC_CALL_VV2(__call_if_dbg_syscall_t, CYGNUM_CALL_IF_DBG_SYSCALL) +#define CYGACC_CALL_IF_DBG_SYSCALL(_id_,_p_) \ + CYGACC_CALL_VV2(__call_if_dbg_syscall_t, CYGNUM_CALL_IF_DBG_SYSCALL, _id_, _p_) +__call_VV2(CYGNUM_CALL_IF_DBG_SYSCALL, __call_if_dbg_syscall_t, int, enum dbg_syscall_ids , union dbg_thread_syscall_parms *) #define CYGACC_CALL_IF_DBG_SYSCALL_SET(_x_) \ hal_virtual_vector_table[CYGNUM_CALL_IF_DBG_SYSCALL]=(CYG_ADDRWORD)(_x_)
--- a/packages/hal/common/current/include/hal_stub.h +++ b/packages/hal/common/current/include/hal_stub.h @@ -289,7 +289,7 @@ static inline char *strcpy( char *s, con return r; } -static inline int strlen( const char *s ) +static inline size_t strlen( const char *s ) { int r = 0; while( *s++ ) r++;
--- a/packages/hal/common/current/src/hal_stub.c +++ b/packages/hal/common/current/src/hal_stub.c @@ -138,6 +138,18 @@ get_register_valid (regnames_t reg) void put_register (regnames_t which, target_register_t value) { +#ifdef CYGPKG_HAL_MIPS_VR4300 + // This is a rather nasty kludge to compensate for the fact that + // the VR4300 GDB is rather old and does not support proper 64 bit + // registers. The only time this really matters is when setting + // the PC after loading an executable. So here we detect this case + // and artificially sign extend it. + + if( which == PC && (value & 0x0000000080000000ULL ) ) + { + value |= 0xFFFFFFFF00000000ULL; + } +#endif _registers[which] = value; }
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,15 @@ +2001-09-07 Nick Garnett <nickg@redhat.com> + + * include/mips-stub.h: Returned target_register_t to long long + type for VR4300 target. This is the only platform that does 64bit + register saves/restores, and the GDB registers must be full sized. + + * include/arch.inc: Added option to select correct initial SR + value when the startup is ROMRAM. + Disabled setting of status and config registers when using a ROM + monitor. The monitor should have already set these to appropriate + values. + 2001-08-22 Gary Thomas <gthomas@redhat.com> * src/redboot_linux_exec.c:
--- a/packages/hal/mips/arch/current/include/arch.inc +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -72,7 +72,7 @@ # define INITIAL_SR_PLF 0x00000000 # endif -#if defined(CYG_HAL_STARTUP_RAM) +#if defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_ROMRAM) # if defined(CYGPKG_HAL_MIPS_SIM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR) # define INITIAL_SR_ARCH 0x1000ff00 /* CP0 usable, Ints enabled, master interrupt disable */ # else @@ -190,6 +190,7 @@ #endif /* CYGPKG_HAL_MIPS_MIPS32 || CYGPKG_HAL_MIPS_MIPS64 */ mtc0 zero,cause # zero cause reg nop +#if !defined(CYGSEM_HAL_USE_ROM_MONITOR) la v0,INITIAL_SR # initialize status register mtc0 v0,status nop @@ -200,6 +201,7 @@ nop nop nop +#endif .endm # Enable interrupts
--- a/packages/hal/mips/arch/current/include/mips-stub.h +++ b/packages/hal/mips/arch/current/include/mips-stub.h @@ -85,7 +85,7 @@ typedef unsigned long target_register_t; #elif defined(CYGPKG_HAL_MIPS_VR4300) // Even though we are only working with 32 bit registers, GDB expects 64 bits #define REGSIZE(X) 8 - typedef unsigned long target_register_t; + typedef unsigned long long target_register_t; // We need to sign-extend the registers so GDB doesn't get confused. #define CYGARC_SIGN_EXTEND_REGISTERS #elif defined(CYGPKG_HAL_MIPS_TX49)
--- a/packages/hal/mips/vr4300/current/ChangeLog +++ b/packages/hal/mips/vr4300/current/ChangeLog @@ -1,3 +1,17 @@ +2001-09-10 Nick Garnett <nickg@redhat.com> + + * src/mips_vr4300.ld: Added .2ram sections to data section needed + for FLASH support. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * include/variant.inc: Added definition of INITIAL_SR_VAR. + + * include/var_arch.h (CYG_HAL_GDB_REG): Returned GDB registers to + full 64bit width. + + * cdl/hal_mips_vr4300.cdl: Added endianness configuration. + 2000-09-01 Jonathan Larmour <jlarmour@redhat.com> * include/var_arch.h (CYG_HAL_GDB_REG): vr4300 GDB stubs now use
--- a/packages/hal/mips/vr4300/current/cdl/hal_mips_vr4300.cdl +++ b/packages/hal/mips/vr4300/current/cdl/hal_mips_vr4300.cdl @@ -69,9 +69,10 @@ cdl_package CYGPKG_HAL_MIPS_VR4300 { cdl_option CYGPKG_HAL_MIPS_MSBFIRST { display "CPU Variant big-endian" - calculated 1 + calculated { CYGPKG_HAL_MIPS_VR4300_VRC4373 != 0 } } + define_proc { puts $::cdl_header "#include <pkgconf/hal_mips.h>" }
--- a/packages/hal/mips/vr4300/current/include/var_arch.h +++ b/packages/hal/mips/vr4300/current/include/var_arch.h @@ -55,7 +55,7 @@ // 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's // not relevant for CYG_HAL_GDB_REG. -#define CYG_HAL_GDB_REG CYG_WORD32 +#define CYG_HAL_GDB_REG CYG_WORD64 //-------------------------------------------------------------------------- #endif // CYGONCE_HAL_VAR_ARCH_H
--- a/packages/hal/mips/vr4300/current/include/variant.inc +++ b/packages/hal/mips/vr4300/current/include/variant.inc @@ -57,6 +57,12 @@ #include <pkgconf/hal.h> #------------------------------------------------------------------------------ +# Initial SR value +# Set the KX bit to enable 64bit accesses in kernel mode. + +#define INITIAL_SR_VAR 0x00000080 + +#------------------------------------------------------------------------------ # Set up initial value for config register. Sets endian mode and # disables the cache on kseg0.
--- a/packages/hal/mips/vr4300/current/src/mips_vr4300.ld +++ b/packages/hal/mips/vr4300/current/src/mips_vr4300.ld @@ -148,6 +148,7 @@ GROUP(libtarget.a libgcc.a) .data _vma_ : _lma_ \ { __ram_data_start = ABSOLUTE (.); \ *(.data*) *(.data1) \ + *( .2ram.*) \ _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ . = ALIGN (8); \
--- a/packages/hal/mips/vrc4373/current/ChangeLog +++ b/packages/hal/mips/vrc4373/current/ChangeLog @@ -1,3 +1,33 @@ +2001-09-07 Nick Garnett <nickg@redhat.com> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Brought up to date and much of + the configury now moved to the VRC437X package. Configury for + Redboot and virtual vectors added here. + + * misc/redboot_RAM.ecm: + * misc/redboot_ROM.ecm: + * misc/redboot_ROMRAM.ecm: + These files added to configure redboot for this target. + + * include/hal_diag.h: + * include/platform.inc: + * include/plf_cache.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/plf_stub.h: + * include/plf_z8530.h: + * misc/stubrom.perm: + * src/hal_diag.c: + * src/platform.S: + * src/plf_misc.c: + * src/plf_stub.c: + * src/pmon.S: + Files removed and relocated to VRC437X package. This package is + now just a configuration and memory layout package. This ChangeLog + is being retained in it original form for archival purposes. + + + 2001-02-26 Jonathan Larmour <jlarmour@redhat.com> * include/platform.inc: Always do unsigned arithmetic on addresses
--- a/packages/hal/mips/vrc4373/current/cdl/hal_mips_vr4300_vrc4373.cdl +++ b/packages/hal/mips/vrc4373/current/cdl/hal_mips_vr4300_vrc4373.cdl @@ -44,20 +44,19 @@ cdl_package CYGPKG_HAL_MIPS_VR4300_VRC43 display "VRC4373 evaluation board" parent CYGPKG_HAL_MIPS requires CYGPKG_HAL_MIPS_VR4300 + requires CYGPKG_HAL_MIPS_VR4300_VRC437X define_header hal_mips_vr4300_vrc4373.h include_dir cyg/hal description " The VRC4373 HAL package should be used when targetting the actual hardware." - compile hal_diag.c plf_misc.c plf_stub.c platform.S pmon.S - - implements CYGINT_HAL_DEBUG_GDB_STUBS - implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mips_vr4300.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_vr4300_vrc4373.h>" + puts $::cdl_header "#include <pkgconf/hal_mips_vr4300_vrc437x.h>" } cdl_component CYG_HAL_STARTUP { @@ -72,58 +71,6 @@ cdl_package CYGPKG_HAL_MIPS_VR4300_VRC43 the system for either RAM bootstrap or ROM bootstrap." } - cdl_option CYGHWR_HAL_MIPS_VR4300_VRC4373_DIAG_PORT { - display "Diagnostic Serial Port" - flavor data - legal_values 0 1 - default_value 0 - description " - The VRC4373 board has two separate serial ports. This option - chooses which of these ports will be used." - } - - cdl_option CYGHWR_HAL_MIPS_VR4300_VRC4373_DIAG_BAUD { - display "Diagnostic Serial Port Baud Rate" - flavor data - legal_values 9600 19200 38400 115200 - default_value 38400 - description " - This option selects the baud rate used for the diagnostic port. - Note: this should match the value chosen for the GDB port if the - diagnostic and GDB port are the same." - } - - cdl_option CYGHWR_HAL_MIPS_VR4300_VRC4373_GDB_PORT { - display "GDB Serial Port" - flavor data - legal_values 0 1 - default_value 0 - description " - The VRC4373 board has two separate serial ports. This option - chooses which of these ports will be used to connect to a host - running GDB." - } - - cdl_option CYGHWR_HAL_MIPS_VR4300_VRC4373_GDB_BAUD { - display "GDB Serial Port Baud Rate" - flavor data - legal_values 9600 19200 38400 115200 - default_value 38400 - description " - This option controls the baud rate used for the GDB connection." - } - - cdl_option CYGSEM_HAL_MIPS_VR4300_VRC4373_DIAG_ACKS_INT_0 { - display "Acknowledge spurious interrupt 0 on output" - default_value 1 - description "When interrupts are disabled for an extended period - of time when outputting packets to GDB, spurious - interrupt 0's can be generated. This option allows - these interrupts to be acknowledged. You should disable - this if you wish to legitimately use interrupt 0." - } - - # Real-time clock/counter specifics cdl_component CYGNUM_HAL_RTC_CONSTANTS { display "Real-time clock constants." @@ -271,7 +218,7 @@ cdl_package CYGPKG_HAL_MIPS_VR4300_VRC43 flavor bool default_value 0 parent CYGPKG_HAL_ROM_MONITOR - requires { CYG_HAL_STARTUP == "ROMRAM" } + requires { CYG_HAL_STARTUP == "ROMRAM" || CYG_HAL_STARTUP == "ROM" } description " Enable this option if this program is to be used as a ROM monitor, i.e. applications will be loaded into RAM on the board, and this @@ -279,4 +226,82 @@ cdl_package CYGPKG_HAL_MIPS_VR4300_VRC43 application. This enables features such as utilizing a separate interrupt stack when exceptions are generated." } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The VRC4373 board has only one serial port. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The VRC4373 board has only one serial port. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + compile -library=libextras.a + + make -priority 325 { + <PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-all $< $(@:.srec=.img) + $(OBJCOPY) -O binary $< $(@:.srec=.bin) + $(OBJCOPY) -O srec $< $@ + } + } + } }
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/hal_diag.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef CYGONCE_HAL_HAL_DIAG_H -#define CYGONCE_HAL_HAL_DIAG_H - -/*============================================================================= -// -// hal_diag.h -// -// HAL Support for Kernel Diagnostic Routines -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg -// Date: 1998-03-02 -// Purpose: HAL Support for Kernel Diagnostic Routines -// Description: Diagnostic routines for use during kernel development. -// Usage: #include <cyg/hal/hal_diag.h> -// -//####DESCRIPTIONEND#### -// -//===========================================================================*/ - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> - -/*---------------------------------------------------------------------------*/ -/* functions implemented in hal_diag.c */ - -externC void hal_diag_init(void); - -externC void hal_diag_write_char(char c); - -externC void hal_diag_read_char(char *c); - -/*---------------------------------------------------------------------------*/ - -#define HAL_DIAG_INIT() hal_diag_init() - -#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) - -#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) - -/*---------------------------------------------------------------------------*/ -/* end of hal_diag.h */ -#endif /* CYGONCE_HAL_HAL_DIAG_H */
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/platform.inc +++ /dev/null @@ -1,646 +0,0 @@ -#ifndef CYGONCE_HAL_PLATFORM_INC -#define CYGONCE_HAL_PLATFORM_INC -##============================================================================= -## -## platform.inc -## -## DDB-VRC4373 board assembler header file -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.1 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://www.redhat.com/ -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): nickg -## Contributors: nickg -## Date: 1999-04-06 -## Purpose: VRC4373 board definitions. -## Description: This file contains various definitions and macros that are -## useful for writing assembly code for the VRC4373 board. -## Usage: -## #include <cyg/hal/platform.inc> -## ... -## -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <cyg/hal/mips.inc> - -##----------------------------------------------------------------------------- -## VRC4372 registers - -#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000 -#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220) - -##----------------------------------------------------------------------------- -## configure the architecture HAL to define the right things. - -## ISR tables are defined in platform.S -#define CYG_HAL_MIPS_ISR_TABLES_DEFINED - -## VSR table is at a fixed RAM address defined by the linker script -#define CYG_HAL_MIPS_VSR_TABLE_DEFINED - -##----------------------------------------------------------------------------- - -#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON) - -## Initial SR value for use with PMON: -## CP0 usable -## Vectors to RAM -## All hw ints disabled -#define INITIAL_SR 0x10000000 - -#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) - -## Initial SR value for use with GDB stubs: -## CP0 and CP1 usable -## FP registers are 64 bit -## Vectors to RAM -## All hw ints disabled -#define INITIAL_SR 0x34000000 - -#else - -## Initial SR value for use standalone: -## CP0 usable -## Vectors to RAM -## All hw ints disabled -#define INITIAL_SR 0x10000000 - -#endif - -#------------------------------------------------------------------------------ -## Load Address and Relocate. This macro is used in code that may be -## linked to execute out of RAM but is actually executed from ROM. The -## code that initializes the memory controller and copies the ROM -## contents to RAM must work in this way, for example. This macro is used -## in place of an "la" macro instruction when loading code and data -## addresses. There are two versions of the macro here. The first -## assumes that we are executing in the ROM space at 0xbfc00000 and are -## linked to run in the RAM space at 0x80000000. It simply adds the -## difference between the two to the loaded address. The second is more -## code, but will execute correctly at either location since it -## calculates the difference at runtime. The second variant is enabled -## by default. - - -#ifdef CYG_HAL_STARTUP_ROMRAM - -#if 0 - .macro lar reg,addr - .set noat - la \reg,\addr - la $at,0x3fc00000 - addu \reg,\reg,$at - .set at - .endm -#else - .macro lar reg,addr - .set noat - move $at,ra # save ra - la \reg,\addr # get address into register - la ra,x\@ # get linked address of label - subiu \reg,\reg,ra # subtract it from value - bal x\@ # branch and link to label - nop # to get current actual address -x\@: - addiu \reg,\reg,ra # add actual address - move ra,$at # restore ra - .set at - .endm - -#endif - -#define CYGPKG_HAL_MIPS_LAR_DEFINED - -#endif - -#------------------------------------------------------------------------------ -# MMU macros. -# The MMU must be set up on this board before we can access any external devices, -# including the memory controller, so we have no RAM to work with yet. -# Since the setup code must work only in registers, we do not do a subroutine -# linkage here, instead the setup code knows to jump back here when finished. - -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) - - .macro hal_mmu_init - .extern hal_mmu_setup - lar k0,hal_mmu_setup - jr k0 - nop - .global hal_mmu_setup_return -hal_mmu_setup_return: - .endm - -#define CYGPKG_HAL_MIPS_MMU_DEFINED - -#endif - -#------------------------------------------------------------------------------ -# MEMC macros. -# - -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) - - .macro hal_memc_init - .extern hal_memc_setup - lar k0,hal_memc_setup - jalr k0 - nop - -#if defined(CYG_HAL_STARTUP_ROMRAM) - # Having got the RAM working, we must now relocate the Entire - # ROM into it and then continue execution from RAM. - - la t0,0x80000000 # dest addr - la t1,0xbfc00000 # source addr - la t3,__ram_data_end # end dest addr -1: - lw v0,0(t1) # get word - addiu t1,t1,4 - sw v0,0(t0) # write word - addiu t0,t0,4 - bne t0,t3,1b - nop - - la v0,2f # RAM address to go to - jr v0 - nop -2: - # We are now executing out of RAM! - -#endif - - .endm - -#define CYGPKG_HAL_MIPS_MEMC_DEFINED - -#endif - -#------------------------------------------------------------------------------ -# Interrupt controller initialization. - - # initialize all interrupts to disabled - .macro hal_intc_init - mfc0 v0,status - nop - la v1,0xFFFF00FF - and v0,v0,v1 # clear the IntMask bits - ori v0,v0,0x3800 # set 3 IPL bits - mtc0 v0,status - nop - nop - nop - # mask them all in the VRC4372 interrupt controller too, - # and write zeros to the status registers to clear any - # pending interrupts. - la v0,CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 - sw zero,0(v0) - sw zero,4(v0) - sw zero,8(v0) - sw zero,12(v0) - sw zero,16(v0) - sw zero,20(v0) - .endm - -#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED - -#------------------------------------------------------------------------------ -# Monitor initialization. - -#ifndef CYGPKG_HAL_MIPS_MON_DEFINED - - - .macro hal_mon_init - - hal_mon_copy_trampoline - - hal_mon_init_vsr_table - - .endm - - -#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON) - - # Copy the other_vector trampoline code into the RAM - # area so we intercept all interrupts. - - .macro hal_mon_copy_trampoline - la a0,other_vector - la a1,other_vector_end - la t0,0xa0000180 -1: - lw v0,0(a0) - sw v0,0(t0) - addiu a0,a0,4 - bne a0,a1,1b - addiu t0,t0,4 - .endm - - - # plant a pointer to the breakpoint springboard into the - # correct vsr table slot. - - .macro hal_mon_init_vsr_table - .extern hal_breakpoint_springboard - la v1,hal_vsr_table - - # Plant the interrupt VSR - la v0,__default_interrupt_vsr - sw v0,(0*4)(v1) - - # And the breakpoint VSR - la v0,hal_breakpoint_springboard - sw v0,(9*4)(v1) - - # Temporarily also plant all the others, so all exceptions - # go to PMON. - sw v0,(4*4)(v1) - sw v0,(5*4)(v1) - sw v0,(6*4)(v1) - sw v0,(7*4)(v1) - sw v0,(8*4)(v1) - sw v0,(10*4)(v1) - sw v0,(11*4)(v1) - sw v0,(12*4)(v1) - sw v0,(13*4)(v1) - sw v0,(14*4)(v1) - sw v0,(15*4)(v1) - - - .endm - -#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) - - # The stubs have a trampoline of their own installed which - # already goes through the VSR table. - - .macro hal_mon_copy_trampoline - .endm - - # plant a pointer to the interrupt VSR handler in the - # correct vsr table slot. Leave the rest for the monitor. - - .macro hal_mon_init_vsr_table - la v0,__default_interrupt_vsr - la v1,hal_vsr_table - sw v0,(0*4)(v1) - - # plant a pointer to our own bus error handler. See the - # comments in platform.S. - .extern hal_bus_error_vsr - la v0,hal_bus_error_vsr - sw v0,(7*4)(v1) - - .endm - -#else - # The other_vector trampoline is already installed as part of - # the executable image. However, the TLB exception is, in RAM - # in the analogous place to the reset vector in ROM. In a - # ROM or ROMRAM startup we need to copy it into place. - -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) - .macro hal_mon_copy_trampoline - la a0,utlb_vector - la a1,utlb_vector_end - la t0,0xa0000000 -1: - lw v0,0(a0) - sw v0,0(t0) - addiu a0,a0,4 - bne a0,a1,1b - addiu t0,t0,4 -#if defined(CYG_HAL_STARTUP_ROM) - la a0,other_vector - la a1,other_vector_end - la t0,0xa0000180 -1: - lw v0,0(a0) - sw v0,0(t0) - addiu a0,a0,4 - bne a0,a1,1b - addiu t0,t0,4 -#endif - .endm -#else - .macro hal_mon_copy_trampoline - .endm -#endif - - # Fill the VSR table with the default VSRs. - # If we contain the stubs, the default VSR will pass - # exceptions on to the stubs. - - .macro hal_mon_init_vsr_table - la v0,__default_exception_vsr - la v1,hal_vsr_table - - sw v0,(1*4)(v1) - sw v0,(2*4)(v1) - sw v0,(3*4)(v1) - sw v0,(4*4)(v1) - sw v0,(5*4)(v1) - sw v0,(6*4)(v1) - sw v0,(7*4)(v1) - sw v0,(8*4)(v1) - sw v0,(9*4)(v1) - sw v0,(10*4)(v1) - sw v0,(11*4)(v1) - sw v0,(12*4)(v1) - sw v0,(13*4)(v1) - sw v0,(14*4)(v1) - sw v0,(15*4)(v1) - sw v0,(23*4)(v1) - sw v0,(24*4)(v1) -# sw v0,(32*4)(v1) # debug - sw v0,(33*4)(v1) # utlb - sw v0,(34*4)(v1) # nmi - - la v0,__default_interrupt_vsr - sw v0,(0*4)(v1) - - .endm - -#endif - - -#define CYGPKG_HAL_MIPS_MON_DEFINED - -#endif - -#------------------------------------------------------------------------------ -# Diagnostic macros - - -#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED - -#if 0 - - # This code generates characters and hex values to a - # Grammar Engine PromICE AI interface. - -#define AILOC 0xbfc70000 - - .macro hal_diag_init - la v0,AILOC -1: - lbu v1,3(v0) - nop ; nop ; nop - subu v1,0xCC - beqz v1,1b - nop - lbu v1,2(v0) - - b 9f - nop - - .global hal_diag_ai_write_char -hal_diag_ai_write_char: - - .set noat - la v0,AILOC # v0 = AI location - -1: - lbu v1,3(v0) # v1 = status register - nop ; nop ; nop - andi v1,v1,1 # v1 = TDA bit - bnez v1,1b # loop while non-zero - nop - - sll a0,a0,1 # a0 = a0<<1 - ori a0,a0,0x0201 # or in start and stop bits - li $at,10 # we have 10 bits to send -2: - andi v1,a0,1 # v1 = ls bit of char - add v1,v0,v1 # v1 = address of ZERO or ONE register - lbu zero,0(v1) # read it to send bit - la v1,100 # delay a bit to let PROMICE deal with it -3: bnez v1,3b # loop while non-zero - add v1,v1,-1 # decrement in delay slot - srl a0,a0,1 # a0 = a0>>1 - subu $at,1 # decrement count - bnez $at,2b # loop while non-zero - nop - - jr ra # all done, return - nop - - .set at - - .global hal_diag_ai_write_hex1 -hal_diag_ai_write_hex1: - la v0,9 - andi a0,a0,0xf - ble a0,v0,1f - nop - addi a0,a0,('A'-'9'-1) -1: addi a0,a0,'0' - b hal_diag_ai_write_char - nop - - .global hal_diag_ai_write_hex2 -hal_diag_ai_write_hex2: - move t0,ra # save ra - move t1,a0 # save arg - srl a0,a0,4 # ms nibble - - bal hal_diag_ai_write_hex1 - nop - - move a0,t1 # retrieve a0 - move ra,t0 # retrieve ra - b hal_diag_ai_write_hex1 - nop - - .global hal_diag_ai_write_hex4 -hal_diag_ai_write_hex4: - move t2,ra # save ra - move t3,a0 # save arg - srl a0,a0,8 # ms byte - - bal hal_diag_ai_write_hex2 - nop - - move a0,t3 # retrieve a0 - move ra,t2 # retrieve ra - b hal_diag_ai_write_hex2 - nop - - - .global hal_diag_ai_write_hex8 -hal_diag_ai_write_hex8: - move t4,ra # save ra - move t5,a0 # save arg - srl a0,a0,16 # ms short - - bal hal_diag_ai_write_hex4 - nop - - move a0,t5 # retrieve a0 - move ra,t4 # retrieve ra - b hal_diag_ai_write_hex4 - nop - - -9: - # Output a '!' to check that the interface is working - - li a0,'!' - bal hal_diag_ai_write_char - nop - - .endm - - # Utility macro to emit a character - .macro hal_diag_writec char - .extern hal_diag_ai_write_char - la a0,\char - lar v0,hal_diag_ai_write_char - jalr v0 -# bal hal_diag_ai_write_char - nop - .endm - -#if 0 - # This macro outputs a '+', the exception number as a - # character offset from 'A' and the exception address - # in hex. - .macro hal_diag_excpt_start - hal_diag_writec '+' - srl k0,k0,2 - addi a0,k0,'A' - jal hal_diag_ai_write_char - nop - move a0,t6 # we know t6 contains the epc value - jal hal_diag_ai_write_hex8 - nop - .endm -#else - .macro hal_diag_excpt_start - .endm -#endif - -#if 0 - # This macro outputs a '=' and the vector number as a - # character offset from 'A'. - .macro hal_diag_intr_start - .extern hal_diag_ai_write_char - hal_diag_writec '=' - addi a0,s2,'A' - jal hal_diag_ai_write_char - nop - .endm -#else - .macro hal_diag_intr_start - .endm -#endif - -#if 0 - .macro hal_diag_restore - hal_diag_writec '^' - lw a0,mipsreg_pc(sp) - lar k0,hal_diag_ai_write_hex8 - jalr k0 - .endm -#else - .macro hal_diag_restore - .endm -#endif - -#define CYGPKG_HAL_MIPS_DIAG_DEFINED - -#elif 0 - -#define DELAY(n) \ - li $at,n; \ -9: bnez $at,9b; \ - subu $at,1; \ - - /* Zilog Access Delay */ -#define DELZ DELAY( (200) ) - - - .macro hal_diag_init - la v0,0xc2000000 - DELZ - lbu v1,8(v0) - andi v1,v1,0xfc - DELZ - sb v1,8(v0) - .endm - - .macro hal_diag_excpt_start - .endm - - .macro hal_diag_intr_start - la v0,0xc2000000 - DELZ - lbu v1,8(v0) - xori v1,v1,0x01 - DELZ - sb v1,8(v0) - .endm - - .macro hal_diag_restore - la v0,0xc2000000 - DELZ - lbu v1,8(v0) - xori v1,v1,0x01 - DELZ - sb v1,8(v0) - -# li a0,0x0310 # a0 = type = INTR,RAISE -# lw a1,mipsreg_sr(sp) # a1 = sr -# mfc0 a2,status -# jal cyg_instrument # call instrument function -# nop - - .endm - -#define CYGPKG_HAL_MIPS_DIAG_DEFINED - - -#endif - -#endif - - - -#------------------------------------------------------------------------------ -#endif // ifndef CYGONCE_HAL_PLATFORM_INC -# end of platform.inc
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/plf_cache.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef CYGONCE_PLF_CACHE_H -#define CYGONCE_PLF_CACHE_H - -//============================================================================= -// -// plf_cache.h -// -// HAL cache control API -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg -// Date: 1998-02-17 -// Purpose: Cache control API -// Description: The macros defined here provide the HAL APIs for handling -// cache control operations. -// Usage: -// #include <cyg/hal/plf_cache.h> -// ... -// -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> -#include <cyg/infra/cyg_type.h> - -#include <cyg/hal/plf_cache.h> - -//============================================================================= - -// Nothing here at present. - -//----------------------------------------------------------------------------- -#endif // ifndef CYGONCE_PLF_CACHE_H -// End of plf_cache.h -
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/plf_intr.h +++ /dev/null @@ -1,290 +0,0 @@ -#ifndef CYGONCE_HAL_PLF_INTR_H -#define CYGONCE_HAL_PLF_INTR_H - -//========================================================================== -// -// plf_intr.h -// -// VRC4373 Interrupt and clock support -// -//========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg, jskov, -// gthomas, jlarmour -// Date: 1999-02-16 -// Purpose: Define Interrupt support -// Description: The macros defined here provide the HAL APIs for handling -// interrupts and the clock for the VRC4373 board. -// -// Usage: -// #include <cyg/hal/plf_intr.h> -// ... -// -// -//####DESCRIPTIONEND#### -// -//========================================================================== - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> - -//-------------------------------------------------------------------------- -// Interrupt controller stuff. - -// The first 6 correspond to the interrupt lines in the status/cause regs -#define CYGNUM_HAL_INTERRUPT_VRC4373 0 -#define CYGNUM_HAL_INTERRUPT_IPL0 1 -#define CYGNUM_HAL_INTERRUPT_IPL1 2 -#define CYGNUM_HAL_INTERRUPT_IPL2 3 -#define CYGNUM_HAL_INTERRUPT_POWER 4 -#define CYGNUM_HAL_INTERRUPT_COMPARE 5 -// The next 32 correspond to the interrupt lines in the 4372 interrupt -// controller. These are decoded from the controller when an interrupt -// on any of the IPL[0:2] lines in signalled. -#define CYGNUM_HAL_INTERRUPT_REALTIME_A 6 -#define CYGNUM_HAL_INTERRUPT_REALTIME_B 7 -#define CYGNUM_HAL_INTERRUPT_DUART 8 -#define CYGNUM_HAL_INTERRUPT_TIMER 9 -#define CYGNUM_HAL_INTERRUPT_PARALLEL 10 -#define CYGNUM_HAL_INTERRUPT_PCI_INTA 11 -#define CYGNUM_HAL_INTERRUPT_PCI_INTB 12 -#define CYGNUM_HAL_INTERRUPT_PCI_INTC 13 -#define CYGNUM_HAL_INTERRUPT_PCI_INTD 14 -#define CYGNUM_HAL_INTERRUPT_INT_9 15 -#define CYGNUM_HAL_INTERRUPT_INT_10 16 -#define CYGNUM_HAL_INTERRUPT_INT_11 17 -#define CYGNUM_HAL_INTERRUPT_INT_12 18 -#define CYGNUM_HAL_INTERRUPT_INT_13 19 -#define CYGNUM_HAL_INTERRUPT_DMA_0 20 -#define CYGNUM_HAL_INTERRUPT_DMA_1 21 -#define CYGNUM_HAL_INTERRUPT_DMA_2 22 -#define CYGNUM_HAL_INTERRUPT_DMA_3 23 -#define CYGNUM_HAL_INTERRUPT_TICK_0 24 -#define CYGNUM_HAL_INTERRUPT_TICK_1 25 -#define CYGNUM_HAL_INTERRUPT_UNUSED_20 26 -#define CYGNUM_HAL_INTERRUPT_UNUSED_21 27 -#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28 -#define CYGNUM_HAL_INTERRUPT_PCI_PERR 29 -#define CYGNUM_HAL_INTERRUPT_PCI_SERR 30 -#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31 -#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32 -#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33 -#define CYGNUM_HAL_INTERRUPT_PCI_ADD 34 -#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35 -#define CYGNUM_HAL_INTERRUPT_UNUSED_30 36 -#define CYGNUM_HAL_INTERRUPT_UNUSED_31 37 - -// Min/Max ISR numbers and how many there are -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX 37 -#define CYGNUM_HAL_ISR_COUNT 38 - -// The vector used by the Real time clock. The default here is to use -// interrupt 5, which is connected to the counter/comparator registers -// in many MIPS variants. - -#ifndef CYGNUM_HAL_INTERRUPT_RTC -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE -#endif - -#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED - -//-------------------------------------------------------------------------- -// controller access code - -#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000 -#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c) -#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220) - -#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF 8 - -// Array which stores the configured priority levels for the configured -// interrupts. -externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; - -#define HAL_INTERRUPT_MASK( _vector_ ) \ -CYG_MACRO_START \ - if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ - { \ - asm volatile ( \ - "mfc0 $3,$12\n" \ - "la $2,0x00000400\n" \ - "sllv $2,$2,%0\n" \ - "nor $2,$2,$0\n" \ - "and $3,$3,$2\n" \ - "mtc0 $3,$12\n" \ - "nop; nop; nop\n" \ - : \ - : "r"(_vector_) \ - : "$2", "$3" \ - ); \ - } \ - else \ - { \ - CYG_WORD32 _mask_; \ - CYG_BYTE _shift_; \ - HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \ - cyg_hal_interrupt_level[_vector_] * \ - CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \ - HAL_READ_UINT32( _maskreg_, _mask_ ); \ - _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ - _mask_ &= ~(1<<_shift_); \ - HAL_WRITE_UINT32( _maskreg_, _mask_ ); \ - } \ -CYG_MACRO_END - -#define HAL_INTERRUPT_UNMASK( _vector_ ) \ -CYG_MACRO_START \ - if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ - { \ - asm volatile ( \ - "mfc0 $3,$12\n" \ - "la $2,0x00000400\n" \ - "sllv $2,$2,%0\n" \ - "or $3,$3,$2\n" \ - "mtc0 $3,$12\n" \ - "nop; nop; nop\n" \ - : \ - : "r"(_vector_) \ - : "$2", "$3" \ - ); \ - } \ - else \ - { \ - CYG_WORD32 _mask_; \ - CYG_BYTE _shift_; \ - HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + \ - cyg_hal_interrupt_level[_vector_] * \ - CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \ - HAL_READ_UINT32( _maskreg_, _mask_ ); \ - _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ - _mask_ |= 1<<_shift_; \ - HAL_WRITE_UINT32( _maskreg_, _mask_ ); \ - } \ -CYG_MACRO_END - -#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ -CYG_MACRO_START \ - CYG_WORD32 _srvector_ = _vector_; \ - if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \ - { \ - CYG_WORD32 _stat_; \ - CYG_BYTE _shift_; \ - HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 +\ - cyg_hal_interrupt_level[_vector_] * \ - CYGHWR_HAL_MIPS_VRC4373_INTC_MASK_OFF; \ - HAL_READ_UINT32( _statreg_, _stat_ ); \ - _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ - _stat_ &= ~(1<<_shift_); \ - HAL_WRITE_UINT32( _statreg_, _stat_ ); \ - _srvector_ = cyg_hal_interrupt_level[_vector_] + \ - CYGNUM_HAL_INTERRUPT_IPL0; \ - } \ - asm volatile ( \ - "mfc0 $3,$13\n" \ - "la $2,0x00000400\n" \ - "sllv $2,$2,%0\n" \ - "nor $2,$2,$0\n" \ - "and $3,$3,$2\n" \ - "mtc0 $3,$13\n" \ - "nop; nop; nop\n" \ - : \ - : "r"(_srvector_) \ - : "$2", "$3" \ - ); \ -CYG_MACRO_END - -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ -CYG_MACRO_START \ - if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \ - (_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \ - { \ - CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \ - CYG_WORD32 pol; \ - CYG_WORD32 trig; \ - HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \ - HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \ - if( _level_ ) \ - { \ - pol &= ~mask; \ - if( _up_ ) trig |= mask; \ - else trig &= ~mask; \ - } \ - else \ - { \ - pol |= mask; \ - if( !(_up_) ) trig |= mask; \ - else trig &= ~mask; \ - } \ - HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_POL, pol ); \ - HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG, trig ); \ - } \ -CYG_MACRO_END - -#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ -CYG_MACRO_START \ - if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \ - { \ - cyg_uint32 _ilevel_ = _level_; \ - while( _ilevel_ > 2 ) _ilevel_ -= 2; \ - cyg_hal_interrupt_level[_vector_] = _ilevel_; \ - } \ -CYG_MACRO_END - -#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED - -//-------------------------------------------------------------------------- -// Control-C support. - -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - -# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART - -externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); - -#define HAL_CTRLC_ISR hal_ctrlc_isr - -#endif - -//---------------------------------------------------------------------------- -// Reset. - -#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT - -//-------------------------------------------------------------------------- -#endif // ifndef CYGONCE_HAL_PLF_INTR_H -// End of plf_intr.h
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/plf_io.h +++ /dev/null @@ -1,215 +0,0 @@ -#ifndef CYGONCE_PLF_IO_H -#define CYGONCE_PLF_IO_H - -//============================================================================= -// -// plf_io.h -// -// Platform specific IO support -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): hmt, jskov, nickg -// Contributors: hmt, jskov, nickg -// Date: 1999-08-09 -// Purpose: VRC4373 PCI IO support macros -// Description: -// Usage: #include <cyg/hal/plf_io.h> -// -// Note: Based on information in -// "VRC4373 System Controller Data Sheet" -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#include <cyg/hal/hal_io.h> // IO macros -#include <cyg/hal/hal_intr.h> // Interrupt vectors - -//----------------------------------------------------------------------------- -// PCI access registers - -#define HAL_PCI_ADDRESS_WINDOW_1 0xAF000014 -#define HAL_PCI_ADDRESS_WINDOW_2 0xAF000018 -#define HAL_PCI_IO_WINDOW 0xAF000024 -#define HAL_PCI_CONFIG_SPACE_DATA 0xAF000028 -#define HAL_PCI_CONFIG_SPACE_ADDR 0xAF00002C -#define HAL_PCI_ENABLE_REG 0xAF000074 - -//----------------------------------------------------------------------------- -// Mappings for PCI memory and IO spaces - -// This is where the PCI spaces are mapped in the CPU's (virtual) -// address space. -#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xC0000000 -#define HAL_PCI_PHYSICAL_IO_BASE 0xAC000000 - -//----------------------------------------------------------------------------- - -// Initialize the PCI bus. -// This has actually already been done by the HAL. -#define HAL_PCI_INIT() - -// Compute address necessary to access PCI config space for the given -// bus and device. -#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \ - ({ \ - cyg_uint32 __addr; \ - cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \ - if (0 == __bus) { \ - __addr = (1 << (__dev+16)); \ - } else { \ - /* We need better info about how to form type 1 addresses */ \ - __addr = 0x800000000 | (__bus << 16) | (__dev << 11); \ - } \ - __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \ - __addr |= (__offset)&~3; \ - __addr; \ - }) - -// The following function allows us to read locations in the PCI config -// space that we are not sure contains a valid device. Support in platform.S -// catches and fixes any bus errors caused. -externC CYG_WORD32 hal_pci_config_read(CYG_ADDRESS addr); -#define HAL_PCI_CONFIG_READ( __addr, __val ) __val = hal_pci_config_read(__addr) - -// Read a value from the PCI configuration space of the appropriate -// size at an address composed from the bus, devfn and offset. -// We can only make 32 bit accesses to the PCI config data register, hence -// all the shifing and masking in these macros. -// Note that we may only use HAL_PCI_CONFIG_READ() here. -#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - CYG_WORD32 _val_; \ - CYG_WORD32 _offset_ = __offset & 3; \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ - __val = (CYG_BYTE)((_val_>>(_offset_*8))&0xFF); \ -CYG_MACRO_END - -#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - CYG_WORD32 _val_; \ - CYG_WORD32 _offset_ = __offset & 2; \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ - __val = (CYG_WORD16)((_val_>>(_offset_*8))&0xFFFF); \ -CYG_MACRO_END - -#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - CYG_WORD32 _val_; \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ - __val = (CYG_WORD32)_val_; \ -CYG_MACRO_END - -// Write a value to the PCI configuration space of the appropriate -// size at an address composed from the bus, devfn and offset. -// We can only make 32 bit accesses to the PCI config data register, hence -// all the shifing and masking in these macros. -// Note that we do not need to use HAL_PCI_CONFIG_READ() here since we -// should not be writing to config space locations that we do not already -// know are valid. -#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - CYG_WORD32 _val_; \ - CYG_WORD32 _offset_ = __offset & 3; \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ - _val_ &= ~(0xFF<<(_offset_*8)); \ - _val_ |= (__val)<<(_offset_*8); \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ -CYG_MACRO_END - -#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - CYG_WORD32 _val_; \ - CYG_WORD32 _offset_ = __offset & 2; \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ - _val_ &= ~(0xFFFF<<(_offset_*8)); \ - _val_ |= (__val)<<(_offset_*8); \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ -CYG_MACRO_END - -#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ -CYG_MACRO_START \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ - HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ - HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, __val); \ -CYG_MACRO_END - - -//----------------------------------------------------------------------------- -// Resources - -// Map PCI device resources starting from these addresses in PCI space. -#define HAL_PCI_ALLOC_BASE_MEMORY 0 -#define HAL_PCI_ALLOC_BASE_IO 0 - -// Translate the PCI interrupt requested by the device (INTA#, INTB#, -// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector). -// We don't actually know what the mappings are at present for this -// board. The following is therefore just a temporary guess until -// we can find out. - -#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \ - CYG_MACRO_START \ - cyg_uint8 __req; \ - HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \ - if (0 != __req) { \ - CYG_ADDRWORD __translation[4] = { \ - CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \ - CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \ - CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \ - CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \ - \ - __vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \ - \ - __valid = true; \ - } else { \ - /* Device will not generate interrupt requests. */ \ - __valid = false; \ - } \ - CYG_MACRO_END - -// Ignore all devices on not on bus 0 since those all seem to map to the -// Nile II controller itself. -#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \ - ((__bus) != 0) - -//----------------------------------------------------------------------------- -// end of plf_io.h -#endif // CYGONCE_PLF_IO_H
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/plf_stub.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef CYGONCE_HAL_PLF_STUB_H -#define CYGONCE_HAL_PLF_STUB_H - -//============================================================================= -// -// plf_stub.h -// -// Platform header for GDB stub support. -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): jskov -// Contributors:jskov -// Date: 1999-02-12 -// Purpose: Platform HAL stub support for MIPS/Vrc4373 boards. -// Usage: #include <cyg/hal/plf_stub.h> -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - -#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM - -#include <cyg/hal/mips-stub.h> // architecture stub support - -//---------------------------------------------------------------------------- -// Define serial stuff. -extern void hal_plf_init_serial( void ); -extern int hal_plf_get_char( void ); -extern void hal_plf_put_char( int c ); - -#define HAL_STUB_PLATFORM_INIT_SERIAL() hal_plf_init_serial() -#define HAL_STUB_PLATFORM_GET_CHAR() hal_plf_get_char() -#define HAL_STUB_PLATFORM_PUT_CHAR(c) hal_plf_put_char((c)) -#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) -#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 -#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT - -//---------------------------------------------------------------------------- -// Stub initializer. - -extern void hal_plf_stub_init(void); - -#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init(); - -#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS -//----------------------------------------------------------------------------- -#endif // CYGONCE_HAL_PLF_STUB_H -// End of plf_stub.h
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/include/plf_z8530.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef CYGONCE_HAL_PLF_Z8530_H -#define CYGONCE_HAL_PLF_Z8530_H - -//============================================================================= -// -// plf_z8530.h -// -// Platform header for Z8530 support. -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors:nickg -// Date: 1999-05-21 -// Purpose: Platform HAL Z8530 support. -// Usage: #include <cyg/hal/plf_z8530.h> -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -/*---------------------------------------------------------------------------*/ -/* Zilog Z8530 access macros. */ - -#if defined(CYGPKG_HAL_MIPS_LSBFIRST) -# define DUART_BASE 0xc1000000 -#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) -# define DUART_BASE 0xc1000003 -#else -#error MIPS endianness not defined by configuration -#endif - -// Address offsets for DUART channels -#define DUART_A 4 -#define DUART_B 0 - -/* Require Delay between Zilog chip (Z8530 and Z8536) register access */ - -//#define ZDEL 66 /* 66 Instructions for 66Mhz */ -#define ZDEL 200 /* 200 Instructions for 133Mhz */ - -#define DELAY_ZACC\ - { register int N = ZDEL; while (--N > 0); } - - -#define HAL_DUART_READ_CR( _chan_, _reg_, _val_) \ -CYG_MACRO_START \ - if( (_reg_) != 0 ) \ - { \ - DELAY_ZACC; \ - HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \ - } \ - DELAY_ZACC; \ - HAL_READ_UINT8( DUART_BASE+(_chan_), _val_ ); \ -CYG_MACRO_END - -#define HAL_DUART_WRITE_CR( _chan_, _reg_, _val_ ) \ -CYG_MACRO_START \ - if( (_reg_) != 0 ) \ - { \ - DELAY_ZACC; \ - HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \ - } \ - DELAY_ZACC; \ - HAL_WRITE_UINT8( DUART_BASE+(_chan_), _val_ ); \ -CYG_MACRO_END - -#define HAL_DUART_WRITE_TR( _chan_, _val_ ) \ -CYG_MACRO_START \ - DELAY_ZACC; \ - HAL_WRITE_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \ -CYG_MACRO_END - -#define HAL_DUART_READ_RR( _chan_, _val_ ) \ -CYG_MACRO_START \ - DELAY_ZACC; \ - HAL_READ_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \ -CYG_MACRO_END - -//----------------------------------------------------------------------------- -#endif // CYGONCE_HAL_PLF_Z8530_H -// End of plf_z8530.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc4373/current/misc/redboot_RAM.ecm @@ -0,0 +1,61 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { +# package CYGPKG_IO_FLASH current ; +# package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +#cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { +# user_value 1 +#}; + +#cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { +# user_value 1 +#}; + +#cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { +# inferred_value 0x1C00000 +#};
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc4373/current/misc/redboot_ROM.ecm @@ -0,0 +1,65 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { +# package CYGPKG_IO_FLASH current ; +# package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +#cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { +# user_value 1 +#}; + +#cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { +# user_value 1 +#}; + +#cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { +# inferred_value 0x1C00000 +#};
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc4373/current/misc/redboot_ROMRAM.ecm @@ -0,0 +1,65 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { +# package CYGPKG_IO_FLASH current ; +# package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +#cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { +# user_value 1 +#}; + +#cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { +# user_value 1 +#}; + +#cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { +# inferred_value 0x1C00000 +#};
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/misc/stubrom.perm +++ /dev/null @@ -1,27 +0,0 @@ -# -# A configuration for building a GDB stub ROM for the DDB-VRC4373 board. -# -# To build the ROMs: -# 1. Create a build directory and cd into it. -# 2. Run: permtest.tcl --srcdir=<sourcedir> <sourcedir>/hal/mips/vrc4373/current/misc/stubrom.perm -# Where <sourcedir> is the path to your source repository. -# 3. Run: make -# 4. Run: make -C hal/common/current/src/stubrom -# -# The file hal/common/current/src/stubrom/stubrom will be an ELF excutable of the ROM. -# Use objcopy to convert this to the appropriate format for your PROM burner. -# Enjoy! -# - -pkgconf --target=mips_vr4300 --platform=vrc4373 --startup=romram --disable-kernel --disable-uitron --disable-libc --disable-libm --disable-io --disable-io_serial --disable-wallclock --disable-watchdog - -header hal.h { - enable CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - enable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT - disable CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT - enable CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT - - enable CYGSEM_HAL_ROM_MONITOR -} - -
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/src/hal_diag.c +++ /dev/null @@ -1,264 +0,0 @@ -/*============================================================================= -// -// hal_diag.c -// -// HAL diagnostic output code -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg -// Date: 1998-03-02 -// Purpose: HAL diagnostic output -// Description: Implementations of HAL diagnostic output support. -// -//####DESCRIPTIONEND#### -// -//===========================================================================*/ - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_arch.h> -#include <cyg/hal/hal_diag.h> - -#include <cyg/hal/hal_intr.h> - -#include <cyg/hal/hal_io.h> - -#include <cyg/hal/plf_z8530.h> - -/*---------------------------------------------------------------------------*/ - -#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) - -#define CYG_KERNEL_DIAG_GDB - -#endif - -#if CYGHWR_HAL_MIPS_VR4300_VRC4373_DIAG_PORT == 0 -#define DUART_CHAN DUART_A -#else -#define DUART_CHAN DUART_B -#endif - -/*---------------------------------------------------------------------------*/ - -extern int pmon_outbyte(char c); -extern int pmon_write( int fd, char *buf, int size); -extern int pmon_open( char *name, int mode, int perms); -extern int pmon_close( int fd ); -extern int pmon_ioctl( int fd, int op, int *argp ); -int fd; - -static unsigned char _diag_init[] = { - 0x00, /* Register 0 */ - 0x00, /* Register 1 - no interrupts */ - 0x00, /* Register 2 */ - 0xC1, /* Register 3 - Rx enable, 8 data */ - 0x44, /* Register 4 - x16 clock, 1 stop, no parity */ - 0x68, /* Register 5 - Tx enable, 8 data */ - 0x00, /* Register 6 */ - 0x00, /* Register 7 */ - 0x00, /* Register 8 */ - 0x00, /* Register 9 */ - 0x00, /* Register 10 */ - 0x56, /* Register 11 - Rx, Tx clocks from baud rate generator */ - 0x00, /* Register 12 - baud rate LSB */ - 0x00, /* Register 13 - baud rate MSB */ - 0x03, /* Register 14 - enable baud rate generator */ - 0x00 /* Register 15 */ -}; - -#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) -#define DUART_CLOCK 4915200 /* Z8530 duart */ -#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ - -void hal_duart_init(void) -{ - unsigned short brg = BRTC(CYGHWR_HAL_MIPS_VR4300_VRC4373_DIAG_BAUD); - int i; -#ifdef CYGSEM_HAL_USE_ROM_MONITOR_PMON - // We close down all of PMON's IO streams. This prevents it - // printing out some silly error messages that are caused by - // us changing the value of the counter/compare registers. By - // default they came out of the debug serial line, disrupting - // GDB session. - pmon_close(0); - pmon_close(1); - pmon_close(2); -// fd = pmon_open( "/dev/tty1", 0 , 0); -// fd = pmon_open( "/dev/tty1", 0 , 0); -// fd = pmon_open( "/dev/tty1", 0 , 0); -#endif - _diag_init[12] = brg & 0xFF; - _diag_init[13] = brg >> 8; - for (i = 1; i < 16; i++) { - HAL_DUART_WRITE_CR(DUART_CHAN, i, _diag_init[i]); - } -} - -/*---------------------------------------------------------------------------*/ - -void hal_duart_write_char(char c) -{ - cyg_uint8 rr0; - do - { - HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); - } while( (rr0 & 0x04) == 0 ); - - HAL_DUART_WRITE_TR( DUART_CHAN, c ); - -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) && \ - defined(CYGHWR_HAL_GDB_PORT_VECTOR) - // Ensure that this write does not provoke a spurious interrupt. - HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR ); -#endif - -} - -/*---------------------------------------------------------------------------*/ - -void hal_duart_read_char(char *c) -{ - cyg_uint8 rr0; - do - { - HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); - } while( (rr0 & 0x01) == 0 ); - - HAL_DUART_READ_RR( DUART_CHAN, *c ); - -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) && \ - defined(CYGHWR_HAL_GDB_PORT_VECTOR) - // Ensure that this read does not provoke a spurious interrupt. - HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR ); -#endif - -} - -/*---------------------------------------------------------------------------*/ - -void hal_diag_init() -{ - hal_duart_init(); -} - -/*---------------------------------------------------------------------------*/ - -extern cyg_bool cyg_hal_is_break(char *buf, int size); -extern void cyg_hal_user_break(CYG_ADDRWORD *regs); - -void hal_diag_write_char(char c) -{ -#ifdef CYG_KERNEL_DIAG_GDB - static char line[100]; - static int pos = 0; - - // No need to send CRs - if( c == '\r' ) return; - - line[pos++] = c; - - if( c == '\n' || pos == sizeof(line) ) - { - - // Disable interrupts. This prevents GDB trying to interrupt us - // while we are in the middle of sending a packet. The serial - // receive interrupt will be seen when we re-enable interrupts - // later. - CYG_INTERRUPT_STATE oldstate; - HAL_DISABLE_INTERRUPTS(oldstate); - - while(1) - { - static char hex[] = "0123456789ABCDEF"; - cyg_uint8 csum = 0; - int i; - char c1; - - hal_duart_write_char('$'); - hal_duart_write_char('O'); - csum += 'O'; - for( i = 0; i < pos; i++ ) - { - char ch = line[i]; - char h = hex[(ch>>4)&0xF]; - char l = hex[ch&0xF]; - hal_duart_write_char(h); - hal_duart_write_char(l); - csum += h; - csum += l; - } - hal_duart_write_char('#'); - hal_duart_write_char(hex[(csum>>4)&0xF]); - hal_duart_write_char(hex[csum&0xF]); - - hal_duart_read_char( &c1 ); - - if( c1 == '+' ) break; - - if( cyg_hal_is_break( &c1 , 1 ) ) - cyg_hal_user_break( NULL ); - - } - - pos = 0; - - // Wait for all data from serial line to drain - // and clear ready-to-send indication. -// hal_diag_drain_serial0(); - - // Disabling the interrupts for an extended period of time - // can provoke a spurious interrupt 0. FIXME - why? -#ifdef CYGSEM_HAL_MIPS_VR4300_VRC4373_DIAG_ACKS_INT_0 - HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_VRC4373 ); -#endif - - // And re-enable interrupts - HAL_RESTORE_INTERRUPTS( oldstate ); - - } -#else - hal_duart_write_char(c); -#endif -} - -/*---------------------------------------------------------------------------*/ - -void hal_diag_read_char(char *c) -{ - hal_duart_read_char(c); -} - -/*---------------------------------------------------------------------------*/ -/* End of hal_diag.c */
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/src/platform.S +++ /dev/null @@ -1,735 +0,0 @@ -##============================================================================= -## -## platform.S -## -## MIPS VRC4372 platform code -## -##============================================================================= -#####COPYRIGHTBEGIN#### -# -# ------------------------------------------- -# The contents of this file are subject to the Red Hat eCos Public License -# Version 1.1 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://www.redhat.com/ -# -# Software distributed under the License is distributed on an "AS IS" -# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -# License for the specific language governing rights and limitations under -# the License. -# -# The Original Code is eCos - Embedded Configurable Operating System, -# released September 30, 1998. -# -# The Initial Developer of the Original Code is Red Hat. -# Portions created by Red Hat are -# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -# All Rights Reserved. -# ------------------------------------------- -# -#####COPYRIGHTEND#### -##============================================================================= -#######DESCRIPTIONBEGIN#### -## -## Author(s): nickg -## Contributors: nickg -## Date: 1999-04-20 -## Purpose: MIPS vrc4372 platform code -## Description: Platform specific code for VRC4372 board. -## -## -## -## -######DESCRIPTIONEND#### -## -##============================================================================= - -#include <pkgconf/system.h> -#include <pkgconf/hal.h> - -#ifdef CYGPKG_KERNEL -# include <pkgconf/kernel.h> -#endif - -#include <cyg/hal/arch.inc> - -##----------------------------------------------------------------------------- -## ISR springboard. -## This routine decodes the interrupt from the VRC4372 interrupt controller -## and vectors to it. - - # On entry: - # a0 = MIPS status register interrupt number (1,2 or 3) - # a1 = ISR data value (= interrupt status reg address) - # a2 = saved reg dump ptr - # s0 = saved reg dump ptr - # s1 = vector table offset - # s2 = interrupt number - # a3,v0,v1 etc available for use - - .text - -hal_isr_springboard: - - lw v0,0(a1) # v0 = stat reg value - - # The following code implements an ls bit index algorithm similar - # to that in hal_lsbit_index() in hal_misc.c. - negu v1,v0 # v1 = -v0 - and v1,v1,v0 # v1 &= v0 [isolate ls bit] - sll v0,v1,16 # v0 = v1<<16 - subu v1,v0,v1 # v1 = v0 - v1 - sll a0,v1,6 # a0 = v1<<6 - addu v1,v1,a0 # v1 += a0 - sll a1,v1,4 # a1 = v1<<4 - addu v1,v1,a1 # v1 += a1 - la v0,hal_isr_springboard_table # v0 = table address - srl v1,v1,26 # v1 = v1>>26 - addu v1,v1,v0 # v1 = table entry address - lb a0,0(v1) # a0 = intc isr number - - addi s2,a0,6 # s2 = eCos isr number - sll s1,s2,2 # s1 = isr table index - - la v1,hal_interrupt_handlers - addu v1,v1,s1 # v1 = isr handler address - lw v1,0(v1) # v1 = isr handler - - la a1,hal_interrupt_data - addu a1,a1,s1 # a1 = address of data ptr - lw a1,0(a1) # a1 = data pointer - - move a0,s2 # pass interrupt number - - jr v1 # jump to handler, return is to - # default vsr already in ra - nop - -hal_isr_springboard_table: - .byte -1, 0, 1, 12, 2, 6, 0, 13 - .byte 3, 0, 7, 0, 0, 0, 0, 14 - .byte 10, 4, 0, 0, 8, 0, 0, 25 - .byte 0, 0, 0, 0, 0, 21, 27, 15 - .byte 31, 11, 5, 0, 0, 0, 0, 0 - .byte 9, 0, 0, 24, 0, 0, 20, 26 - .byte 30, 0, 0, 0, 0, 23, 0, 19 - .byte 29, 0, 22, 18, 28, 17, 16, 0 - -##----------------------------------------------------------------------------- -## Data Load/Store Bus error VSR -## -## If the VRC4373 tries to access a PCI config space register that does -## not have a real device behind it, it provokes a bus error. -## This is a special bus error VSR that detects when we get a bus error -## from a PCI configuration space access and fixes it up to allow the -## program to continue. -## This VSR works in conjunction with hal_pci_config_read(). -## Essentially, if we get a bus error it checks the EPC value and if it -## is at the instruction that accesses the PCI bus, in hal_pci_config_read(), -## it skips it and fixes the registers to allow the program to continue. -## None of this would be necessary if the VRC4373 behaved sensibly and -## returned 0xFFFFFFFF for reads from empty device slots like it should. - - .text - - .globl hal_bus_error_vsr -hal_bus_error_vsr: - # We come here with everything still in registers and: - # K0 = vector number (==7*4) - # K1 = address of this routine - - # Check for special address - - la k1,hal_pci_config_read_load - mvafc0 k0,epc - bne k0,k1,1f - nop - - # We have a match, skip the offending instruction - # and put 0xFFFFFFFF into V0. - # First we must clear the EXL bit so that we can - # write to EPC. - mfc0 k1,status # Get status reg - la v0,0xFFFFFFFD # mask for EXL - and k1,v0,k1 # clear EXL - mtc0 k1,status # return to CP0 - nop # let it work - nop - nop - addi k0,k0,4 # skip offending instruction - mvatc0 k0,epc # return to EPC - nop # let it work - nop - nop - la v0,0xFFFFFFFF # Put 0xFFFFFFFF into v0 - sync # let everything settle - eret # and return - nop - - # If this is not the special location, we need to continue - # with the usual bus error handling. Since we no longer have - # the original VSR table entry, we use the one just before it - # (for instruction fetch bus error). At present this points - # to the same error handler. -1: - la k1,hal_vsr_table # Get VSR table - lw k1,24(k1) # Pick another vector to follow - la k0,28 # but pretend we are still Bus Error - jr k1 # go there - nop - - -##----------------------------------------------------------------------------- -## PCI config space access function -## -## This is the only function that should be used to read data from the PCI -## configuration space data register. It works with the bus error VSR -## above to work around any bus errors provoked by the VRC4373. - -FUNC_START(hal_pci_config_read) - -hal_pci_config_read_load: - .set noreorder - lw v0,0(a0) # Read the value. If this bus-errors the - # handler will skip this instruction and - # put 0xFFFFFFFF into v0. - jr ra # And return - nop - -FUNC_END(hal_pci_config_read) - - -##----------------------------------------------------------------------------- -## Breakpoint springboard - -## The following value has been determined by looking at the code that -## PMON puts in the interrupt vector. Clearly it will be different for -## different versions of PMON. A better approach might be to copy the original -## code out and execute that here. However, there is no guarantee that it is -## position independent. - -#define CYGHWR_MIPS_PMON_EXEPTION_ENTRY 0xa0000dd4 - - .text - - .globl hal_breakpoint_springboard -hal_breakpoint_springboard: - - # We enter here with all of the CPU state still - # in its registers except: - # K0 = vector index - # K1 = address of this function - - la k0,CYGHWR_MIPS_PMON_EXEPTION_ENTRY - jr k0 - nop - -##----------------------------------------------------------------------------- -## ISR tables. - - .extern hal_default_isr - - .data - - .globl hal_interrupt_handlers -hal_interrupt_handlers: - .long hal_default_isr - .long hal_isr_springboard - .long hal_isr_springboard - .long hal_isr_springboard - .long hal_default_isr - .long hal_default_isr - - .rept 32 - .long hal_default_isr - .endr - - .globl hal_interrupt_data -hal_interrupt_data: - - .long 0 - .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 - .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 - .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 - .long 0 - .long 0 - - .rept 32 - .long 0 - .endr - - .globl hal_interrupt_objects -hal_interrupt_objects: - .rept 38 - .long 0 - .endr - - .globl cyg_hal_interrupt_level -cyg_hal_interrupt_level: - .rept 38 - .byte 0 - .endr - -##----------------------------------------------------------------------------- -## MMU setup. -## Much of this code is taken from the PMON sources, hence it does not fully -## conform to our normal coding conventions. - -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) - -## DEFINITIONS FOR THE TLB SUPPORT - -#define IO_PHYSICAL_BASE 0x80000000 -#define IO_VIRTUAL_BASE 0xc0000000 -#define NTLBENTRIES 32 -#define K0BASE 0x80000000 -#define TLBLO_G 0x00000001 -#define TLBLO_V 0x00000002 -#define TLBLO_D 0x00000004 -#define TLBPGMASK_MASK 0x01ffe000 -#define TLBINX_INXMASK 0x0000003f -#define CFG_C_UNCACHED 2 -#define TLBLO_CSHIFT 3 -#define TLBLO_PFNSHIFT 6 -#define TLBLO_PFNMASK 0x3fffffc0 -#define TLBHI_VPN2MASK 0xffffe000 -#define TLBHI_VPN2SHIFT 13 -#define TLBHI_VPNMASK 0xfffff000 -#define TLBHI_VPNSHIFT 12 - - -#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) -#define PAGE_SIZE 0x01000000 -#define PADDR_INC 0x02000000 -#define NUMB_PG 8 - - .text - - .set noreorder - - .extern hal_mmu_setup_return - -FUNC_START(hal_mmu_setup) - - mtc0 zero,tlbhi - nop - li a0,0 -2: - bal resettlb - nop - addiu a0,a0,1 - bne a0,NTLBENTRIES,2b - nop - - -#define tlblo_even s0 -#define tlblo_odd s1 -#define vaddr s2 -#define paddr0 s3 -#define paddr1 s4 -#define pmask s5 -#define tmp s6 -#define ix k1 - - - li ix,0 - li vaddr,IO_VIRTUAL_BASE - li paddr0,IO_PHYSICAL_BASE -loop: - - li a0,((PAGE_SIZE - 1) << 1) - li a1,TLBPGMASK_MASK - and pmask, a0,a1 - - li tlblo_even, TLBLO_V | TLBLO_D | TLBLO_G - li tlblo_odd, TLBLO_V | TLBLO_D | TLBLO_G - - li tmp,PAGE_SIZE - addu paddr1,paddr0,tmp - li tmp,TLBHI_VPN2MASK - and a1,vaddr,tmp - - li tmp,TLBLO_PFNSHIFT - srl a2,paddr0,tmp - li tmp,TLBLO_PFNMASK - and a2,a2,tmp - or a2,a2,TLBLO_UNCACHED - or a2,a2,tlblo_even - - li tmp,TLBLO_PFNSHIFT - srl a3,paddr1,tmp - li tmp,TLBLO_PFNMASK - and a3,a3,tmp - or a3,a3,TLBLO_UNCACHED - or a3,a3,tlblo_odd - - - move a0,pmask - or a0,a0,ix - - bal map_tlb4000 - nop - - addi ix,ix,1 - - li tmp,PADDR_INC - addu vaddr,vaddr,tmp - addu paddr0,paddr0,tmp - - li tmp,NUMB_PG - bne ix,tmp,loop - nop - - # Go back via a jump, not a return - lar k0,hal_mmu_setup_return - jr k0 - nop - -FUNC_END(hal_mmu_setup) - - -## Invalidate the TLB entry specified by index -## -## resettlb(index) -## a0 = index -## -## Uses : t0, t2, v0, a0 - -FUNC_START(resettlb) - - li t2,K0BASE & TLBHI_VPN2MASK - mfc0 t0,tlbhi # save current TLBHI - mfc0 v0,status # save SR and disable interrupts - mtc0 zero,status # clear interrupts - mtc0 t2,tlbhi # invalidate entry - mtc0 zero,tlblo0 - mtc0 zero,tlblo1 - mtc0 a0,index - nop; nop; nop; nop; nop; nop; nop; nop - tlbwi - nop; nop; nop; nop; nop; nop; nop; nop - mtc0 t0,tlbhi - mtc0 v0,status - j ra - nop - -FUNC_END(resettlb) - -## Setup R4000 TLB entry -## -## map_tlb4000(mask_index, tlbhi, pte_even, pte_odd) -## a0 = TLB entry index and page mask -## a1 = virtual page number and PID -## a2 = pte -- contents of even pte -## a3 = pte -- contents of odd pte -## -## -## -## Uses : t0, t1, t2, v0, a0, a1, a2, a3 - -FUNC_START(map_tlb4000) - and t2,a0,TLBPGMASK_MASK - and a0,TLBINX_INXMASK - mfc0 t1,tlbhi # save current TLBPID - mfc0 v0,status # save SR and disable interrupts - mtc0 zero,status # clear interrupts - mtc0 t2,pagemask # set - mtc0 a1,tlbhi # set VPN and TLBPID - mtc0 a2,tlblo0 # set PPN and access bits - mtc0 a3,tlblo1 # set PPN and access bits - mtc0 a0,index # set INDEX to wired entry - nop; nop; nop; nop; nop; nop; nop; nop - tlbwi # drop it in - nop; nop; nop; nop; nop; nop; nop; nop - mtc0 t1,tlbhi # restore TLBPID - mtc0 v0,status # restore SR - j ra - nop -FUNC_END(map_tlb4000) - -#endif - -##----------------------------------------------------------------------------- -## MEMC initialization. -## This also initializes the PCI bus and ISA bus bridge, so at the end of this -## we should have full access to all the memory and devices we need. -## This code is table driven, which is somewhat more compact that coding it all. -## Table entries consist of an address and a value to store in that address. -## A zero address terminates the table. Two special address values modify the -## behaviour: -## DELAY_LOOP loops for the number of iterations in the value field. -## WRITE16 treats the next 2 words as an address and value to be written -## with a 16 bit write cycle. - -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) - -#define DELAY_LOOP 1 -#define WRITE16 2 - - -FUNC_START(hal_memc_setup) - - lar t0,hal_memc_setup_table - la t1,0xbfc00000 - la t2,DELAY_LOOP - la t3,WRITE16 -1: - lw a0,0(t0) # next table entry - lw a1,4(t0) # value to write - addiu t0,8 # go to next entry - beq a0,t2,2f # Check for delay - nop - beq a0,t3,3f # Check for 16 bit write - nop - beqz a0,9f # zero terminates loop - nop - sw a1,0(a0) # write it - lw zero,0(t1) # uncached read to flush write buffer - b 1b - nop -2: - lw zero,0(t1) # uncached read to flush write buffer - bnez a1,2b # count down by value in a1 - addiu a1,-1 # decrement in delay slot - b 1b # go back to loop - nop -3: - lw a3,0(t0) # get next word - addiu t0,4 # skip it - sh a3,0(a1) # store halfword - lw zero,0(t1) # uncached read to flush write buffer - b 1b - nop -9: - jr ra - nop - -FUNC_END(hal_memc_setup) - -##----------------------------------------------------------------------------- -## Definitions for the VRC4373, also known as the Nile I, -## and maybe the Nile III as well. - -#define N1_BASE 0xAF000000 -#define N2_BASE 0xBC000000 - -#define BMCTRL (N1_BASE + 0x00) -#define S1CTRL (N1_BASE + 0x04) -#define S2CTRL (N1_BASE + 0x08) -#define S3CTRL (N1_BASE + 0x0C) -#define S4CTRL (N1_BASE + 0x10) -#define PCIMSTRADDR1 (N1_BASE + 0x14) -#define PCIMSTRADDR2 (N1_BASE + 0x18) -#define PCISLAVADDR1 (N1_BASE + 0x1C) -#define PCISLAVADDR2 (N1_BASE + 0x20) -#define PCIMSTRIO (N1_BASE + 0x24) -#define PCICNFGDATA (N1_BASE + 0x28) -#define PCICNFGADDR (N1_BASE + 0x2C) -#define PCIMBOX1 (N1_BASE + 0x30) -#define PCIMBOX2 (N1_BASE + 0x34) -#define DMACTRL1 (N1_BASE + 0x38) -#define DMALCLADDR1 (N1_BASE + 0x3C) -#define DMAPCIADDR1 (N1_BASE + 0x40) -#define DMACTRL2 (N1_BASE + 0x44) -#define DMALCLADDR2 (N1_BASE + 0x48) -#define DMAPCIADDR2 (N1_BASE + 0x4C) -#define BUSERRSTAT (N1_BASE + 0x50) -#define INTCNTRL (N1_BASE + 0x54) -#define REFRESHRATE (N1_BASE + 0x58) -#define BOOTROMWPRTCT (N1_BASE + 0x5C) -#define PCI_EXCL_ACC (N1_BASE + 0x60) -#define PCI_ENABLE_REG (N1_BASE + 0x74) -#define N3_POM_INIT (N1_BASE + 0x78) -/* -#define N1RESERVED1 (N1_BASE + 0x60) -*/ -#define N1PCIHEADER (N1_BASE + 0x100) -#define N1PCICMD (N1PCIHEADER + 0x04) -#define MBOXPCIADDR (N1PCIHEADER + 0x10) - -#define N1CLSIZE (N1PCIHEADER + 0x0c) /* Cache Line Size */ -#define N1MLTIM (N1PCIHEADER + 0x0d) -#define N1MBADD (N1PCIHEADER + 0x10) -#define N1RSVD2 (N1PCIHEADER + 0x40) /* Word boundary */ -#define N1RTYTIM (N1PCIHEADER + 0x41) - -##----------------------------------------------------------------------------- -## Definitions for the VRC4372, also known as the Nile II. - -#define PCI_N2_DEV 0x00010000 /* PCI Device # - Nile 2 */ - -#define N2CLSIZE ( 0x0c) /* Cache Line Size */ -#define N2IOADD ( 0x14) -#define N2DSCTIM ( 0x40) - -#define IOCON (N2_BASE + 0x0000) - - /* GPIO Bus Controller Registers */ -#define GPDIR (IOCON + 0x0100) -#define GPOUT (IOCON + 0x0104) -#define GPIN (IOCON + 0x0108) - - /* Interrupt Controller Registers */ -#define INTPOL (IOCON + 0x200) -#define INTTRIG (IOCON + 0x204) -#define INTPINS (IOCON + 0x208) -#define INTMASK0 (IOCON + 0x20C) -#define INTSTAT0 (IOCON + 0x210) -#define INTMASK1 (IOCON + 0x214) -#define INTSTAT1 (IOCON + 0x218) -#define INTMASK2 (IOCON + 0x21C) -#define INTSTAT2 (IOCON + 0x220) - - /* IO Bus Controller Registers */ -#if defined(CYGPKG_HAL_MIPS_MSBFIRST) -// The 16 bit registers are swapped pairwise in each word. -#define IOPROF_00 (IOCON + 0x0402) -#define IOPROF_01 (IOCON + 0x0400) -#define IOPROF_02 (IOCON + 0x0406) -#define IOPROF_03 (IOCON + 0x0404) -#define IOPROF_04 (IOCON + 0x040A) -#define IOPROF_05 (IOCON + 0x0408) -#define IOPROF_06 (IOCON + 0x040E) -#define IOPROF_07 (IOCON + 0x040C) -#define IOPROF_08 (IOCON + 0x0412) -#define IOPROF_09 (IOCON + 0x0410) -#define IOPROF_0A (IOCON + 0x0416) -#define IOPROF_0B (IOCON + 0x0414) -#define IOPROF_0C (IOCON + 0x041a) -#define IOPROF_10 (IOCON + 0x0422) -#define IOPROF_11 (IOCON + 0x0420) -#define IOPROF_12 (IOCON + 0x0426) -#define IOPROF_13 (IOCON + 0x0424) -#elif defined(CYGPKG_HAL_MIPS_LSBFIRST) -#define IOPROF_00 (IOCON + 0x0400) -#define IOPROF_01 (IOCON + 0x0402) -#define IOPROF_02 (IOCON + 0x0404) -#define IOPROF_03 (IOCON + 0x0406) -#define IOPROF_04 (IOCON + 0x0408) -#define IOPROF_05 (IOCON + 0x040A) -#define IOPROF_06 (IOCON + 0x040C) -#define IOPROF_07 (IOCON + 0x040E) -#define IOPROF_08 (IOCON + 0x0410) -#define IOPROF_09 (IOCON + 0x0412) -#define IOPROF_0A (IOCON + 0x0414) -#define IOPROF_0B (IOCON + 0x0416) -#define IOPROF_0C (IOCON + 0x0418) -#define IOPROF_10 (IOCON + 0x0420) -#define IOPROF_11 (IOCON + 0x0422) -#define IOPROF_12 (IOCON + 0x0424) -#define IOPROF_13 (IOCON + 0x0426) -#else -#error MIPS endianness not define by configuration -#endif -#define IOTOUT (IOCON + 0x0430) -#define IOPOL (IOCON + 0x0434) - -##----------------------------------------------------------------------------- -## PCI definitions - -#define PCI_IOSPACE_BASE 0x0c /* PCI I/O Space Adr */ - -#define PCIADR_REGNO 0x000000fc /* Register # mask */ - -#define PCI_CONFIG( dev, func, reg ) ( dev | ( reg & PCIADR_REGNO) ) - -#define PCI_COMMAND_STATUS_REG 0x04 -#define PCI_MAP_REG_START 0x10 -#define PCI_INTERRUPT_REG 0x3c - -##----------------------------------------------------------------------------- -## The initialization table - -hal_memc_setup_table: - - .long DELAY_LOOP, 0x00010000 # Wait for HW to settle - - # Set up SDRAM and SIMM1 - .long BMCTRL, 0x0000803b # Base memory setup - .long S1CTRL, 0x0402013f # SIMM1 - - # Set up power-on memory state - .long N3_POM_INIT, 0x00000002 # Power-on memory init - .long DELAY_LOOP, 0x00000100 # wait a bit - .long N3_POM_INIT, 0x00000004 # Power-on memory init - .long DELAY_LOOP, 0x00000100 # wait a bit - .long N3_POM_INIT, 0x00000001 # Power-on memory init - .long DELAY_LOOP, 0x00000100 # wait a bit - .long REFRESHRATE, 0x00000300 # DRAM refresh rate - - .long BOOTROMWPRTCT, 0xffffff3e # Write protect boot ROM - - # Set up PCI master address window - .long PCIMSTRADDR1, 0x1c0fd01c - .long PCIMSTRADDR2, 0x80081080 - - # Set up PCI slave address window - .long PCISLAVADDR1, 0x00081000 - .long PCISLAVADDR2, 0x10081080 - - # Map PCI IO space Phys == Local - .long PCIMSTRIO, (0x000fd000 | ( PCI_IOSPACE_BASE << 24) | PCI_IOSPACE_BASE) - - # VRC4373 Bridge config space - - .long N1PCICMD, 0x00000006 # Memory space enable, bus master - .long N1CLSIZE, 0x00003000 # Master latency time - .long N1MBADD, 0x20000000 # Mailbox base address - .long N1RSVD2, 0x0000f000 # Retry value - - .long PCI_EXCL_ACC, 0x00000020 # PCI exclusive access register - .long PCI_ENABLE_REG, 0x00000005 # PCI config done, enable arbitration - - # Set up 4372. This is configured entirely through its PCI - # configuration space. Hence the following all consist of - # writing an address to the PCICNFGADDR register followed - # by a write of the data to the PCICNFGDATA register. - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_COMMAND_STATUS_REG) - .long PCICNFGDATA, 0x00000146 - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2CLSIZE) - .long PCICNFGDATA, 0x00003000 - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_MAP_REG_START) - .long PCICNFGDATA, 0x1c000000 - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2IOADD) - .long PCICNFGDATA, 0x80000000 - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_INTERRUPT_REG) - .long PCICNFGDATA, 0x00000000 - - .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2DSCTIM) - .long PCICNFGDATA, 0x0070f000 - - # Set up IO bus controller chip select profile registers to - # allow access to the devices. - - .long WRITE16, IOPROF_00, 0x04d1 # RTC - DS1386 - .long WRITE16, IOPROF_01, 0x007f # DUART - Z8530 - .long WRITE16, IOPROF_02, 0x007f # Timer - Z8536 - .long WRITE16, IOPROF_03, 0x00d9 # Parallel = 8255 - .long WRITE16, IOPROF_06, 0x007f # 7 segment display - .long WRITE16, IOPROF_07, 0x007f # 7 segment display - - # Configure the rest of the 4372 - - .long IOTOUT, 0x200003c0 # IO timout control - .long IOPOL, 0x00000000 # IO bus pin polarity - .long GPDIR, 0x000007c0 # GPIO pins 6-10 output - .long INTPOL, 0x00003fff # Interrupt polarity - .long INTTRIG, 0x00003fff # Interrupt trigger - .long INTSTAT0, 0x00000000 # Zero all int status regs - .long INTSTAT1, 0x00000000 - .long INTSTAT2, 0x00000000 - - .long DELAY_LOOP, 0x00010000 # Wait for HW to settle - - .long 0, 0 - -#endif - -##----------------------------------------------------------------------------- -## end of platform.S -
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/src/plf_misc.c +++ /dev/null @@ -1,170 +0,0 @@ -//========================================================================== -// -// plf_misc.c -// -// HAL platform miscellaneous functions -// -//========================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg -// Contributors: nickg, jlarmour -// Date: 1999-01-21 -// Purpose: HAL miscellaneous functions -// Description: This file contains miscellaneous functions provided by the -// HAL. -// -//####DESCRIPTIONEND#### -// -//========================================================================*/ - -#include <pkgconf/hal.h> - -#include <cyg/infra/cyg_type.h> // Base types -#include <cyg/infra/cyg_trac.h> // tracing macros -#include <cyg/infra/cyg_ass.h> // assertion macros - -#include <cyg/hal/hal_arch.h> // architectural definitions - -#include <cyg/hal/hal_intr.h> // Interrupt handling - -#include <cyg/hal/hal_cache.h> // Cache handling - -#include <cyg/hal/plf_z8530.h> - -/*------------------------------------------------------------------------*/ - -void hal_platform_init(void) -{ -#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ - (defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) || \ - defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)) - - { - extern CYG_ADDRESS hal_virtual_vector_table[32]; - void patch_dbg_syscalls( void * ); - patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); - } -#endif -} - -/*------------------------------------------------------------------------*/ -/* Functions to support the detection and execution of a user provoked */ -/* program break. These are usually called from interrupt routines. */ - -cyg_bool cyg_hal_is_break(char *buf, int size) -{ - while( size ) - if( buf[--size] == 0x03 ) return true; - - return false; -} - -void cyg_hal_user_break( CYG_ADDRWORD *regs ) -{ -#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) - // The following code should be at the very start of this function so - // that it can access the RA register before it is saved and reused. - register CYG_WORD32 ra; - asm volatile ( "move %0,$31;" : "=r" (ra) ); - - { - extern CYG_ADDRESS hal_virtual_vector_table[64]; - typedef void install_bpt_fn(void *epc); - CYG_WORD32 pc; - HAL_SavedRegisters *sreg = (HAL_SavedRegisters *)regs; - install_bpt_fn *ibp = (install_bpt_fn *)hal_virtual_vector_table[35]; - - if( regs == NULL ) pc = ra; - else pc = sreg->pc; - - if( ibp != NULL ) ibp((void *)pc); - } - -#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) - - { - extern void breakpoint(void); - breakpoint(); - } - -#else - - HAL_BREAKPOINT(breakinst); - -#endif - -} - -/*------------------------------------------------------------------------*/ -/* Control C ISR support */ - -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - -#if CYGHWR_HAL_MIPS_VR4300_VRC4373_GDB_PORT == 0 -#define DUART_CHAN DUART_A -#else -#define DUART_CHAN DUART_B -#endif - -struct Hal_SavedRegisters *hal_saved_interrupt_state; - -void hal_ctrlc_isr_init(void) -{ - HAL_DUART_WRITE_CR( DUART_CHAN, 1, 0x10 ); - HAL_DUART_WRITE_CR( DUART_CHAN, 9, 0x0a ); - HAL_INTERRUPT_SET_LEVEL( CYGHWR_HAL_GDB_PORT_VECTOR, 0 ); - HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR ); -} - -cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) -{ - - char c; - cyg_uint8 rr0; - - HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR ); - HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); - - // The following return value prevents a spurious interrupt report. - // That is what should happen, but for some reason we get the odd extra - // character when running in the test farm. - - if ( (rr0 & 0x01) == 0 ) return 2; - - HAL_DUART_READ_RR( DUART_CHAN, c ); - - if( cyg_hal_is_break( &c , 1 ) ) - cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state ); - - return 2; -} - -#endif - -/*------------------------------------------------------------------------*/ -/* End of plf_misc.c */
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/src/plf_stub.c +++ /dev/null @@ -1,167 +0,0 @@ -//============================================================================= -// -// plf_stub.c -// -// Platform specific code for GDB stub support. -// -//============================================================================= -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//============================================================================= -//#####DESCRIPTIONBEGIN#### -// -// Author(s): nickg, jskov (based on the old tx39 hal_stub.c) -// Contributors:nickg, jskov -// Date: 1999-02-12 -// Purpose: Platform specific code for GDB stub support. -// -//####DESCRIPTIONEND#### -// -//============================================================================= - -#include <pkgconf/hal.h> - -#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS - -#include <cyg/hal/hal_stub.h> - -#include <cyg/hal/hal_io.h> // HAL IO macros -#include <cyg/hal/hal_diag.h> // diag output. FIXME - -#include <cyg/hal/hal_intr.h> - -#include <cyg/hal/plf_z8530.h> - -/*---------------------------------------------------------------------------*/ - -#if CYGHWR_HAL_MIPS_VR4300_VRC4373_GDB_PORT == 0 -#define DUART_CHAN DUART_A -#else -#define DUART_CHAN DUART_B -#endif - -/*---------------------------------------------------------------------------*/ - -static unsigned char _diag_init[] = { - 0x00, /* Register 0 */ - 0x00, /* Register 1 - no interrupts */ - 0x00, /* Register 2 */ - 0xC1, /* Register 3 - Rx enable, 8 data */ - 0x44, /* Register 4 - x16 clock, 1 stop, no parity */ - 0x68, /* Register 5 - Tx enable, 8 data */ - 0x00, /* Register 6 */ - 0x00, /* Register 7 */ - 0x00, /* Register 8 */ - 0x00, /* Register 9 */ - 0x00, /* Register 10 */ - 0x56, /* Register 11 - Rx, Tx clocks from baud rate generator */ - 0x00, /* Register 12 - baud rate LSB */ - 0x00, /* Register 13 - baud rate MSB */ - 0x03, /* Register 14 - enable baud rate generator */ - 0x00 /* Register 15 */ -}; - -#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) -#define DUART_CLOCK 4915200 /* Z8530 duart */ -#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ - -void hal_plf_init_serial() -{ - unsigned short brg = BRTC(CYGHWR_HAL_MIPS_VR4300_VRC4373_DIAG_BAUD); - int i; - - _diag_init[12] = brg & 0xFF; - _diag_init[13] = brg >> 8; - for (i = 1; i < 16; i++) { - HAL_DUART_WRITE_CR(DUART_CHAN, i, _diag_init[i]); - } -} - -/*---------------------------------------------------------------------------*/ - -void hal_plf_put_char( int c) -{ - cyg_uint8 rr0; - do - { - HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); - } while( (rr0 & 0x04) == 0 ); - - HAL_DUART_WRITE_TR( DUART_CHAN, c ); - - HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_DUART ); -} - -/*---------------------------------------------------------------------------*/ - -int hal_plf_get_char( void ) -{ - char c; - cyg_uint8 rr0; - - do - { - HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); - } while( (rr0 & 0x01) == 0 ); - - HAL_DUART_READ_RR( DUART_CHAN, c ); - - HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_DUART ); - - return c; -} - -//----------------------------------------------------------------------------- -// Stub init - -void hal_plf_stub_init(void) -{ - extern CYG_ADDRESS hal_virtual_vector_table[64]; - extern void init_thread_syscall( void *); - extern void install_async_breakpoint(void *epc); - void (*oldvsr)(void); - extern void __default_exception_vsr(void); - - // Ensure that the breakpoint VSR points to the default VSR. This will pass - // it on to the stubs. - HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, __default_exception_vsr, &oldvsr ); - - // Install async breakpoint handler into vector table. - hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint; - -#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT) - // Only include this code if we do not have a kernel. Otherwise - // the kernel supplies the functionality for the app we are linked - // with. - - // Prepare for application installation of thread info function in - // vector table. - hal_virtual_vector_table[15] = 0; - init_thread_syscall( (void *)&hal_virtual_vector_table[15] ); -#endif -} - -#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS -//----------------------------------------------------------------------------- -// End of plf_stub.c
deleted file mode 100644 --- a/packages/hal/mips/vrc4373/current/src/pmon.S +++ /dev/null @@ -1,267 +0,0 @@ -//======================================================================== -// -// pmon.S -// -// Low-level entry points into PMON monitor. -// -//======================================================================== -//####COPYRIGHTBEGIN#### -// -// ------------------------------------------- -// The contents of this file are subject to the Red Hat eCos Public License -// Version 1.1 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://www.redhat.com/ -// -// Software distributed under the License is distributed on an "AS IS" -// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the -// License for the specific language governing rights and limitations under -// the License. -// -// The Original Code is eCos - Embedded Configurable Operating System, -// released September 30, 1998. -// -// The Initial Developer of the Original Code is Red Hat. -// Portions created by Red Hat are -// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. -// All Rights Reserved. -// ------------------------------------------- -// -//####COPYRIGHTEND#### -//======================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): Red Hat, nickg -// Contributors: Red Hat, nickg -// Date: 1999-04-21 -// Purpose: -// Description: Low-level entry points into PMON monitor. -// Usage: -// -//####DESCRIPTIONEND#### -// -//======================================================================== - - -#ifdef __mips16 -/* This file contains 32 bit assembly code. */ - .set nomips16 -#endif - -#if __mips < 3 - /* This machine does not support 64-bit operations. */ - #define ADDU addu - #define SUBU subu -#else - /* This machine supports 64-bit operations. */ - #define ADDU daddu - #define SUBU dsubu -#endif - - -/* Standard MIPS register names: */ -#define zero $0 -#define z0 $0 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel private register 0 */ -#define k1 $27 /* kernel private register 1 */ -#define gp $28 /* global data pointer */ -#define sp $29 /* stack-pointer */ -#define fp $30 /* frame-pointer */ -#define ra $31 /* return address */ -#define pc $pc /* pc, used on mips16 */ - -#define fp0 $f0 -#define fp1 $f1 - -/* Useful memory constants: */ -#define K0BASE 0x80000000 -#ifndef __mips64 -#define K1BASE 0xA0000000 -#else -#define K1BASE 0xFFFFFFFFA0000000LL -#endif - -#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) - -/* Standard Co-Processor 0 register numbers: */ -#define C0_COUNT $9 /* Count Register */ -#define C0_SR $12 /* Status Register */ -#define C0_CAUSE $13 /* last exception description */ -#define C0_EPC $14 /* Exception error address */ -#define C0_CONFIG $16 /* CPU configuration */ - -/* Standard Status Register bitmasks: */ -#define SR_CU1 0x20000000 /* Mark CP1 as usable */ -#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ -#define SR_BEV 0x00400000 /* Controls location of exception vectors */ -#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ - -#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ -#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ -#define SR_UX 0x00000020 /* User extended addressing enabled */ - -/* Standard (R4000) cache operations. Taken from "MIPS R4000 - Microprocessor User's Manual" 2nd edition: */ - -#define CACHE_I (0) /* primary instruction */ -#define CACHE_D (1) /* primary data */ -#define CACHE_SI (2) /* secondary instruction */ -#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ - -#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ -#define INDEX_LOAD_TAG (1) -#define INDEX_STORE_TAG (2) -#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ -#define HIT_INVALIDATE (4) -#define CACHE_FILL (5) /* CACHE_I only */ -#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ -#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ -#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ - -#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) - -/* Individual cache operations: */ -#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) -#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) -#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) -#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) - -#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) -#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) -#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) -#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) - -#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) -#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) -#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) -#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) - -#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) -#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) - -#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) -#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) -#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) -#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) - -#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) -#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) -#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) - -#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) -#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) -#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) - -#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) -#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) - - .text - .align 2 - -#ifdef LSI - #define PMON_VECTOR 0xffffffffbfc00200 -#else - #define PMON_VECTOR 0xffffffffbfc00500 -#endif - -#ifndef __mips_eabi -/* Provide named functions for entry into the monitor: */ -#define INDIRECT(name,index) \ - .globl name; \ - .ent name; \ - .set noreorder; \ -name: la $2,+(PMON_VECTOR+((index)*4)); \ - lw $2,0($2); \ - j $2; \ - nop; \ - .set reorder; \ - .end name - -#else -#define INDIRECT(name,index) \ - .globl name; \ - .ent name; \ - .set noreorder; \ -name: la $2,+(PMON_VECTOR+((index)*4)); \ - lw $2,0($2); \ - SUBU sp,sp,0x40; \ - sd ra,0x38(sp); \ - sd fp,0x30(sp); \ - jal $2; \ - move fp,sp; \ - ld ra,0x38(sp); \ - ld fp,0x30(sp); \ - j ra; \ - ADDU sp,sp,0x40; \ - .set reorder; \ - .end name -#endif - - -/* The following magic numbers are for the slots into the PMON monitor */ -/* The first are used as the lo-level library run-time: */ -INDIRECT(pmon_read,0) -INDIRECT(pmon_write,1) -INDIRECT(pmon_open,2) -INDIRECT(pmon_close,3) -/* The following are useful monitor routines: */ -INDIRECT(pmon_ioctl,4) -INDIRECT(pmon_printf,5) -INDIRECT(pmon_vsprintf,6) -INDIRECT(pmon_ttctl,7) -INDIRECT(pmon_cliexit,8) -INDIRECT(pmon_getenv,9) -INDIRECT(pmon_onintr,10) -INDIRECT(pmon_flush_cache,11) -INDIRECT(pmon_exception,12) - -/* The following routine is required by the "print()" function: */ - .globl pmon_outbyte - .ent pmon_outbyte - .set noreorder -pmon_outbyte: - subu sp,sp,0x20 /* allocate stack space for string */ - sd ra,0x18(sp) /* stack return address */ - sd fp,0x10(sp) /* stack frame-pointer */ - move fp,sp /* take a copy of the stack pointer */ - /* We leave so much space on the stack for the string (16 - characters), since the call to mon_printf seems to corrupt - the 8bytes at offset 8 into the string/stack. */ - sb a0,0x00(sp) /* character to print */ - sb z0,0x01(sp) /* NUL terminator */ - jal pmon_printf /* and output the string */ - move a0,sp /* take a copy of the string pointer {DELAY SLOT} */ - - move sp,fp /* recover stack pointer */ - ld ra,0x18(sp) /* recover return address */ - ld fp,0x10(sp) /* recover frame-pointer */ - j ra /* return to the caller */ - addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */ - .set reorder - .end pmon_outbyte - -/* EOF pmon.S */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/ChangeLog @@ -0,0 +1,510 @@ +2001-09-07 Nick Garnett <nickg@redhat.com> + + This package is newly created to contain code that is common to + all VRC437X platforms. Most of the contents is derived from the + original VRC4373 package. All ChangeLog entries other than this + one were made when the files were in that package. This ChangeLog + entry describes any major changes that have occured to the files + during the move. + + * include/platform.inc: + Converted INITIAL_SR to INITIAL_SR_PLF to work with architecture + and variant HALs. + + * src/plf_serial.c: File added to implement serial IO in a vector + compatible manner. + + * cdl/hal_mips_vr4300_vrc437x.cdl: Generic configuration for all + targets added. Platform specific configuration moved out to + specific packages. + + * include/hal_diag.h: + * include/plf_cache.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/plf_stub.h: + * include/plf_z8530.h: + * misc/stubrom.perm: + * src/hal_diag.c: + * src/plf_misc.c: + * src/plf_stub.c: + * src/pmon.S: + Files move with minor changes only from original VRC4373 package. + + +2001-02-26 Jonathan Larmour <jlarmour@redhat.com> + + * include/platform.inc: Always do unsigned arithmetic on addresses + * src/platform.S: Ditto + Reported by Chris Morrow <cmorrow@YottaYotta.com> + +2001-02-05 Jesper Skov <jskov@redhat.com> + + * include/plf_io.h: Ignore devices not on bus 0. + +2001-01-31 Nick Garnett <nickg@cygnus.co.uk> + + * src/platform.S: Added *va* (see mips/arch/.../arch.inc) macros + when manipulating values that are potentially 64 bits. + +2001-01-26 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: Reset macros moved + * include/plf_intr.h: to this file. + +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.mlt: + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.mlt: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.mlt: + Add heap1 section + + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.h: + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.h: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.h: + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.ldi: + Regenerated + +2000-09-15 Nick Garnett <nickg@cygnus.co.uk> + + * include/platform.inc: Added some extra ifdefs and code to try + and get ROM startup working. + + * cdl/hal_mips_vr4300_vrc4373.cdl: + Building GDB stubs was requiring ROM startup when it should have + ROMRAM startup. + +2000-08-31 Jonathan Larmour <jlarmour@redhat.com> + + * src/platform.S (hal_pci_config_read): Prevent assembler reordering, + the address is important + +2000-08-16 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.mlt: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.h: + Fixed typo in last change. Forgot that the RAM base address + appears twice in these files. Also fixed .h file to match. + +2000-08-15 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.mlt: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.ldi: + RAM start on these configurations should be 0x80000000 not + 0x80100000. + +2000-05-22 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Removed CTRLC init hacks. + + * src/plf_misc.c (hal_ctrlc_isr_init): Made public. + +2000-05-17 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: Let arch call ctrlc_init. + +2000-02-18 Jonathan Larmour <jlarmour@redhat.co.uk> + + * cdl/hal_mips_vr4300_vrc4373.cdl (CYGBLD_BUILD_GDB_STUBS): When + building stubs, define every dependency required here rather than + in the template + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * include/plf_stub.h: + Removed HAL_STUB_PLATFORM_STUBS_INIT. + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: Removed stubs as a + legal startup type. + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_vr4300_vrc4373.cdl: use cpu options when linking. + +2000-02-03 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Implements stubs. + +2000-01-27 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Moved part of stubs build rule to + common HAL. Changed description. + +2000-01-24 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Add stubs build rule. + +2000-01-24 John Dallaway <jld@cygnus.co.uk> + + * cdl/*.cdl: + + Remove obsolete option CYGTST_TESTING_IDENTIFIER. + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * misc/stubrom.perm: Rename CYG_HAL_ROM_MONITOR -> + CYGSEM_HAL_ROM_MONITOR + + * include/platform.inc: Rename CYG_HAL_USE_ROM_MONITOR_PMON -> + CYGSEM_HAL_USE_ROM_MONITOR_PMON throughout + Rename CYG_HAL_USE_ROM_MONITOR_GDB_STUBS -> + CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs throughout + + * src/hal_diag.c: Likewise + + * src/plf_misc.c: Likewise. Similarly CYG_HAL_USE_ROM_MONITOR_CYGMON + -> CYGSEM_HAL_USE_ROM_MONITOR_CygMon + + * cdl/hal_mips_vr4300_vrc4373.cdl: Add new platform-specific + CYGSEM_HAL_USE_ROM_MONITOR and CYGSEM_HAL_ROM_MONITOR options to + control ROM monitor support + +1999-12-20 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Add -Wl for linker options. + +1999-11-25 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: + Reparent under HAL MIPS variants as for other MIPS targets + +1999-11-25 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_mips_vr4300_vrc4373.cdl: + + Remove references to obsolete 'STUBS' memory layout. + +1999-11-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.h: New file. + + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.mlt: Real file. + + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.h: + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.h: New file(s). + +1999-11-02 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_mips_vr4300_vrc4373.cdl: Added. + +1999-10-29 Nick Garnett <nickg@cygnus.co.uk> + + * include/plf_intr.h: + * src/plf_misc.c: + * src/hal_diag.c: + Changed CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT to + CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT. + +1999-10-05 Nick Garnett <nickg@cygnus.co.uk> + + * src/platform.S: Swapped around the IOPROF registers for + big-endian mode. These 16 bit registers end up in opposite halves + of the 32 bit word in big endian mode. + + * include/plf_z8530.h: In big-endian mode the Z8530 registers are + at the other end of the word. This is easily fixed by redefining + the DUART_BASE only. + +1999-09-14 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): Ack VRC4373 interrupt to + prevent spurious interrupts + * include/pkgconf/hal_mips_vr4300_vrc4373.h: + Add new CYGSEM_HAL_MIPS_VR4300_VRC4373_DIAG_ACKS_INT_0 option to + control the above behaviour + +1999-09-08 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/plf_intr.h (HAL_INTERRUPT_UNMASK): Rephrase to silence warnings + about left-shifting negative numbers. Equivalent when optimized. + (HAL_INTERRUPT_ACKNOWLEDGE): Likewise + (HAL_INTERRUPT_MASK): Likewise + +1999-09-09 Nick Garnett <nickg@cygnus.co.uk> + + * include/platform.inc: Changed end address for copy from + __bss_end to __ram_data_end. + +1999-09-08 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/platform.S (NTLBENTRIES): Fix typo: 0x32 -> 32 + + * include/platform.inc (hal_mon_copy_trampoline): Use branch delay slot + when copying - both for ROMRAM startup and CYG_HAL_USE_ROM_MONITOR_PMON + (hal_mon_init_vsr_table): Don't init debug vector - not used on + vr4300 CPUs + +1999-09-02 Nick Garnett <nickg@cygnus.co.uk> + + * include/platform.inc: Added code to monitor setup to copy + other_vector in to correct RAM location. + +1999-08-19 Nick Garnett <nickg@cygnus.co.uk> + + * include/plf_io.h: Added this file to contain PCI access support. + + * include/platform.inc: + * src/platform.S: + Added function to read data from the PCI data register together + with a data load/store VSR which catches any exceptions and fixes + them up so that the program can continue. + +1999-07-15 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/hal_diag.c: Add prototypes for cyg_hal_is_break and + cyg_hal_user_break to silence warning + +1999-06-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_misc.c (hal_ctrlc_isr): Changed all return codes to 2 so + that the interrupt is reported as handled. + +1999-06-17 Nick Garnett <nickg@cygnus.co.uk> + + * include/platform.inc: Added code to initialize VSR slots for + debug, utlb and nmi vectors. + + * misc/stubrom.perm: Added disable of + CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT when building ROM monitor. + +1999-06-10 Jesper Skov <jskov@cygnus.co.uk> + + * src/plf_stub.c (hal_plf_stub_init): Fix config problem. + +1999-06-10 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_stub.c: Added interrupt acknowledge calls to character + IO routines to prevent spurious interrupts. + +1999-06-08 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_diag.c: Ensure that reads and writes do not provoke + spurious interrupts. + + * include/platform.inc: Tidied up debug version of + hal_diag_intr_start a little. + +1999-05-28 Nick Garnett <nickg@cygnus.co.uk> + + * misc/stubrom.perm: Added this file to contain a permutation for + building a stub ROM for the VRC4373 board. + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: Removed redfinitions + triggered by CYG_HAL_STARTUP_STUBS. + + * include/plf_stub.h: Added HAL_STUB_PLATFORM_INIT and voided + HAL_STUB_PLATFORM_INIT_BREAK_IRQ and HAL_STUB_PLATFORM_STUBS_INIT. + + * src/plf_stub.c: + Moved all setup into hal_plf_stub_init(). Deleted + hal_plf_init_break_irq(). + +1999-05-27 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_stub.c: + Moved Z8530 definitions out to plf_z8530.h. + Added setup of install_async_breakpoint() function is vector + table. + + * src/platform.S: Some minor tidies to the code. + + * src/hal_diag.c: + Moved Z8530 definitions out to plf_z8530.h. + Added modifications for Control-C support - mostly removing some + defunct code. + + * include/plf_z8530.h + Added this file to contain definitions and access macros to the + Z8530 DUART for use in the HAL. + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: Removed some + unnecessary defines. + + * include/plf_intr.h: + * src/plf_misc.c: + Added Control-C support. + + * include/platform.inc: Some minor changes to diagnostic macros. + +1999-05-21 Nick Garnett <nickg@cygnus.co.uk> + + * src/plf_stub.c (hal_plf_init_serial): Tidied away some unused + code. + + * src/platform.S: + Made use of ROMRAM startup option where relevant. + Modified code to be position independent since under ROMRAM + startup it is linked to run in RAM but must actually run in ROM + prior to the copy. + Added some delay loops to try and get the hardware to settle on + startup. Without these the machine sometimes wedges after + power-on. + + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_romram.mlt: + * include/pkgconf/mlt_mips_vr4300_vrc4373_stubs.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_stubs.mlt: + Added these files to support the new startup types. + Note: at present the .mlt files do not match the .ldi files. + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: + Added ROMRAM and STUBS startup options to CDL. Moved default ports + for DIAG and GDB to 0 at 38400 baud. + Added an ifdef to modify the configuration for STUBS startup. + + * include/plf_stub.h: Removed spurious include. + + * include/platform.inc: + Added version of INITIAL_SR for use with GDB stubs. + Added implementation of "lar" macro and converted the relevant + instances of "la" to use it. + Made use of ROMRAM startup option where relevant. + Implemented copy of ROM image to RAM and transfer of control to + it. + Tidied up trampoline copy and VSR table init in monitor init + macros. + Added code to generate messages to the GrammerEngine PromIce AI + interface during initialization. + +1999-05-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_mips_vr4300_vrc4373.h: Move RTC setup here. + +1999-05-13 Nick Garnett <nickg@cygnus.co.uk> + + Imported whole directory tree into main trunk of repository. + +1999-05-11 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.ldi: + Moved RAM and ROM back to their correct addresses. + + * include/pkgconf/hal_vr4300_vrc4373.h: + * include/pkgconf/hal_mips_vr4300_vrc4373.h: + Renamed hal_vr4300_vrc4373.h to match file name synthesized by + pkgconf.tcl. + + * src/hal_diag.c: + * src/plf_stub.c: + Removed explicit include of vrc4372 pkgconf file. + +1999-05-06 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/pkgconf/hal_vr4300_vrc4373.h: Switched initial DIAG and + GDB baud rates to 38400. + + * include/plf_stub.h: + * src/plf_stub.c: + Added hal_plf_stub_init() to initialize the virtual vector table + for thread-aware debugging. + +1999-05-05 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/platform.inc: Added code to plant interrupt VSR in table + when using PMON. + +1999-04-29 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.ldi: + * include/pkgconf/mlt_mips_vr4300_vrc4373_ram.mlt: + Load address moved to 0x80100000, which is the cacheable area (kseg0). + + * include/pkgconf/mlt_mips_vr4300_vrc4373_rom.ldi: For testing + purposes ROM loaded code is put at 0x80680000 and its working RAM + at 0x80600800. These will be moved back to the real addresses when + we can build real ROMs. + The corresponding .mlt file has NOT been changed. + + * src/plf_stub.c (hal_plf_init_serial): Re-enabled initialization + of serial port. + Temporarily made calls to PMON close function unconditional. + + * src/plf_misc.c (hal_platform_init): Added call to + patch_dbg_syscalls(). + + * src/platform.S: Lots of code, tables and definitions added to + initialize the MMU and memory/bus controllers. + + * src/hal_diag.c: Added support for GDB protocol messages. + + * include/platform.inc: Added hal_mmu_init and hal_memc_init + macros. Added code to initialize the VSR table in various + configurations. + +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + [VR4300 branch] + * include/pkgconf/hal_vr4300_vrc4373.h: Default diagnostics on port B. + + * src/hal_diag.c (hal_diag_init): Port initialization was incorrect. + +1999-04-23 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/platform.inc: Added some extra vsr table redirects for + most other exceptions while we are running under PMON. + +1999-04-22 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/plf_stub.h: + * src/plf_stub.c: + * src/PKGconf.mak (COMPILE): + Files added to start work on GDB stub support. + +1999-04-22 Gary Thomas <gthomas@cygnus.co.uk> + + [VR4300 branch] + * src/hal_diag.c: + * include/pkgconf/hal_vr4300_vrc4373.h: Add diag/gdb serial + port configury. + +1999-04-22 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * include/platform.inc: Modified hal_intc_init to always enable + IPL0..2 bits in CP0 status register. + +1999-04-21 Nick Garnett <nickg@cygnus.co.uk> + + [VR4300 branch] + * src/plf_misc.c: Added this file to contain hal_platform_init(). + + * src/pmon.S: Renamed pmon entry functions to avoid clashes with + the C library. Removed unused code. + + * src/platform.S: Added this file. It contains an ISR springboard + routine to decode interrupts via the vrc4372, a breakpoint + springboard to allow breakpoints to continue being handled by + PMON, and board specific versions of the ISR tables. + [later] Fixed a bug in the ISR springboard, added a few comments + too. + + * src/hal_diag.c: Implemented direct-to-hardware diagnostic + output. + + * src/PKGconf.mak (COMPILE): Added platform.S. + Added plf_misc.c. + + * include/plf_intr.h: Added extensive support for vr4372 interrupt + controller. + + * include/platform.inc: Added an initial status register value to + avoid upsetting PMON. Added plant of hal_breakpoint_springboard in + VSR table. Added some diagnostic code to wiggle a led. + Added an implementation of hal_intc_init. Changed initial status + register value. Moved VRC4372 register definitions here. +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/cdl/hal_mips_vr4300_vrc437x.cdl @@ -0,0 +1,69 @@ +# ==================================================================== +# +# hal_mips_vr4300_vrc437x.cdl +# +# VR4300/VRC437x board HAL package configuration data +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: bartv +# Contributors: +# Date: 1999-11-02 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_MIPS_VR4300_VRC437X { + display "VRC437X evaluation board" + parent CYGPKG_HAL_MIPS + requires CYGPKG_HAL_MIPS_VR4300 + define_header hal_mips_vr4300_vrc437x.h + include_dir cyg/hal + description " + The VRC437X HAL package should be used when targetting the + actual hardware." + + compile hal_diag.c plf_misc.c plf_serial.c plf_stub.c platform.S pmon.S + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + + cdl_option CYGSEM_HAL_MIPS_VR4300_VRC437X_DIAG_ACKS_INT_0 { + display "Acknowledge spurious interrupt 0 on output" + default_value 1 + description "When interrupts are disabled for an extended period + of time when outputting packets to GDB, spurious + interrupt 0's can be generated. This option allows + these interrupts to be acknowledged. You should disable + this if you wish to legitimately use interrupt 0." + } + + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/hal_diag.h @@ -0,0 +1,71 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-03-02 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c */ + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/platform.inc @@ -0,0 +1,645 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## DDB-VRC4373 board assembler header file +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-06 +## Purpose: VRC4373 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the VRC4373 board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/mips.inc> + +##----------------------------------------------------------------------------- +## VRC4372 registers + +#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000 +#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c) +#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220) + +##----------------------------------------------------------------------------- +## configure the architecture HAL to define the right things. + +## ISR tables are defined in platform.S +#define CYG_HAL_MIPS_ISR_TABLES_DEFINED + +## VSR table is at a fixed RAM address defined by the linker script +#define CYG_HAL_MIPS_VSR_TABLE_DEFINED + +##----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON) + +## Initial SR value for use with PMON: +## CP0 usable +## Vectors to RAM +## All hw ints disabled +#define INITIAL_SR_PLF 0x10000000 + +#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + +## Initial SR value for use with GDB stubs: +## CP0 and CP1 usable +## FP registers are 64 bit +## Vectors to RAM +## All hw ints disabled +#define INITIAL_SR_PLF 0x34000000 + +#else + +## Initial SR value for use standalone: +## CP0 usable +## Vectors to RAM +## All hw ints disabled +#define INITIAL_SR_PLF 0x10000000 + +#endif + +#------------------------------------------------------------------------------ +## Load Address and Relocate. This macro is used in code that may be +## linked to execute out of RAM but is actually executed from ROM. The +## code that initializes the memory controller and copies the ROM +## contents to RAM must work in this way, for example. This macro is used +## in place of an "la" macro instruction when loading code and data +## addresses. There are two versions of the macro here. The first +## assumes that we are executing in the ROM space at 0xbfc00000 and are +## linked to run in the RAM space at 0x80000000. It simply adds the +## difference between the two to the loaded address. The second is more +## code, but will execute correctly at either location since it +## calculates the difference at runtime. The second variant is enabled +## by default. + + +#ifdef CYG_HAL_STARTUP_ROMRAM + +#if 0 + .macro lar reg,addr + .set noat + la \reg,\addr + la $at,0x3fc00000 + addu \reg,\reg,$at + .set at + .endm +#else + .macro lar reg,addr + .set noat + move $at,ra # save ra + la \reg,\addr # get address into register + la ra,x\@ # get linked address of label + subu \reg,\reg,ra # subtract it from value + bal x\@ # branch and link to label + nop # to get current actual address +x\@: + addu \reg,\reg,ra # add actual address + move ra,$at # restore ra + .set at + .endm + +#endif + +#define CYGPKG_HAL_MIPS_LAR_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# MMU macros. +# The MMU must be set up on this board before we can access any external devices, +# including the memory controller, so we have no RAM to work with yet. +# Since the setup code must work only in registers, we do not do a subroutine +# linkage here, instead the setup code knows to jump back here when finished. + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + + .macro hal_mmu_init + .extern hal_mmu_setup + lar k0,hal_mmu_setup + jr k0 + nop + .global hal_mmu_setup_return +hal_mmu_setup_return: + .endm + +#define CYGPKG_HAL_MIPS_MMU_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# MEMC macros. +# + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + + .macro hal_memc_init + .extern hal_memc_setup + lar k0,hal_memc_setup + jalr k0 + nop + +#if defined(CYG_HAL_STARTUP_ROMRAM) + # Having got the RAM working, we must now relocate the Entire + # ROM into it and then continue execution from RAM. + + la t0,reset_vector # dest addr + lar t1,reset_vector # source addr + la t3,__ram_data_end # end dest addr +1: + lw v0,0(t1) # get word + sw v0,0(t0) # write word + addiu t1,t1,4 + addiu t0,t0,4 + bne t0,t3,1b + nop + + la v0,2f # RAM address to go to + jr v0 + nop +2: + # We are now executing out of RAM! +#endif + + .endm + +#define CYGPKG_HAL_MIPS_MEMC_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Interrupt controller initialization. + + # initialize all interrupts to disabled + .macro hal_intc_init + mfc0 v0,status + nop + la v1,0xFFFF00FF + and v0,v0,v1 # clear the IntMask bits + ori v0,v0,0x3800 # set 3 IPL bits + mtc0 v0,status + nop + nop + nop + # mask them all in the VRC4372 interrupt controller too, + # and write zeros to the status registers to clear any + # pending interrupts. + la v0,CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 + sw zero,0(v0) + sw zero,4(v0) + sw zero,8(v0) + sw zero,12(v0) + sw zero,16(v0) + sw zero,20(v0) + .endm + +#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MIPS_MON_DEFINED + + + .macro hal_mon_init + + hal_mon_copy_trampoline + + hal_mon_init_vsr_table + + .endm + + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON) + + # Copy the other_vector trampoline code into the RAM + # area so we intercept all interrupts. + + .macro hal_mon_copy_trampoline + la a0,other_vector + la a1,other_vector_end + la t0,0xa0000180 +1: + lw v0,0(a0) + sw v0,0(t0) + addiu a0,a0,4 + bne a0,a1,1b + addiu t0,t0,4 + .endm + + + # plant a pointer to the breakpoint springboard into the + # correct vsr table slot. + + .macro hal_mon_init_vsr_table + .extern hal_breakpoint_springboard + la v1,hal_vsr_table + + # Plant the interrupt VSR + la v0,__default_interrupt_vsr + sw v0,(0*4)(v1) + + # And the breakpoint VSR + la v0,hal_breakpoint_springboard + sw v0,(9*4)(v1) + + # Temporarily also plant all the others, so all exceptions + # go to PMON. + sw v0,(4*4)(v1) + sw v0,(5*4)(v1) + sw v0,(6*4)(v1) + sw v0,(7*4)(v1) + sw v0,(8*4)(v1) + sw v0,(10*4)(v1) + sw v0,(11*4)(v1) + sw v0,(12*4)(v1) + sw v0,(13*4)(v1) + sw v0,(14*4)(v1) + sw v0,(15*4)(v1) + + + .endm + +#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + + # The stubs have a trampoline of their own installed which + # already goes through the VSR table. + + .macro hal_mon_copy_trampoline + .endm + + # plant a pointer to the interrupt VSR handler in the + # correct vsr table slot. Leave the rest for the monitor. + + .macro hal_mon_init_vsr_table + la v0,__default_interrupt_vsr + la v1,hal_vsr_table + sw v0,(0*4)(v1) + + # plant a pointer to our own bus error handler. See the + # comments in platform.S. + .extern hal_bus_error_vsr + la v0,hal_bus_error_vsr + sw v0,(7*4)(v1) + + .endm + +#else + # The other_vector trampoline is already installed as part of + # the executable image. However, the TLB exception is, in RAM + # in the analogous place to the reset vector in ROM. In a + # ROM or ROMRAM startup we need to copy it into place. + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + .macro hal_mon_copy_trampoline + la a0,utlb_vector + la a1,utlb_vector_end + la t0,0xa0000000 +1: + lw v0,0(a0) + sw v0,0(t0) + addiu a0,a0,4 + bne a0,a1,1b + addiu t0,t0,4 +#if defined(CYG_HAL_STARTUP_ROM) + la a0,other_vector + la a1,other_vector_end + la t0,0xa0000180 +1: + lw v0,0(a0) + sw v0,0(t0) + addiu a0,a0,4 + bne a0,a1,1b + addiu t0,t0,4 +#endif + .endm +#else + .macro hal_mon_copy_trampoline + .endm +#endif + + # Fill the VSR table with the default VSRs. + # If we contain the stubs, the default VSR will pass + # exceptions on to the stubs. + + .macro hal_mon_init_vsr_table + la v0,__default_exception_vsr + la v1,hal_vsr_table + + sw v0,(1*4)(v1) + sw v0,(2*4)(v1) + sw v0,(3*4)(v1) + sw v0,(4*4)(v1) + sw v0,(5*4)(v1) + sw v0,(6*4)(v1) + sw v0,(7*4)(v1) + sw v0,(8*4)(v1) + sw v0,(9*4)(v1) + sw v0,(10*4)(v1) + sw v0,(11*4)(v1) + sw v0,(12*4)(v1) + sw v0,(13*4)(v1) + sw v0,(14*4)(v1) + sw v0,(15*4)(v1) + sw v0,(23*4)(v1) + sw v0,(24*4)(v1) +# sw v0,(32*4)(v1) # debug + sw v0,(33*4)(v1) # utlb + sw v0,(34*4)(v1) # nmi + + la v0,__default_interrupt_vsr + sw v0,(0*4)(v1) + + .endm + +#endif + + +#define CYGPKG_HAL_MIPS_MON_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Diagnostic macros + + +#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED + +#if 0 + + # This code generates characters and hex values to a + # Grammar Engine PromICE AI interface. + +#define AILOC 0xbfc70000 + + .macro hal_diag_init + la v0,AILOC +1: + lbu v1,3(v0) + nop ; nop ; nop + subu v1,0xCC + beqz v1,1b + nop + lbu v1,2(v0) + + b 9f + nop + + .global hal_diag_ai_write_char +hal_diag_ai_write_char: + + .set noat + la v0,AILOC # v0 = AI location + +1: + lbu v1,3(v0) # v1 = status register + nop ; nop ; nop + andi v1,v1,1 # v1 = TDA bit + bnez v1,1b # loop while non-zero + nop + + sll a0,a0,1 # a0 = a0<<1 + ori a0,a0,0x0201 # or in start and stop bits + li $at,10 # we have 10 bits to send +2: + andi v1,a0,1 # v1 = ls bit of char + add v1,v0,v1 # v1 = address of ZERO or ONE register + lbu zero,0(v1) # read it to send bit + la v1,100 # delay a bit to let PROMICE deal with it +3: bnez v1,3b # loop while non-zero + add v1,v1,-1 # decrement in delay slot + srl a0,a0,1 # a0 = a0>>1 + subu $at,1 # decrement count + bnez $at,2b # loop while non-zero + nop + + jr ra # all done, return + nop + + .set at + + .global hal_diag_ai_write_hex1 +hal_diag_ai_write_hex1: + la v0,9 + andi a0,a0,0xf + ble a0,v0,1f + nop + addi a0,a0,('A'-'9'-1) +1: addi a0,a0,'0' + b hal_diag_ai_write_char + nop + + .global hal_diag_ai_write_hex2 +hal_diag_ai_write_hex2: + move t0,ra # save ra + move t1,a0 # save arg + srl a0,a0,4 # ms nibble + + bal hal_diag_ai_write_hex1 + nop + + move a0,t1 # retrieve a0 + move ra,t0 # retrieve ra + b hal_diag_ai_write_hex1 + nop + + .global hal_diag_ai_write_hex4 +hal_diag_ai_write_hex4: + move t2,ra # save ra + move t3,a0 # save arg + srl a0,a0,8 # ms byte + + bal hal_diag_ai_write_hex2 + nop + + move a0,t3 # retrieve a0 + move ra,t2 # retrieve ra + b hal_diag_ai_write_hex2 + nop + + + .global hal_diag_ai_write_hex8 +hal_diag_ai_write_hex8: + move t4,ra # save ra + move t5,a0 # save arg + srl a0,a0,16 # ms short + + bal hal_diag_ai_write_hex4 + nop + + move a0,t5 # retrieve a0 + move ra,t4 # retrieve ra + b hal_diag_ai_write_hex4 + nop + + +9: + # Output a '!' to check that the interface is working + + li a0,'!' + bal hal_diag_ai_write_char + nop + + .endm + + # Utility macro to emit a character + .macro hal_diag_writec char + .extern hal_diag_ai_write_char + la a0,\char + lar v0,hal_diag_ai_write_char + jalr v0 +# bal hal_diag_ai_write_char + nop + .endm + +#if 0 + # This macro outputs a '+', the exception number as a + # character offset from 'A' and the exception address + # in hex. + .macro hal_diag_excpt_start + hal_diag_writec '+' + srl k0,k0,2 + addi a0,k0,'A' + jal hal_diag_ai_write_char + nop + move a0,t6 # we know t6 contains the epc value + jal hal_diag_ai_write_hex8 + nop + .endm +#else + .macro hal_diag_excpt_start + .endm +#endif + +#if 0 + # This macro outputs a '=' and the vector number as a + # character offset from 'A'. + .macro hal_diag_intr_start + .extern hal_diag_ai_write_char + hal_diag_writec '=' + addi a0,s2,'A' + jal hal_diag_ai_write_char + nop + .endm +#else + .macro hal_diag_intr_start + .endm +#endif + +#if 0 + .macro hal_diag_restore + hal_diag_writec '^' + lw a0,mipsreg_pc(sp) + lar k0,hal_diag_ai_write_hex8 + jalr k0 + .endm +#else + .macro hal_diag_restore + .endm +#endif + +#define CYGPKG_HAL_MIPS_DIAG_DEFINED + +#elif 0 + +#define DELAY(n) \ + li $at,n; \ +9: bnez $at,9b; \ + subu $at,1; \ + + /* Zilog Access Delay */ +#define DELZ DELAY( (200) ) + + + .macro hal_diag_init + la v0,0xc2000000 + DELZ + lbu v1,8(v0) + andi v1,v1,0xfc + DELZ + sb v1,8(v0) + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + la v0,0xc2000000 + DELZ + lbu v1,8(v0) + xori v1,v1,0x01 + DELZ + sb v1,8(v0) + .endm + + .macro hal_diag_restore + la v0,0xc2000000 + DELZ + lbu v1,8(v0) + xori v1,v1,0x01 + DELZ + sb v1,8(v0) + +# li a0,0x0310 # a0 = type = INTR,RAISE +# lw a1,mipsreg_sr(sp) # a1 = sr +# mfc0 a2,status +# jal cyg_instrument # call instrument function +# nop + + .endm + +#define CYGPKG_HAL_MIPS_DIAG_DEFINED + + +#endif + +#endif + + + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/plf_cache.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/plf_intr.h @@ -0,0 +1,292 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// VRC437X Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour +// Date: 1999-02-16 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the VRC437X board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +// Interrupt controller stuff. + +// The first 6 correspond to the interrupt lines in the status/cause regs +#define CYGNUM_HAL_INTERRUPT_VRC437X 0 +#define CYGNUM_HAL_INTERRUPT_IPL0 1 +#define CYGNUM_HAL_INTERRUPT_IPL1 2 +#define CYGNUM_HAL_INTERRUPT_IPL2 3 +#define CYGNUM_HAL_INTERRUPT_POWER 4 +#define CYGNUM_HAL_INTERRUPT_COMPARE 5 +// The next 32 correspond to the interrupt lines in the 4372 interrupt +// controller. These are decoded from the controller when an interrupt +// on any of the IPL[0:2] lines in signalled. +#define CYGNUM_HAL_INTERRUPT_REALTIME_A 6 +#define CYGNUM_HAL_INTERRUPT_REALTIME_B 7 +#define CYGNUM_HAL_INTERRUPT_DUART 8 +#define CYGNUM_HAL_INTERRUPT_TIMER 9 +#define CYGNUM_HAL_INTERRUPT_PARALLEL 10 +#define CYGNUM_HAL_INTERRUPT_PCI_INTA 11 +#define CYGNUM_HAL_INTERRUPT_PCI_INTB 12 +#define CYGNUM_HAL_INTERRUPT_PCI_INTC 13 +#define CYGNUM_HAL_INTERRUPT_PCI_INTD 14 +#define CYGNUM_HAL_INTERRUPT_INT_9 15 +#define CYGNUM_HAL_INTERRUPT_INT_10 16 +#define CYGNUM_HAL_INTERRUPT_INT_11 17 +#define CYGNUM_HAL_INTERRUPT_INT_12 18 +#define CYGNUM_HAL_INTERRUPT_INT_13 19 +#define CYGNUM_HAL_INTERRUPT_DMA_0 20 +#define CYGNUM_HAL_INTERRUPT_DMA_1 21 +#define CYGNUM_HAL_INTERRUPT_DMA_2 22 +#define CYGNUM_HAL_INTERRUPT_DMA_3 23 +#define CYGNUM_HAL_INTERRUPT_TICK_0 24 +#define CYGNUM_HAL_INTERRUPT_TICK_1 25 +#define CYGNUM_HAL_INTERRUPT_UNUSED_20 26 +#define CYGNUM_HAL_INTERRUPT_UNUSED_21 27 +#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28 +#define CYGNUM_HAL_INTERRUPT_PCI_PERR 29 +#define CYGNUM_HAL_INTERRUPT_PCI_SERR 30 +#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31 +#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32 +#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33 +#define CYGNUM_HAL_INTERRUPT_PCI_ADD 34 +#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35 +#define CYGNUM_HAL_INTERRUPT_UNUSED_30 36 +#define CYGNUM_HAL_INTERRUPT_UNUSED_31 37 + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 37 +#define CYGNUM_HAL_ISR_COUNT 38 + +// The vector used by the Real time clock. The default here is to use +// interrupt 5, which is connected to the counter/comparator registers +// in many MIPS variants. + +#ifndef CYGNUM_HAL_INTERRUPT_RTC +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE +#endif + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +//-------------------------------------------------------------------------- +// controller access code + +#define CYGHWR_HAL_MIPS_VRC4372_BASE 0xbc000000 +#define CYGHWR_HAL_MIPS_VRC4372_INTC_POL (CYGHWR_HAL_MIPS_VRC4372_BASE+0x200) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4372_BASE+0x204) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_PINS (CYGHWR_HAL_MIPS_VRC4372_BASE+0x208) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x20c) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x210) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x214) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x218) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x21c) +#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x220) + +#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF 8 + +// Array which stores the configured priority levels for the configured +// interrupts. +externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + +#define HAL_INTERRUPT_MASK( _vector_ ) \ +CYG_MACRO_START \ + if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ + } \ + else \ + { \ + CYG_WORD32 _mask_; \ + CYG_BYTE _shift_; \ + HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \ + cyg_hal_interrupt_level[_vector_] * \ + CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \ + HAL_READ_UINT32( _maskreg_, _mask_ ); \ + _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ + _mask_ &= ~(1<<_shift_); \ + HAL_WRITE_UINT32( _maskreg_, _mask_ ); \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ +CYG_MACRO_START \ + if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "or $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ + } \ + else \ + { \ + CYG_WORD32 _mask_; \ + CYG_BYTE _shift_; \ + HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \ + cyg_hal_interrupt_level[_vector_] * \ + CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \ + HAL_READ_UINT32( _maskreg_, _mask_ ); \ + _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ + _mask_ |= 1<<_shift_; \ + HAL_WRITE_UINT32( _maskreg_, _mask_ ); \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +CYG_MACRO_START \ + CYG_WORD32 _srvector_ = _vector_; \ + if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + CYG_WORD32 _stat_; \ + CYG_BYTE _shift_; \ + HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 +\ + cyg_hal_interrupt_level[_vector_] * \ + CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \ + HAL_READ_UINT32( _statreg_, _stat_ ); \ + _shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \ + _stat_ &= ~(1<<_shift_); \ + HAL_WRITE_UINT32( _statreg_, _stat_ ); \ + _srvector_ = cyg_hal_interrupt_level[_vector_] + \ + CYGNUM_HAL_INTERRUPT_IPL0; \ + } \ + asm volatile ( \ + "mfc0 $3,$13\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$13\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_srvector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ +CYG_MACRO_START \ + if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \ + (_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \ + { \ + CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \ + CYG_WORD32 pol; \ + CYG_WORD32 trig; \ + HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \ + HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \ + if( _level_ ) \ + { \ + pol &= ~mask; \ + if( _up_ ) trig |= mask; \ + else trig &= ~mask; \ + } \ + else \ + { \ + pol |= mask; \ + if( !(_up_) ) trig |= mask; \ + else trig &= ~mask; \ + } \ + HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \ + HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ +CYG_MACRO_START \ + if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \ + { \ + cyg_uint32 _ilevel_ = _level_; \ + while( _ilevel_ > 2 ) _ilevel_ -= 2; \ + cyg_hal_interrupt_level[_vector_] = _ilevel_; \ + } \ +CYG_MACRO_END + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +//-------------------------------------------------------------------------- +// Control-C support. + +#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) + +# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART + +externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_CTRLC_ISR hal_ctrlc_isr + +#endif + +//---------------------------------------------------------------------------- +// Reset. + +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000 + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/plf_io.h @@ -0,0 +1,215 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt, jskov, nickg +// Contributors: hmt, jskov, nickg +// Date: 1999-08-09 +// Purpose: VRC4373 PCI IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +// Note: Based on information in +// "VRC4373 System Controller Data Sheet" +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_intr.h> // Interrupt vectors + +//----------------------------------------------------------------------------- +// PCI access registers + +#define HAL_PCI_ADDRESS_WINDOW_1 0xAF000014 +#define HAL_PCI_ADDRESS_WINDOW_2 0xAF000018 +#define HAL_PCI_IO_WINDOW 0xAF000024 +#define HAL_PCI_CONFIG_SPACE_DATA 0xAF000028 +#define HAL_PCI_CONFIG_SPACE_ADDR 0xAF00002C +#define HAL_PCI_ENABLE_REG 0xAF000074 + +//----------------------------------------------------------------------------- +// Mappings for PCI memory and IO spaces + +// This is where the PCI spaces are mapped in the CPU's (virtual) +// address space. +#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xC0000000 +#define HAL_PCI_PHYSICAL_IO_BASE 0xAC000000 + +//----------------------------------------------------------------------------- + +// Initialize the PCI bus. +// This has actually already been done by the HAL. +#define HAL_PCI_INIT() + +// Compute address necessary to access PCI config space for the given +// bus and device. +#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \ + ({ \ + cyg_uint32 __addr; \ + cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \ + if (0 == __bus) { \ + __addr = (1 << (__dev+16)); \ + } else { \ + /* We need better info about how to form type 1 addresses */ \ + __addr = 0x800000000 | (__bus << 16) | (__dev << 11); \ + } \ + __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \ + __addr |= (__offset)&~3; \ + __addr; \ + }) + +// The following function allows us to read locations in the PCI config +// space that we are not sure contains a valid device. Support in platform.S +// catches and fixes any bus errors caused. +externC CYG_WORD32 hal_pci_config_read(CYG_ADDRESS addr); +#define HAL_PCI_CONFIG_READ( __addr, __val ) __val = hal_pci_config_read(__addr) + +// Read a value from the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +// We can only make 32 bit accesses to the PCI config data register, hence +// all the shifing and masking in these macros. +// Note that we may only use HAL_PCI_CONFIG_READ() here. +#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + CYG_WORD32 _val_; \ + CYG_WORD32 _offset_ = __offset & 3; \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ + __val = (CYG_BYTE)((_val_>>(_offset_*8))&0xFF); \ +CYG_MACRO_END + +#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + CYG_WORD32 _val_; \ + CYG_WORD32 _offset_ = __offset & 2; \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ + __val = (CYG_WORD16)((_val_>>(_offset_*8))&0xFFFF); \ +CYG_MACRO_END + +#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + CYG_WORD32 _val_; \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ + __val = (CYG_WORD32)_val_; \ +CYG_MACRO_END + +// Write a value to the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +// We can only make 32 bit accesses to the PCI config data register, hence +// all the shifing and masking in these macros. +// Note that we do not need to use HAL_PCI_CONFIG_READ() here since we +// should not be writing to config space locations that we do not already +// know are valid. +#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + CYG_WORD32 _val_; \ + CYG_WORD32 _offset_ = __offset & 3; \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ + _val_ &= ~(0xFF<<(_offset_*8)); \ + _val_ |= (__val)<<(_offset_*8); \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ +CYG_MACRO_END + +#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + CYG_WORD32 _val_; \ + CYG_WORD32 _offset_ = __offset & 2; \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ + _val_ &= ~(0xFFFF<<(_offset_*8)); \ + _val_ |= (__val)<<(_offset_*8); \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \ +CYG_MACRO_END + +#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ +CYG_MACRO_START \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \ + HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \ + HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, __val); \ +CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// Resources + +// Map PCI device resources starting from these addresses in PCI space. +#define HAL_PCI_ALLOC_BASE_MEMORY 0 +#define HAL_PCI_ALLOC_BASE_IO 0 + +// Translate the PCI interrupt requested by the device (INTA#, INTB#, +// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector). +// We don't actually know what the mappings are at present for this +// board. The following is therefore just a temporary guess until +// we can find out. + +#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \ + CYG_MACRO_START \ + cyg_uint8 __req; \ + HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \ + if (0 != __req) { \ + CYG_ADDRWORD __translation[4] = { \ + CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \ + CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \ + CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \ + CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \ + \ + __vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \ + \ + __valid = true; \ + } else { \ + /* Device will not generate interrupt requests. */ \ + __valid = false; \ + } \ + CYG_MACRO_END + +// Ignore all devices on not on bus 0 since those all seem to map to the +// Nile II controller itself. +#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \ + ((__bus) != 0) + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/plf_stub.h @@ -0,0 +1,78 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-02-12 +// Purpose: Platform HAL stub support for MIPS/Vrc4373 boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/mips-stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define serial stuff. +extern void cyg_hal_plf_comms_init( void ); +extern cyg_uint8 cyg_hal_plf_serial_getc( void *chan ); +extern void cyg_hal_plf_serial_putc( void *chan, cyg_uint8 c ); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() +#define HAL_STUB_PLATFORM_GET_CHAR() cyg_hal_plf_serial_getc(0) +#define HAL_STUB_PLATFORM_PUT_CHAR(c) cyg_hal_plf_serial_putc(0,(c)) +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +extern void hal_plf_stub_init(void); + +#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init(); + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/include/plf_z8530.h @@ -0,0 +1,109 @@ +#ifndef CYGONCE_HAL_PLF_Z8530_H +#define CYGONCE_HAL_PLF_Z8530_H + +//============================================================================= +// +// plf_z8530.h +// +// Platform header for Z8530 support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 1999-05-21 +// Purpose: Platform HAL Z8530 support. +// Usage: #include <cyg/hal/plf_z8530.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +/*---------------------------------------------------------------------------*/ +/* Zilog Z8530 access macros. */ + +#if defined(CYGPKG_HAL_MIPS_LSBFIRST) +# define DUART_BASE 0xc1000000 +#elif defined(CYGPKG_HAL_MIPS_MSBFIRST) +# define DUART_BASE 0xc1000003 +#else +#error MIPS endianness not defined by configuration +#endif + +// Address offsets for DUART channels +#define DUART_A 4 +#define DUART_B 0 + +/* Require Delay between Zilog chip (Z8530 and Z8536) register access */ + +//#define ZDEL 66 /* 66 Instructions for 66Mhz */ +#define ZDEL 200 /* 200 Instructions for 133Mhz */ + +#define DELAY_ZACC\ + { register int N = ZDEL; while (--N > 0); } + + +#define HAL_DUART_READ_CR( _chan_, _reg_, _val_) \ +CYG_MACRO_START \ + if( (_reg_) != 0 ) \ + { \ + DELAY_ZACC; \ + HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \ + } \ + DELAY_ZACC; \ + HAL_READ_UINT8( DUART_BASE+(_chan_), _val_ ); \ +CYG_MACRO_END + +#define HAL_DUART_WRITE_CR( _chan_, _reg_, _val_ ) \ +CYG_MACRO_START \ + if( (_reg_) != 0 ) \ + { \ + DELAY_ZACC; \ + HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \ + } \ + DELAY_ZACC; \ + HAL_WRITE_UINT8( DUART_BASE+(_chan_), _val_ ); \ +CYG_MACRO_END + +#define HAL_DUART_WRITE_TR( _chan_, _val_ ) \ +CYG_MACRO_START \ + DELAY_ZACC; \ + HAL_WRITE_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \ +CYG_MACRO_END + +#define HAL_DUART_READ_RR( _chan_, _val_ ) \ +CYG_MACRO_START \ + DELAY_ZACC; \ + HAL_READ_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \ +CYG_MACRO_END + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_Z8530_H +// End of plf_z8530.h
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/misc/stubrom.perm @@ -0,0 +1,27 @@ +# +# A configuration for building a GDB stub ROM for the DDB-VRC4373 board. +# +# To build the ROMs: +# 1. Create a build directory and cd into it. +# 2. Run: permtest.tcl --srcdir=<sourcedir> <sourcedir>/hal/mips/vrc4373/current/misc/stubrom.perm +# Where <sourcedir> is the path to your source repository. +# 3. Run: make +# 4. Run: make -C hal/common/current/src/stubrom +# +# The file hal/common/current/src/stubrom/stubrom will be an ELF excutable of the ROM. +# Use objcopy to convert this to the appropriate format for your PROM burner. +# Enjoy! +# + +pkgconf --target=mips_vr4300 --platform=vrc4373 --startup=romram --disable-kernel --disable-uitron --disable-libc --disable-libm --disable-io --disable-io_serial --disable-wallclock --disable-watchdog + +header hal.h { + enable CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + enable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + disable CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT + enable CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + + enable CYGSEM_HAL_ROM_MONITOR +} + +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/hal_diag.c @@ -0,0 +1,158 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_stub.h> + + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + +#define CYG_KERNEL_DIAG_GDB + +#endif + +/*---------------------------------------------------------------------------*/ + +void hal_diag_init() +{ + cyg_hal_plf_comms_init(); +} + +/*---------------------------------------------------------------------------*/ + +void hal_diag_write_char(char c) +{ +#ifdef CYG_KERNEL_DIAG_GDB + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + CYG_INTERRUPT_STATE oldstate; + HAL_DISABLE_INTERRUPTS(oldstate); + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + cyg_hal_plf_serial_putc(NULL, '$'); + cyg_hal_plf_serial_putc(NULL, 'O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + cyg_hal_plf_serial_putc(NULL, h); + cyg_hal_plf_serial_putc(NULL, l); + csum += h; + csum += l; + } + cyg_hal_plf_serial_putc(NULL, '#'); + cyg_hal_plf_serial_putc(NULL, hex[(csum>>4)&0xF]); + cyg_hal_plf_serial_putc(NULL, hex[csum&0xF]); + + c1 = cyg_hal_plf_serial_getc( NULL ); + + if( c1 == '+' ) break; + + if( cyg_hal_is_break( &c1 , 1 ) ) + cyg_hal_user_break( NULL ); + + } + + pos = 0; + + // Wait for all data from serial line to drain + // and clear ready-to-send indication. +// hal_diag_drain_serial0(); + + // Disabling the interrupts for an extended period of time + // can provoke a spurious interrupt 0. FIXME - why? +#ifdef CYGSEM_HAL_MIPS_VR4300_VRC437X_DIAG_ACKS_INT_0 + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_VRC437X ); +#endif + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS( oldstate ); + + } +#else + cyg_hal_plf_serial_putc(NULL, c); +#endif +} + +/*---------------------------------------------------------------------------*/ + +void hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(NULL); +} + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/platform.S @@ -0,0 +1,765 @@ +##============================================================================= +## +## platform.S +## +## MIPS VRC4372 platform code +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: nickg +## Date: 1999-04-20 +## Purpose: MIPS vrc4372 platform code +## Description: Platform specific code for VRC4372 board. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- +## ISR springboard. +## This routine decodes the interrupt from the VRC4372 interrupt controller +## and vectors to it. + + # On entry: + # a0 = MIPS status register interrupt number (1,2 or 3) + # a1 = ISR data value (= interrupt status reg address) + # a2 = saved reg dump ptr + # s0 = saved reg dump ptr + # s1 = vector table offset + # s2 = interrupt number + # a3,v0,v1 etc available for use + + .text + +hal_isr_springboard: + + lw v0,0(a1) # v0 = stat reg value + + # The following code implements an ls bit index algorithm similar + # to that in hal_lsbit_index() in hal_misc.c. + negu v1,v0 # v1 = -v0 + and v1,v1,v0 # v1 &= v0 [isolate ls bit] + sll v0,v1,16 # v0 = v1<<16 + subu v1,v0,v1 # v1 = v0 - v1 + sll a0,v1,6 # a0 = v1<<6 + addu v1,v1,a0 # v1 += a0 + sll a1,v1,4 # a1 = v1<<4 + addu v1,v1,a1 # v1 += a1 + la v0,hal_isr_springboard_table # v0 = table address + srl v1,v1,26 # v1 = v1>>26 + addu v1,v1,v0 # v1 = table entry address + lb a0,0(v1) # a0 = intc isr number + + addi s2,a0,6 # s2 = eCos isr number + sll s1,s2,2 # s1 = isr table index + + la v1,hal_interrupt_handlers + addu v1,v1,s1 # v1 = isr handler address + lw v1,0(v1) # v1 = isr handler + + la a1,hal_interrupt_data + addu a1,a1,s1 # a1 = address of data ptr + lw a1,0(a1) # a1 = data pointer + + move a0,s2 # pass interrupt number + + jr v1 # jump to handler, return is to + # default vsr already in ra + nop + +hal_isr_springboard_table: + .byte -1, 0, 1, 12, 2, 6, 0, 13 + .byte 3, 0, 7, 0, 0, 0, 0, 14 + .byte 10, 4, 0, 0, 8, 0, 0, 25 + .byte 0, 0, 0, 0, 0, 21, 27, 15 + .byte 31, 11, 5, 0, 0, 0, 0, 0 + .byte 9, 0, 0, 24, 0, 0, 20, 26 + .byte 30, 0, 0, 0, 0, 23, 0, 19 + .byte 29, 0, 22, 18, 28, 17, 16, 0 + +##----------------------------------------------------------------------------- +## Data Load/Store Bus error VSR +## +## If the VRC4373 tries to access a PCI config space register that does +## not have a real device behind it, it provokes a bus error. +## This is a special bus error VSR that detects when we get a bus error +## from a PCI configuration space access and fixes it up to allow the +## program to continue. +## This VSR works in conjunction with hal_pci_config_read(). +## Essentially, if we get a bus error it checks the EPC value and if it +## is at the instruction that accesses the PCI bus, in hal_pci_config_read(), +## it skips it and fixes the registers to allow the program to continue. +## None of this would be necessary if the VRC4373 behaved sensibly and +## returned 0xFFFFFFFF for reads from empty device slots like it should. + + .text + + .globl hal_bus_error_vsr +hal_bus_error_vsr: + # We come here with everything still in registers and: + # K0 = vector number (==7*4) + # K1 = address of this routine + + # Check for special address + + la k1,hal_pci_config_read_load + mvafc0 k0,epc + bne k0,k1,1f + nop + + # We have a match, skip the offending instruction + # and put 0xFFFFFFFF into V0. + # First we must clear the EXL bit so that we can + # write to EPC. + mfc0 k1,status # Get status reg + la v0,0xFFFFFFFD # mask for EXL + and k1,v0,k1 # clear EXL + mtc0 k1,status # return to CP0 + nop # let it work + nop + nop + addi k0,k0,4 # skip offending instruction + mvatc0 k0,epc # return to EPC + nop # let it work + nop + nop + la v0,0xFFFFFFFF # Put 0xFFFFFFFF into v0 + sync # let everything settle + eret # and return + nop + + # If this is not the special location, we need to continue + # with the usual bus error handling. Since we no longer have + # the original VSR table entry, we use the one just before it + # (for instruction fetch bus error). At present this points + # to the same error handler. +1: + la k1,hal_vsr_table # Get VSR table + lw k1,24(k1) # Pick another vector to follow + la k0,28 # but pretend we are still Bus Error + jr k1 # go there + nop + + +##----------------------------------------------------------------------------- +## PCI config space access function +## +## This is the only function that should be used to read data from the PCI +## configuration space data register. It works with the bus error VSR +## above to work around any bus errors provoked by the VRC4373. + +FUNC_START(hal_pci_config_read) + +hal_pci_config_read_load: + .set noreorder + lw v0,0(a0) # Read the value. If this bus-errors the + # handler will skip this instruction and + # put 0xFFFFFFFF into v0. + jr ra # And return + nop + +FUNC_END(hal_pci_config_read) + + +##----------------------------------------------------------------------------- +## Breakpoint springboard + +## The following value has been determined by looking at the code that +## PMON puts in the interrupt vector. Clearly it will be different for +## different versions of PMON. A better approach might be to copy the original +## code out and execute that here. However, there is no guarantee that it is +## position independent. + +#define CYGHWR_MIPS_PMON_EXEPTION_ENTRY 0xa0000dd4 + + .text + + .globl hal_breakpoint_springboard +hal_breakpoint_springboard: + + # We enter here with all of the CPU state still + # in its registers except: + # K0 = vector index + # K1 = address of this function + + la k0,CYGHWR_MIPS_PMON_EXEPTION_ENTRY + jr k0 + nop + +##----------------------------------------------------------------------------- +## ISR tables. + + .extern hal_default_isr + + .data + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_isr + .long hal_isr_springboard + .long hal_isr_springboard + .long hal_isr_springboard + .long hal_default_isr + .long hal_default_isr + + .rept 32 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + + .long 0 + .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 + .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 + .long CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 + .long 0 + .long 0 + + .rept 32 + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept 38 + .long 0 + .endr + + .globl cyg_hal_interrupt_level +cyg_hal_interrupt_level: + .rept 38 + .byte 0 + .endr + +##----------------------------------------------------------------------------- +## MMU setup. +## Much of this code is taken from the PMON sources, hence it does not fully +## conform to our normal coding conventions. + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + +## DEFINITIONS FOR THE TLB SUPPORT + +#define IO_PHYSICAL_BASE 0x80000000 +#define IO_VIRTUAL_BASE 0xc0000000 +#define NTLBENTRIES 32 +#define K0BASE 0x80000000 +#define TLBLO_G 0x00000001 +#define TLBLO_V 0x00000002 +#define TLBLO_D 0x00000004 +#define TLBPGMASK_MASK 0x01ffe000 +#define TLBINX_INXMASK 0x0000003f +#define CFG_C_UNCACHED 2 +#define TLBLO_CSHIFT 3 +#define TLBLO_PFNSHIFT 6 +#define TLBLO_PFNMASK 0x3fffffc0 +#define TLBHI_VPN2MASK 0xffffe000 +#define TLBHI_VPN2SHIFT 13 +#define TLBHI_VPNMASK 0xfffff000 +#define TLBHI_VPNSHIFT 12 + + +#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) +#define PAGE_SIZE 0x01000000 +#define PADDR_INC 0x02000000 +#define NUMB_PG 8 + + .text + + .set noreorder + + .extern hal_mmu_setup_return + +FUNC_START(hal_mmu_setup) + + mtc0 zero,tlbhi + nop + li a0,0 +2: + bal resettlb + nop + addiu a0,a0,1 + bne a0,NTLBENTRIES,2b + nop + + +#define tlblo_even s0 +#define tlblo_odd s1 +#define vaddr s2 +#define paddr0 s3 +#define paddr1 s4 +#define pmask s5 +#define tmp s6 +#define ix k1 + + + li ix,0 + li vaddr,IO_VIRTUAL_BASE + li paddr0,IO_PHYSICAL_BASE +loop: + + li a0,((PAGE_SIZE - 1) << 1) + li a1,TLBPGMASK_MASK + and pmask, a0,a1 + + li tlblo_even, TLBLO_V | TLBLO_D | TLBLO_G + li tlblo_odd, TLBLO_V | TLBLO_D | TLBLO_G + + li tmp,PAGE_SIZE + addu paddr1,paddr0,tmp + li tmp,TLBHI_VPN2MASK + and a1,vaddr,tmp + + li tmp,TLBLO_PFNSHIFT + srl a2,paddr0,tmp + li tmp,TLBLO_PFNMASK + and a2,a2,tmp + or a2,a2,TLBLO_UNCACHED + or a2,a2,tlblo_even + + li tmp,TLBLO_PFNSHIFT + srl a3,paddr1,tmp + li tmp,TLBLO_PFNMASK + and a3,a3,tmp + or a3,a3,TLBLO_UNCACHED + or a3,a3,tlblo_odd + + + move a0,pmask + or a0,a0,ix + + bal map_tlb4000 + nop + + addi ix,ix,1 + + li tmp,PADDR_INC + addu vaddr,vaddr,tmp + addu paddr0,paddr0,tmp + + li tmp,NUMB_PG + bne ix,tmp,loop + nop + + # Go back via a jump, not a return + lar k0,hal_mmu_setup_return + jr k0 + nop + +FUNC_END(hal_mmu_setup) + + +## Invalidate the TLB entry specified by index +## +## resettlb(index) +## a0 = index +## +## Uses : t0, t2, v0, a0 + +FUNC_START(resettlb) + + li t2,K0BASE & TLBHI_VPN2MASK + mfc0 t0,tlbhi # save current TLBHI + mfc0 v0,status # save SR and disable interrupts + mtc0 zero,status # clear interrupts + mtc0 t2,tlbhi # invalidate entry + mtc0 zero,tlblo0 + mtc0 zero,tlblo1 + mtc0 a0,index + nop; nop; nop; nop; nop; nop; nop; nop + tlbwi + nop; nop; nop; nop; nop; nop; nop; nop + mtc0 t0,tlbhi + mtc0 v0,status + j ra + nop + +FUNC_END(resettlb) + +## Setup R4000 TLB entry +## +## map_tlb4000(mask_index, tlbhi, pte_even, pte_odd) +## a0 = TLB entry index and page mask +## a1 = virtual page number and PID +## a2 = pte -- contents of even pte +## a3 = pte -- contents of odd pte +## +## +## +## Uses : t0, t1, t2, v0, a0, a1, a2, a3 + +FUNC_START(map_tlb4000) + and t2,a0,TLBPGMASK_MASK + and a0,TLBINX_INXMASK + mfc0 t1,tlbhi # save current TLBPID + mfc0 v0,status # save SR and disable interrupts + mtc0 zero,status # clear interrupts + mtc0 t2,pagemask # set + mtc0 a1,tlbhi # set VPN and TLBPID + mtc0 a2,tlblo0 # set PPN and access bits + mtc0 a3,tlblo1 # set PPN and access bits + mtc0 a0,index # set INDEX to wired entry + nop; nop; nop; nop; nop; nop; nop; nop + tlbwi # drop it in + nop; nop; nop; nop; nop; nop; nop; nop + mtc0 t1,tlbhi # restore TLBPID + mtc0 v0,status # restore SR + j ra + nop +FUNC_END(map_tlb4000) + +#endif + +##----------------------------------------------------------------------------- +## MEMC initialization. +## This also initializes the PCI bus and ISA bus bridge, so at the end of this +## we should have full access to all the memory and devices we need. +## This code is table driven, which is somewhat more compact that coding it all. +## Table entries consist of an address and a value to store in that address. +## A zero address terminates the table. Two special address values modify the +## behaviour: +## DELAY_LOOP loops for the number of iterations in the value field. +## WRITE16 treats the next 2 words as an address and value to be written +## with a 16 bit write cycle. + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + +#define DELAY_LOOP 1 +#define WRITE16 2 +#define WRITEREAD32 3 + + +FUNC_START(hal_memc_setup) + + lar t0,hal_memc_setup_table + la t1,0xbfc00000 + la t2,DELAY_LOOP + la t3,WRITE16 + la t4,WRITEREAD32 +1: + lw a0,0(t0) # next table entry + lw a1,4(t0) # value to write + addiu t0,8 # go to next entry + beq a0,t2,2f # Check for delay + nop + beq a0,t3,3f # Check for 16 bit write + nop + beq a0,t4,4f # Check for 32 bit write/read + nop + beqz a0,9f # zero terminates loop + nop + lw zero,0(t1) # uncached read to flush write buffer + sw a1,0(a0) # write it + lw zero,0(t1) # uncached read to flush write buffer + b 1b + nop +4: + lw a3,0(t0) # get next word + addiu t0,4 # skip it + lw zero,0(t1) # uncached read to flush write buffer + sw a3,0(a1) # write it + lw a3,0(a1) # and read it back + lw zero,0(t1) # uncached read to flush write buffer + b 1b + nop +2: + lw zero,0(t1) # uncached read to flush write buffer + bnez a1,2b # count down by value in a1 + addiu a1,-1 # decrement in delay slot + b 1b # go back to loop + nop +3: + lw a3,0(t0) # get next word + addiu t0,4 # skip it + sh a3,0(a1) # store halfword + lw zero,0(t1) # uncached read to flush write buffer + b 1b + nop +9: + jr ra + nop + +FUNC_END(hal_memc_setup) + +##----------------------------------------------------------------------------- +## Definitions for the VRC4373, also known as the Nile I, +## and maybe the Nile III as well. + +#define N1_BASE 0xAF000000 +#define N2_BASE 0xBC000000 + +#define BMCTRL (N1_BASE + 0x00) +#define S1CTRL (N1_BASE + 0x04) +#define S2CTRL (N1_BASE + 0x08) +#define S3CTRL (N1_BASE + 0x0C) +#define S4CTRL (N1_BASE + 0x10) +#define PCIMSTRADDR1 (N1_BASE + 0x14) +#define PCIMSTRADDR2 (N1_BASE + 0x18) +#define PCISLAVADDR1 (N1_BASE + 0x1C) +#define PCISLAVADDR2 (N1_BASE + 0x20) +#define PCIMSTRIO (N1_BASE + 0x24) +#define PCICNFGDATA (N1_BASE + 0x28) +#define PCICNFGADDR (N1_BASE + 0x2C) +#define PCIMBOX1 (N1_BASE + 0x30) +#define PCIMBOX2 (N1_BASE + 0x34) +#define DMACTRL1 (N1_BASE + 0x38) +#define DMALCLADDR1 (N1_BASE + 0x3C) +#define DMAPCIADDR1 (N1_BASE + 0x40) +#define DMACTRL2 (N1_BASE + 0x44) +#define DMALCLADDR2 (N1_BASE + 0x48) +#define DMAPCIADDR2 (N1_BASE + 0x4C) +#define BUSERRSTAT (N1_BASE + 0x50) +#define INTCNTRL (N1_BASE + 0x54) +#define REFRESHRATE (N1_BASE + 0x58) +#define BOOTROMWPRTCT (N1_BASE + 0x5C) +#define PCI_EXCL_ACC (N1_BASE + 0x60) +#define PCI_ENABLE_REG (N1_BASE + 0x74) +#define N3_POM_INIT (N1_BASE + 0x78) +/* +#define N1RESERVED1 (N1_BASE + 0x60) +*/ + + +#define N1PCIHEADER (N1_BASE + 0x100) +#define N1PCICMD (N1PCIHEADER + 0x04) +#define MBOXPCIADDR (N1PCIHEADER + 0x10) + +#define N1CLSIZE (N1PCIHEADER + 0x0c) /* Cache Line Size */ +#define N1MLTIM (N1PCIHEADER + 0x0d) +#define N1MBADD (N1PCIHEADER + 0x10) +#define N1RSVD2 (N1PCIHEADER + 0x40) /* Word boundary */ +#define N1RTYTIM (N1PCIHEADER + 0x41) + +##----------------------------------------------------------------------------- +## Definitions for the VRC4372, also known as the Nile II. + +#if defined(CYGPKG_HAL_MIPS_VR4300_VRC4373) +#define PCI_N2_DEV 0x00010000 /* PCI Device # - Nile 2 */ +#endif + +#define N2CLSIZE ( 0x0c) /* Cache Line Size */ +#define N2IOADD ( 0x14) +#define N2DSCTIM ( 0x40) + +#define IOCON (N2_BASE + 0x0000) + + /* GPIO Bus Controller Registers */ +#define GPDIR (IOCON + 0x0100) +#define GPOUT (IOCON + 0x0104) +#define GPIN (IOCON + 0x0108) + + /* Interrupt Controller Registers */ +#define INTPOL (IOCON + 0x200) +#define INTTRIG (IOCON + 0x204) +#define INTPINS (IOCON + 0x208) +#define INTMASK0 (IOCON + 0x20C) +#define INTSTAT0 (IOCON + 0x210) +#define INTMASK1 (IOCON + 0x214) +#define INTSTAT1 (IOCON + 0x218) +#define INTMASK2 (IOCON + 0x21C) +#define INTSTAT2 (IOCON + 0x220) + + /* IO Bus Controller Registers */ +#if defined(CYGPKG_HAL_MIPS_MSBFIRST) +// The 16 bit registers are swapped pairwise in each word. +#define IOPROF_00 (IOCON + 0x0402) +#define IOPROF_01 (IOCON + 0x0400) +#define IOPROF_02 (IOCON + 0x0406) +#define IOPROF_03 (IOCON + 0x0404) +#define IOPROF_04 (IOCON + 0x040A) +#define IOPROF_05 (IOCON + 0x0408) +#define IOPROF_06 (IOCON + 0x040E) +#define IOPROF_07 (IOCON + 0x040C) +#define IOPROF_08 (IOCON + 0x0412) +#define IOPROF_09 (IOCON + 0x0410) +#define IOPROF_0A (IOCON + 0x0416) +#define IOPROF_0B (IOCON + 0x0414) +#define IOPROF_0C (IOCON + 0x041a) +#define IOPROF_10 (IOCON + 0x0422) +#define IOPROF_11 (IOCON + 0x0420) +#define IOPROF_12 (IOCON + 0x0426) +#define IOPROF_13 (IOCON + 0x0424) +#elif defined(CYGPKG_HAL_MIPS_LSBFIRST) +#define IOPROF_00 (IOCON + 0x0400) +#define IOPROF_01 (IOCON + 0x0402) +#define IOPROF_02 (IOCON + 0x0404) +#define IOPROF_03 (IOCON + 0x0406) +#define IOPROF_04 (IOCON + 0x0408) +#define IOPROF_05 (IOCON + 0x040A) +#define IOPROF_06 (IOCON + 0x040C) +#define IOPROF_07 (IOCON + 0x040E) +#define IOPROF_08 (IOCON + 0x0410) +#define IOPROF_09 (IOCON + 0x0412) +#define IOPROF_0A (IOCON + 0x0414) +#define IOPROF_0B (IOCON + 0x0416) +#define IOPROF_0C (IOCON + 0x0418) +#define IOPROF_10 (IOCON + 0x0420) +#define IOPROF_11 (IOCON + 0x0422) +#define IOPROF_12 (IOCON + 0x0424) +#define IOPROF_13 (IOCON + 0x0426) +#else +#error MIPS endianness not define by configuration +#endif +#define IOTOUT (IOCON + 0x0430) +#define IOPOL (IOCON + 0x0434) + +##----------------------------------------------------------------------------- +## PCI definitions + +#define PCI_IOSPACE_BASE 0x0c /* PCI I/O Space Adr */ + +#define PCIADR_REGNO 0x000000fc /* Register # mask */ + +#define PCI_CONFIG( dev, func, reg ) ( dev | ( reg & PCIADR_REGNO) ) + +#define PCI_COMMAND_STATUS_REG 0x04 +#define PCI_MAP_REG_START 0x10 +#define PCI_INTERRUPT_REG 0x3c + +##----------------------------------------------------------------------------- +## The initialization table + +hal_memc_setup_table: + + .long DELAY_LOOP, 0x00010000 # Wait for HW to settle + + + # Set up SDRAM and SIMM1 + +#if defined(CYGPKG_HAL_MIPS_VR4300_VRC4373) + + .long BMCTRL, 0x0000803b # Base memory setup + .long S1CTRL, 0x0402013f # SIMM1 + +#else +#error Unsupported board +#endif + + # Set up power-on memory state + .long N3_POM_INIT, 0x00000002 # Power-on memory init + .long DELAY_LOOP, 0x00000100 # wait a bit + .long WRITEREAD32, N3_POM_INIT, 0x00000004 # Power-on memory init + .long DELAY_LOOP, 0x00000100 # wait a bit + .long WRITEREAD32, N3_POM_INIT, 0x00000001 # Power-on memory init + .long DELAY_LOOP, 0x00000100 # wait a bit + .long REFRESHRATE, 0x00000fff # DRAM refresh rate + + + .long BOOTROMWPRTCT, 0xffffff3e # Write protect boot ROM + + # Set up PCI master address window + .long PCIMSTRADDR1, 0x1c0fd01c + .long PCIMSTRADDR2, 0x80081080 + + # Set up PCI slave address window + .long PCISLAVADDR1, 0x00081000 + .long PCISLAVADDR2, 0x10081080 + + # Map PCI IO space Phys == Local + .long PCIMSTRIO, (0x000fd000 | ( PCI_IOSPACE_BASE << 24) | PCI_IOSPACE_BASE) + + # VRC437X Bridge config space + + .long N1PCICMD, 0x00000006 # Memory space enable, bus master + .long N1CLSIZE, 0x00003000 # Master latency time + .long N1MBADD, 0x20000000 # Mailbox base address + .long N1RSVD2, 0x0000f000 # Retry value + + .long PCI_EXCL_ACC, 0x00000020 # PCI exclusive access register + .long PCI_ENABLE_REG, 0x00000005 # PCI config done, enable arbitration + + # Set up 4372. This is configured entirely through its PCI + # configuration space. Hence the following all consist of + # writing an address to the PCICNFGADDR register followed + # by a write of the data to the PCICNFGDATA register. + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_COMMAND_STATUS_REG) + .long PCICNFGDATA, 0x00000146 + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2CLSIZE) + .long PCICNFGDATA, 0x00003000 + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_MAP_REG_START) + .long PCICNFGDATA, 0x1c000000 + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2IOADD) + .long PCICNFGDATA, 0x80000000 + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, PCI_INTERRUPT_REG) + .long PCICNFGDATA, 0x00000000 + + .long PCICNFGADDR, PCI_CONFIG( PCI_N2_DEV, 0, N2DSCTIM) + .long PCICNFGDATA, 0x0070f000 + + # Set up IO bus controller chip select profile registers to + # allow access to the devices. + + .long WRITE16, IOPROF_00, 0x04d1 # RTC - DS1386 + .long WRITE16, IOPROF_01, 0x007f # DUART - Z8530 + .long WRITE16, IOPROF_02, 0x007f # Timer - Z8536 + .long WRITE16, IOPROF_03, 0x00d9 # Parallel = 8255 + .long WRITE16, IOPROF_06, 0x007f # 7 segment display + .long WRITE16, IOPROF_07, 0x007f # 7 segment display + + # Configure the rest of the 4372 + + .long IOTOUT, 0x200003c0 # IO timout control + .long IOPOL, 0x00000000 # IO bus pin polarity + .long GPDIR, 0x000007c0 # GPIO pins 6-10 output + .long INTPOL, 0x00003fff # Interrupt polarity + .long INTTRIG, 0x00003fff # Interrupt trigger + .long INTMASK0, 0x00000000 + .long INTMASK1, 0x00000000 + .long INTMASK2, 0x00000000 + .long INTSTAT0, 0x00000000 # Zero all int status regs + .long INTSTAT1, 0x00000000 + .long INTSTAT2, 0x00000000 + + .long DELAY_LOOP, 0x00010000 # Wait for HW to settle + + .long 0, 0 + +#endif + +##----------------------------------------------------------------------------- +## end of platform.S +
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/plf_misc.c @@ -0,0 +1,181 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +#include <cyg/hal/plf_z8530.h> + +/*------------------------------------------------------------------------*/ + +void hal_platform_init(void) +{ +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) + // Set up eCos/ROM interfaces + hal_if_init(); +#endif + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + (defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) || \ + defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)) + + { + extern CYG_ADDRESS hal_virtual_vector_table[32]; + void patch_dbg_syscalls( void * ); + patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); + } +#endif +} + +/*------------------------------------------------------------------------*/ +/* Functions to support the detection and execution of a user provoked */ +/* program break. These are usually called from interrupt routines. */ + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) && \ + defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) + +cyg_bool cyg_hal_is_break(char *buf, int size) +{ + while( size ) + if( buf[--size] == 0x03 ) return true; + + return false; +} + +void cyg_hal_user_break( CYG_ADDRWORD *regs ) +{ +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) + // The following code should be at the very start of this function so + // that it can access the RA register before it is saved and reused. + register CYG_WORD32 ra; + asm volatile ( "move %0,$31;" : "=r" (ra) ); + + { + extern CYG_ADDRESS hal_virtual_vector_table[64]; + typedef void install_bpt_fn(void *epc); + CYG_WORD32 pc; + HAL_SavedRegisters *sreg = (HAL_SavedRegisters *)regs; + install_bpt_fn *ibp = (install_bpt_fn *)hal_virtual_vector_table[35]; + + if( regs == NULL ) pc = ra; + else pc = sreg->pc; + + if( ibp != NULL ) ibp((void *)pc); + } + +#elif defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + + { + extern void breakpoint(void); + breakpoint(); + } + +#else + + HAL_BREAKPOINT(breakinst); + +#endif + +} + +#endif + +/*------------------------------------------------------------------------*/ +/* Control C ISR support */ + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) && \ + defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) + +#if CYGHWR_HAL_MIPS_VR4300_VRC437X_GDB_PORT == 0 +#define DUART_CHAN DUART_A +#else +#define DUART_CHAN DUART_B +#endif + +struct Hal_SavedRegisters *hal_saved_interrupt_state; + +void hal_ctrlc_isr_init(void) +{ + HAL_DUART_WRITE_CR( DUART_CHAN, 1, 0x10 ); + HAL_DUART_WRITE_CR( DUART_CHAN, 9, 0x0a ); + HAL_INTERRUPT_SET_LEVEL( CYGHWR_HAL_GDB_PORT_VECTOR, 0 ); + HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR ); +} + +cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + + char c; + cyg_uint8 rr0; + + HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR ); + HAL_DUART_READ_CR(DUART_CHAN, 0, rr0 ); + + // The following return value prevents a spurious interrupt report. + // That is what should happen, but for some reason we get the odd extra + // character when running in the test farm. + + if ( (rr0 & 0x01) == 0 ) return 2; + + HAL_DUART_READ_RR( DUART_CHAN, c ); + + if( cyg_hal_is_break( &c , 1 ) ) + cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state ); + + return 2; +} + +#endif + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/plf_serial.c @@ -0,0 +1,434 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jskov (based on the old tx39 hal_stub.c) +// Contributors:nickg, jskov +// Date: 1999-02-12 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_io.h> // HAL IO macros +#include <cyg/hal/hal_diag.h> // diag output. FIXME + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/plf_z8530.h> + +/*---------------------------------------------------------------------------*/ + +static unsigned char _diag_init[] = { + 0x00, /* Register 0 */ + 0x00, /* Register 1 - no interrupts */ + 0x00, /* Register 2 */ + 0xC1, /* Register 3 - Rx enable, 8 data */ + 0x44, /* Register 4 - x16 clock, 1 stop, no parity */ + 0x68, /* Register 5 - Tx enable, 8 data */ + 0x00, /* Register 6 */ + 0x00, /* Register 7 */ + 0x00, /* Register 8 */ + 0x00, /* Register 9 */ + 0x00, /* Register 10 */ + 0x56, /* Register 11 - Rx, Tx clocks from baud rate generator */ + 0x00, /* Register 12 - baud rate LSB */ + 0x00, /* Register 13 - baud rate MSB */ + 0x03, /* Register 14 - enable baud rate generator */ + 0x00 /* Register 15 */ +}; + +#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2) +#define DUART_CLOCK 4915200 /* Z8530 duart */ +#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */ + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 base; + cyg_uint32 msec_timeout; + int isr_vector; +} channel_data_t; + +static const channel_data_t channels[2] = { + { DUART_A, 1000, CYGNUM_HAL_INTERRUPT_DUART}, + { DUART_B, 1000, CYGNUM_HAL_INTERRUPT_DUART} +}; + +//----------------------------------------------------------------------------- +// Set the baud rate + +static void +cyg_hal_plf_serial_set_baud(cyg_uint32 duart, cyg_uint16 baud_rate) +{ + unsigned short brg = BRTC(baud_rate); + HAL_DUART_WRITE_CR(duart, 12, brg&0xFF); + HAL_DUART_WRITE_CR(duart, 13, brg>>8); +} + +//----------------------------------------------------------------------------- +// The minimal init, get and put functions. All by polling. + +void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint32 duart; + unsigned short brg = BRTC(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); + int i; + channel_data_t *chan; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + +#ifdef CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + if( (chan-&channels[0]) == CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL ) + brg = BRTC(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); +#endif +#ifdef CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + if( (chan-&channels[0]) == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL ) + brg = BRTC(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); +#endif + + duart = chan->base; + + _diag_init[12] = brg & 0xFF; + _diag_init[13] = brg >> 8; + for (i = 1; i < 16; i++) { + HAL_DUART_WRITE_CR(duart, i, _diag_init[i]); + } + +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) +{ + cyg_uint32 duart; + cyg_uint8 rr0; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + duart = ((channel_data_t*)__ch_data)->base; + + CYGARC_HAL_SAVE_GP(); + + do + { + HAL_DUART_READ_CR(duart, 0, rr0 ); + } while( (rr0 & 0x04) == 0 ); + + HAL_DUART_WRITE_TR( duart, __ch ); + + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_DUART ); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint32 duart; + cyg_uint8 rr0; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + duart = ((channel_data_t*)__ch_data)->base; + + HAL_DUART_READ_CR(duart, 0, rr0 ); + + if( (rr0 & 0x01) == 0 ) + return false; + + HAL_DUART_READ_RR( duart, *ch ); + + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_DUART ); + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_DUART_WRITE_CR( chan->base, 1, 0x10 ); + HAL_DUART_WRITE_CR( chan->base, 9, 0x0a ); + + HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 0); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_DUART_WRITE_CR( chan->base, 1, 0x00 ); + HAL_DUART_WRITE_CR( chan->base, 9, 0x00 ); + + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + break; + case __COMMCTL_SETBAUD: + { + cyg_uint32 baud_rate; + cyg_uint32 duart = chan->base; + va_list ap; + + va_start(ap, __func); + baud_rate = va_arg(ap, cyg_uint32); + va_end(ap); + + // Set baud rate. + cyg_hal_plf_serial_set_baud(duart, baud_rate); + + } + break; + + case __COMMCTL_GETBAUD: + break; + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + channel_data_t* chan; + char c; + + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + *__ctrlc = 0; + + if ( cyg_hal_plf_serial_getc_nonblock(__ch_data, &c) ) + { + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + + return res; +} + +#endif + +static void +cyg_hal_plf_serial_init(void) +{ +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); +#endif + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[0].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel((void*)&channels[0]); + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +#endif +} + + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// End of plf_serial.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/plf_stub.c @@ -0,0 +1,87 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jskov (based on the old tx39 hal_stub.c) +// Contributors:nickg, jskov +// Date: 1999-02-12 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_io.h> // HAL IO macros +#include <cyg/hal/hal_diag.h> // diag output. FIXME + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- +// Stub init + +void hal_plf_stub_init(void) +{ +// extern CYG_ADDRESS hal_virtual_vector_table[64]; + extern void init_thread_syscall( void *); + extern void install_async_breakpoint(void *epc); + void (*oldvsr)(void); + extern void __default_exception_vsr(void); + + // Ensure that the breakpoint VSR points to the default VSR. This will pass + // it on to the stubs. + HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, __default_exception_vsr, &oldvsr ); + + // Install async breakpoint handler into vector table. + hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint; + +#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT) + // Only include this code if we do not have a kernel. Otherwise + // the kernel supplies the functionality for the app we are linked + // with. + + // Prepare for application installation of thread info function in + // vector table. + hal_virtual_vector_table[15] = 0; + init_thread_syscall( (void *)&hal_virtual_vector_table[15] ); +#endif +} + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +// End of plf_stub.c
new file mode 100644 --- /dev/null +++ b/packages/hal/mips/vrc437x/current/src/pmon.S @@ -0,0 +1,267 @@ +//======================================================================== +// +// pmon.S +// +// Low-level entry points into PMON monitor. +// +//======================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat, nickg +// Contributors: Red Hat, nickg +// Date: 1999-04-21 +// Purpose: +// Description: Low-level entry points into PMON monitor. +// Usage: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +#ifdef __mips16 +/* This file contains 32 bit assembly code. */ + .set nomips16 +#endif + +#if __mips < 3 + /* This machine does not support 64-bit operations. */ + #define ADDU addu + #define SUBU subu +#else + /* This machine supports 64-bit operations. */ + #define ADDU daddu + #define SUBU dsubu +#endif + + +/* Standard MIPS register names: */ +#define zero $0 +#define z0 $0 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel private register 0 */ +#define k1 $27 /* kernel private register 1 */ +#define gp $28 /* global data pointer */ +#define sp $29 /* stack-pointer */ +#define fp $30 /* frame-pointer */ +#define ra $31 /* return address */ +#define pc $pc /* pc, used on mips16 */ + +#define fp0 $f0 +#define fp1 $f1 + +/* Useful memory constants: */ +#define K0BASE 0x80000000 +#ifndef __mips64 +#define K1BASE 0xA0000000 +#else +#define K1BASE 0xFFFFFFFFA0000000LL +#endif + +#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) + +/* Standard Co-Processor 0 register numbers: */ +#define C0_COUNT $9 /* Count Register */ +#define C0_SR $12 /* Status Register */ +#define C0_CAUSE $13 /* last exception description */ +#define C0_EPC $14 /* Exception error address */ +#define C0_CONFIG $16 /* CPU configuration */ + +/* Standard Status Register bitmasks: */ +#define SR_CU1 0x20000000 /* Mark CP1 as usable */ +#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ +#define SR_BEV 0x00400000 /* Controls location of exception vectors */ +#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ + +#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ +#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ +#define SR_UX 0x00000020 /* User extended addressing enabled */ + +/* Standard (R4000) cache operations. Taken from "MIPS R4000 + Microprocessor User's Manual" 2nd edition: */ + +#define CACHE_I (0) /* primary instruction */ +#define CACHE_D (1) /* primary data */ +#define CACHE_SI (2) /* secondary instruction */ +#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ + +#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ +#define INDEX_LOAD_TAG (1) +#define INDEX_STORE_TAG (2) +#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ +#define HIT_INVALIDATE (4) +#define CACHE_FILL (5) /* CACHE_I only */ +#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ +#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ +#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ + +#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) + +/* Individual cache operations: */ +#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) +#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) +#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) +#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) + +#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) +#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) +#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) +#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) + +#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) +#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) +#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) +#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) + +#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) +#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) + +#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) +#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) +#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) +#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) + +#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) +#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) +#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) + +#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) +#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) +#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) + +#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) +#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) + + .text + .align 2 + +#ifdef LSI + #define PMON_VECTOR 0xffffffffbfc00200 +#else + #define PMON_VECTOR 0xffffffffbfc00500 +#endif + +#ifndef __mips_eabi +/* Provide named functions for entry into the monitor: */ +#define INDIRECT(name,index) \ + .globl name; \ + .ent name; \ + .set noreorder; \ +name: la $2,+(PMON_VECTOR+((index)*4)); \ + lw $2,0($2); \ + j $2; \ + nop; \ + .set reorder; \ + .end name + +#else +#define INDIRECT(name,index) \ + .globl name; \ + .ent name; \ + .set noreorder; \ +name: la $2,+(PMON_VECTOR+((index)*4)); \ + lw $2,0($2); \ + SUBU sp,sp,0x40; \ + sd ra,0x38(sp); \ + sd fp,0x30(sp); \ + jal $2; \ + move fp,sp; \ + ld ra,0x38(sp); \ + ld fp,0x30(sp); \ + j ra; \ + ADDU sp,sp,0x40; \ + .set reorder; \ + .end name +#endif + + +/* The following magic numbers are for the slots into the PMON monitor */ +/* The first are used as the lo-level library run-time: */ +INDIRECT(pmon_read,0) +INDIRECT(pmon_write,1) +INDIRECT(pmon_open,2) +INDIRECT(pmon_close,3) +/* The following are useful monitor routines: */ +INDIRECT(pmon_ioctl,4) +INDIRECT(pmon_printf,5) +INDIRECT(pmon_vsprintf,6) +INDIRECT(pmon_ttctl,7) +INDIRECT(pmon_cliexit,8) +INDIRECT(pmon_getenv,9) +INDIRECT(pmon_onintr,10) +INDIRECT(pmon_flush_cache,11) +INDIRECT(pmon_exception,12) + +/* The following routine is required by the "print()" function: */ + .globl pmon_outbyte + .ent pmon_outbyte + .set noreorder +pmon_outbyte: + subu sp,sp,0x20 /* allocate stack space for string */ + sd ra,0x18(sp) /* stack return address */ + sd fp,0x10(sp) /* stack frame-pointer */ + move fp,sp /* take a copy of the stack pointer */ + /* We leave so much space on the stack for the string (16 + characters), since the call to mon_printf seems to corrupt + the 8bytes at offset 8 into the string/stack. */ + sb a0,0x00(sp) /* character to print */ + sb z0,0x01(sp) /* NUL terminator */ + jal pmon_printf /* and output the string */ + move a0,sp /* take a copy of the string pointer {DELAY SLOT} */ + + move sp,fp /* recover stack pointer */ + ld ra,0x18(sp) /* recover return address */ + ld fp,0x10(sp) /* recover frame-pointer */ + j ra /* return to the caller */ + addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */ + .set reorder + .end pmon_outbyte + +/* EOF pmon.S */
--- a/packages/hal/powerpc/quicc/current/ChangeLog +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_powerpc_quicc.cdl (CYGNUM_HAL_QUICC_DIAG_BAUD): + 234000->230400 typo. + 2001-07-31 Jonathan Larmour <jlarmour@redhat.com> 2001-07-31 Christoph Csebits <christoph.csebits@frequentis.com>
--- a/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl +++ b/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl @@ -58,7 +58,7 @@ cdl_package CYGPKG_HAL_QUICC { display "Baud rate for the HAL diagnostic port" flavor data legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 - 4800 7200 9600 14400 19200 38400 57600 115200 234000 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 } default_value 38400 description "
--- a/packages/hal/sh/arch/current/ChangeLog +++ b/packages/hal/sh/arch/current/ChangeLog @@ -1,3 +1,11 @@ +2001-09-11 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_sh.cdl (CYGHWR_HAL_SH_BIGENDIAN): Set the default + from what the platform requests, using the new + CYGINT_HAL_SH_PLF_LITTLEENDIAN_DEFAULT CDL interface. + + * src/sh.ld: Support .rel.got input sections. + 2001-09-05 Jesper Skov <jskov@redhat.com> * src/sh_stub.c (__single_step): Changed type 2 handling.
--- a/packages/hal/sh/arch/current/cdl/hal_sh.cdl +++ b/packages/hal/sh/arch/current/cdl/hal_sh.cdl @@ -113,10 +113,19 @@ cdl_package CYGPKG_HAL_SH { cdl_option CYGHWR_HAL_SH_BIGENDIAN { display "Use big-endian mode" - default_value 1 + default_value { (CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT != 0) \ + ? 1 : 0 } description " Use the CPU in big-endian mode." } + + cdl_interface CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT { + display "Platform wants default BE" + no_define + description " + This interface is set by the platform, not by the user, + to indicate what the default endianness should be." + } } cdl_component CYGPKG_HAL_SH_CACHE {
--- a/packages/hal/sh/arch/current/src/sh.ld +++ b/packages/hal/sh/arch/current/src/sh.ld @@ -82,7 +82,7 @@ GROUP(libtarget.a libgcc.a) KEEP(*(SORT(.dtors*))) CYG_LABEL_DEFN(__DTOR_END__) = ABSOLUTE(.); \ . = ALIGN(8); \ KEEP(*( SORT (.ecos.table.*))) ; \ - *(.got*) *(.rela.got) \ + *(.got*) *(.rela.got) *(.rel.got) \ . = ALIGN(4); \ } > _region_ \ CYG_LABEL_DEFN(_rom_data_start) = LOADADDR(.data); \
--- a/packages/hal/sh/cq7708/current/ChangeLog +++ b/packages/hal/sh/cq7708/current/ChangeLog @@ -1,3 +1,7 @@ +2001-09-11 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_sh_sh7708_cq7708.cdl: Default to big-endian. + 2001-05-29 Jesper Skov <jskov@redhat.com> * include/plf_io.h: Added.
--- a/packages/hal/sh/cq7708/current/cdl/hal_sh_sh7708_cq7708.cdl +++ b/packages/hal/sh/cq7708/current/cdl/hal_sh_sh7708_cq7708.cdl @@ -56,6 +56,7 @@ cdl_package CYGPKG_HAL_SH_SH7708_CQ7708 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED + implements CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
--- a/packages/hal/sh/cq7750/current/ChangeLog +++ b/packages/hal/sh/cq7750/current/ChangeLog @@ -1,3 +1,7 @@ +2001-09-11 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_sh_sh7750_cq7750.cdl: Default to big endian. + 2001-08-08 Jesper Skov <jskov@redhat.com> * misc/redboot_ROM.ecm: Added.
--- a/packages/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl +++ b/packages/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl @@ -55,6 +55,7 @@ cdl_package CYGPKG_HAL_SH_SH7750_CQ7750 implements CYGINT_HAL_DEBUG_GDB_STUBS implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
--- a/packages/hal/sh/edk7708/current/ChangeLog +++ b/packages/hal/sh/edk7708/current/ChangeLog @@ -1,3 +1,7 @@ +2001-09-11 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_sh_edk7708.cdl: Default to big endian. + 2001-05-29 Jesper Skov <jskov@redhat.com> * include/plf_io.h: Added.
--- a/packages/hal/sh/edk7708/current/cdl/hal_sh_edk7708.cdl +++ b/packages/hal/sh/edk7708/current/cdl/hal_sh_edk7708.cdl @@ -56,6 +56,7 @@ cdl_package CYGPKG_HAL_SH_EDK7708 { implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED + implements CYGINT_HAL_SH_PLF_BIGENDIAN_DEFAULT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
--- a/packages/hal/sh/sh3/current/ChangeLog +++ b/packages/hal/sh/sh3/current/ChangeLog @@ -1,3 +1,8 @@ +2001-09-10 Jesper Skov <jskov@redhat.com> + + * src/sh3_sci.c (cyg_hal_plf_sci_isr, + cyg_hal_plf_sci_getc_nonblock): Recover from serial RX overruns. + 2001-09-05 Jesper Skov <jskov@redhat.com> * include/mod_regs_ubc.h: Type 2 BRCR definitions.
--- a/packages/hal/sh/sh3/current/src/sh3_sci.c +++ b/packages/hal/sh/sh3/current/src/sh3_sci.c @@ -87,6 +87,13 @@ cyg_hal_plf_sci_getc_nonblock(void* __ch cyg_uint8 sr; HAL_READ_UINT8(base+_REG_SCSSR, sr); + if (sr & CYGARC_REG_SCSSR_ORER) { + // Serial RX overrun. Clear error and let caller try again. + HAL_WRITE_UINT8(base+_REG_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER); + return false; + } + if ((sr & CYGARC_REG_SCSSR_RDRF) == 0) return false; @@ -239,7 +246,13 @@ cyg_hal_plf_sci_isr(void *__ch_data, int *__ctrlc = 0; HAL_READ_UINT8(base+_REG_SCSSR, sr); - if (sr & CYGARC_REG_SCSSR_RDRF) { + if (sr & CYGARC_REG_SCSSR_ORER) { + // Serial RX overrun. Clear error and hope protocol recovers. + HAL_WRITE_UINT8(base+_REG_SCSSR, + CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER); + res = CYG_ISR_HANDLED; + } else if (sr & CYGARC_REG_SCSSR_RDRF) { + // Received character HAL_READ_UINT8(base+_REG_SCRDR, c); // Clear buffer full flag.
--- a/packages/infra/current/ChangeLog +++ b/packages/infra/current/ChangeLog @@ -1,3 +1,7 @@ +2001-09-11 Jesper Skov <jskov@redhat.com> + + * src/diag.cxx (diag_check_string): Also accept \b. + 2001-08-25 Gary Thomas <gthomas@redhat.com> * src/diag.cxx (_vprintf): Fix confusion between signed and unsigned
--- a/packages/infra/current/src/diag.cxx +++ b/packages/infra/current/src/diag.cxx @@ -229,12 +229,11 @@ static cyg_bool diag_check_string( const if( s-str > 256 ) result = false; - /* We only really support CR and NL at present. If we want to - * use tabs or other special chars, this test will have to be - * expanded. - */ - - if( c == '\n' || c == '\r' ) + /* We only really support CR, NL, and backspace at present. If + * we want to use tabs or other special chars, this test will + * have to be expanded. */ + + if( c == '\n' || c == '\r' || c == '\b' ) continue; /* Check for printable chars. This assumes ASCII */
--- a/packages/isoinfra/current/ChangeLog +++ b/packages/isoinfra/current/ChangeLog @@ -1,3 +1,9 @@ +2001-09-10 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/isoinfra.cdl: Add CYGINT_ISO_PTHREAD_MUTEX and + CYGBLD_ISO_PTHREAD_MUTEX_HEADER. + * include/pthread.h: Include above header if set. + 2001-08-06 Jonathan Larmour <jlarmour@redhat.com> * cdl/isoinfra.cdl: Add a separate POSIX mutex types header option.
--- a/packages/isoinfra/current/cdl/isoinfra.cdl +++ b/packages/isoinfra/current/cdl/isoinfra.cdl @@ -966,6 +966,17 @@ cdl_package CYGPKG_ISOINFRA { flavor booldata default_value 0 } + + cdl_interface CYGINT_ISO_PTHREAD_MUTEX { + display "POSIX mutex/cond var implementations" + requires { 1 >= CYGINT_ISO_PTHREAD_MUTEX } + } + + cdl_option CYGBLD_ISO_PTHREAD_MUTEX_HEADER { + display "POSIX mutex/cond var implementation header" + flavor booldata + default_value 0 + } } # ====================================================================
--- a/packages/isoinfra/current/include/pthread.h +++ b/packages/isoinfra/current/include/pthread.h @@ -59,6 +59,11 @@ # endif #endif +#if CYGINT_ISO_PTHREAD_MUTEX +# ifdef CYGBLD_ISO_PTHREAD_MUTEX_HEADER +# include CYGBLD_ISO_PTHREAD_MUTEX_HEADER +# endif +#endif #endif /* CYGONCE_ISO_PTHREAD_H multiple inclusion protection */
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,13 @@ +2001-09-07 Jonathan Larmour <jlarmour@redhat.com> + + * include/thread.inl (measure_stack_usage): Deal with stack limits. + +2001-09-07 Nick Garnett <nickg@redhat.com> + + * src/common/thread.cxx (set_priority): Change argument to + instrumentation call to new_priority rather than current + priority. (Suggested by Andrew Lunn). + 2001-09-05 Jesper Skov <jskov@redhat.com> * include/mqueue.inl (Cyg_Mqueue): Initialize busy flag of last
--- a/packages/kernel/current/include/thread.inl +++ b/packages/kernel/current/include/thread.inl @@ -134,8 +134,13 @@ inline void Cyg_HardwareThread::check_st #ifdef CYGFUN_KERNEL_THREADS_STACK_MEASUREMENT inline cyg_uint32 Cyg_HardwareThread::measure_stack_usage(void) { +#ifdef CYGFUN_KERNEL_THREADS_STACK_LIMIT + CYG_WORD *base = (CYG_WORD *)stack_limit; + cyg_uint32 size = (stack_size - (stack_limit-stack_base))/sizeof(CYG_WORD); +#else CYG_WORD *base = (CYG_WORD *)stack_base; cyg_uint32 size = stack_size/sizeof(CYG_WORD); +#endif cyg_ucount32 i; // Work up the stack comparing with the preset value
--- a/packages/kernel/current/src/common/thread.cxx +++ b/packages/kernel/current/src/common/thread.cxx @@ -864,7 +864,7 @@ Cyg_Thread::set_priority( cyg_priority n // CYG_ASSERT( new_priority >= CYG_THREAD_MAX_PRIORITY, "Priority out of range"); // CYG_ASSERT( new_priority <= CYG_THREAD_MIN_PRIORITY, "Priority out of range"); - CYG_INSTRUMENT_THREAD(PRIORITY,this,priority); + CYG_INSTRUMENT_THREAD(PRIORITY,this,new_priority); // Prevent preemption Cyg_Scheduler::lock();
--- a/packages/redboot/current/ChangeLog +++ b/packages/redboot/current/ChangeLog @@ -1,3 +1,19 @@ +2001-09-11 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/redboot.cdl (CYGPKG_REDBOOT_FLASH): Be conditional on an + actual flash device, not just the generic flash layer. + +2001-09-11 Gary Thomas <gthomas@redhat.com> + + * src/version.c (_CERTIFICATE): Add information about product + certification (either Red Hat certified or not). + + * src/flash.c (fis_delete): Deny user deleting "reserved" images. + +2001-09-07 Andrew Lunn <andrew.lunn@ascom.ch> + * src/parse.c: A semi colon can be used to separate multiple + commands on one line. + 2001-09-06 Jonathan Larmour <jlarmour@redhat.com> * include/redboot.h: Include string function prototype header. @@ -7,6 +23,13 @@ 2001-09-06 Jesper Skov <jskov@redhat.c * src/fs/ide.c (ide_read_sectors): Use diag_(s)printf. * src/fs/disk.c (do_disks): Same. +2001-08-27 Andrew Lunn <andrew.lunn@ascom.ch> + * src/flash.c: Allow the flash blocks used for FIS directory and + config information to be user configured. Generalise the fis_init + function to deal with the blocks in any order. + * cdl/redboot.cdl: Added the configury needed to specify which + flash blocks to use. + 2001-08-27 Mark Salter <msalter@redhat.com> * src/syscall.c (HZ): Should be 60 for ARM, also.
--- a/packages/redboot/current/cdl/redboot.cdl +++ b/packages/redboot/current/cdl/redboot.cdl @@ -239,7 +239,7 @@ cdl_package CYGPKG_REDBOOT { display "Allow RedBoot to support FLASH programming" flavor bool default_value 1 - active_if CYGPKG_IO_FLASH + active_if CYGHWR_IO_FLASH_DEVICE description " If this option is enabled then RedBoot will provide commands to manage images in FLASH memory. These images can be loaded @@ -296,6 +296,17 @@ cdl_package CYGPKG_REDBOOT { active_if CYGOPT_REDBOOT_FIS calculated 1 + cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + display "Flash block containing the Directory" + flavor data + default_value (-1) + description " + Which block of flash should hold the directory + information. Positive numbers are absolute block numbers. + Negative block numbers count backwards from the last block. + eg 2 means block 2, -2 means the last but one block." + } + cdl_option CYGOPT_REDBOOT_FIS_RESERVED_BASE { display "Pseudo-file to describe reserved area" active_if { 0 != CYGNUM_REDBOOT_FLASH_RESERVED_BASE } @@ -375,6 +386,17 @@ cdl_package CYGPKG_REDBOOT { to be used for configuration options (persistent storage)." } + cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + display "Which block of flash to use" + flavor data + default_value (-2) + description " + Which block of flash should hold the configuration + information. Positive numbers are absolute block numbers. + Negative block numbers count backwards from the last block. + eg 2 means block 2, -2 means the last but one block." + } + cdl_option CYGSEM_REDBOOT_FLASH_ALIASES { display "Support simple macros/aliases in FLASH" flavor bool
--- a/packages/redboot/current/include/redboot.h +++ b/packages/redboot/current/include/redboot.h @@ -217,7 +217,7 @@ struct option_info { #define OPTION_ARG_TYPE_FLG 2 // Flag only // Command line parsing -externC struct cmd *parse(char *line, int *argc, char **argv); +externC struct cmd *parse(char **line, int *argc, char **argv); externC void init_opts(struct option_info *opts, char flag, bool takes_arg, int arg_type, void **arg, bool *arg_set, char *name);
--- a/packages/redboot/current/src/flash.c +++ b/packages/redboot/current/src/flash.c @@ -150,6 +150,8 @@ static int fisdir_size; // Size of FIS #ifdef CYGSEM_REDBOOT_FLASH_CONFIG static void *cfg_base; // Location in Flash of config data static int cfg_size; // Length of config data - rounded to Flash block size +// Prototypes for local functions +static unsigned char *flash_lookup_config(char *key); #endif static void @@ -167,7 +169,13 @@ fis_lookup(char *name) void *fis_addr; struct fis_image_desc *img; - fis_addr = (void *)((unsigned long)flash_end - block_size); + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + fis_addr = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + fis_addr = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } memcpy(fis_work_block, fis_addr, block_size); img = (struct fis_image_desc *)fis_work_block; for (i = 0; i < block_size/sizeof(*img); i++, img++) { @@ -251,6 +259,13 @@ fis_init(int argc, char *argv[]) // And a descriptor for the configuration data memset(img, 0, sizeof(*img)); strcpy(img->name, "RedBoot config"); + if (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK < 0) { + cfg_base = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } else { + cfg_base = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } img->flash_base = (unsigned long)cfg_base; img->mem_base = (unsigned long)cfg_base; img->size = cfg_size; @@ -259,7 +274,13 @@ fis_init(int argc, char *argv[]) // And a descriptor for the descriptor table itself memset(img, 0, sizeof(*img)); strcpy(img->name, "FIS directory"); - fis_base = (void *)((unsigned long)flash_end - block_size); + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + fis_base = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + fis_base = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } img->flash_base = (unsigned long)fis_base; img->mem_base = (unsigned long)fis_base; img->size = block_size; @@ -270,10 +291,9 @@ fis_init(int argc, char *argv[]) if (full_init) { unsigned long erase_start, erase_size; - // Erase everything except default RedBoot images, fis block, and config block. - // FIXME! This still assumes that fis and config blocks can use top of FLASH. - - // first deal with the possible first part, before RedBoot images: + // Erase everything except default RedBoot images, fis block, + // and config block. + // First deal with the possible first part, before RedBoot images: erase_start = (unsigned long)flash_start + CYGNUM_REDBOOT_FLASH_RESERVED_BASE; erase_size = (unsigned long)flash_start + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET; if ( erase_size > erase_start ) { @@ -286,11 +306,42 @@ fis_init(int argc, char *argv[]) } // second deal with the larger part in the main: erase_start = redboot_flash_start; // high water of created images + // Now the empty bits between the end of Redboot and the cfg and dir + // blocks. #ifdef CYGSEM_REDBOOT_FLASH_CONFIG - erase_size = (unsigned long)cfg_base - erase_start; // the gap between HWM and config data -#else + if (fis_base > cfg_base) { + erase_size = (unsigned long)cfg_base - erase_start; // the gap between HWM and config data + } else { + erase_size = (unsigned long)fis_base - erase_start; // the gap between HWM and fis data + } + if ((stat = flash_erase((void *)erase_start, erase_size, + (void **)&err_addr)) != 0) { + diag_printf(" initialization failed %p: %s\n", + err_addr, flash_errmsg(stat)); + } + erase_start += (erase_size + block_size); + if (fis_base > cfg_base) { + erase_size = (unsigned long)fis_base - erase_start; // the gap between config and fis data + } else { + erase_size = (unsigned long)cfg_base - erase_start; // the gap between fis and config data + } + if ((stat = flash_erase((void *)erase_start, erase_size, + (void **)&err_addr)) != 0) { + diag_printf(" initialization failed %p: %s\n", + err_addr, flash_errmsg(stat)); + } + erase_start += (erase_size + block_size); +#else // !CYGSEM_REDBOOT_FLASH_CONFIG erase_size = (unsigned long)fis_base - erase_start; // the gap between HWM and fis data + if ((stat = flash_erase((void *)erase_start, erase_size, + (void **)&err_addr)) != 0) { + diag_printf(" initialization failed %p: %s\n", + err_addr, flash_errmsg(stat)); + } + erase_start += (erase_size + block_size); #endif + // Lastly, anything at the end + erase_size = (unsigned long)flash_end - erase_start; if ((stat = flash_erase((void *)erase_start, erase_size, (void **)&err_addr)) != 0) { diag_printf(" initialization failed at %p: %s\n", @@ -342,9 +393,14 @@ fis_list(int argc, char *argv[]) { return; } - - img = (struct fis_image_desc *)((unsigned long)flash_end - block_size); - // Let diag_printf do the formatting in both cases, rather than cnouting + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + img = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + img = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } + // Let diag_printf do the formatting in both cases, rather than counting // cols by hand.... diag_printf("%-16s %-10s %-10s %-10s %-s\n", "Name","FLASH addr", @@ -487,7 +543,13 @@ fis_create(int argc, char *argv[]) defaults_assumed = false; if (name) { // Search existing files to acquire defaults for params not specified: - fis_addr = (void *)((unsigned long)flash_end - block_size); + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + fis_addr = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + fis_addr = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } memcpy(fis_work_block, fis_addr, block_size); img = (struct fis_image_desc *)fis_work_block; for (i = 0; i < block_size/sizeof(*img); i++, img++) { @@ -560,7 +622,13 @@ fis_create(int argc, char *argv[]) // Find a slot in the directory for this entry // First, see if an image by this name is already present slot_found = false; - fis_addr = (void *)((unsigned long)flash_end - block_size); + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + fis_addr = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + fis_addr = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } memcpy(fis_work_block, fis_addr, block_size); img = (struct fis_image_desc *)fis_work_block; for (i = 0; i < block_size/sizeof(*img); i++, img++) { @@ -656,7 +724,7 @@ static void fis_delete(int argc, char *argv[]) { char *name; - int i, stat; + int num_reserved, i, stat; void *fis_addr, *err_addr; struct fis_image_desc *img; bool slot_found; @@ -666,34 +734,42 @@ fis_delete(int argc, char *argv[]) fis_usage("invalid arguments"); return; } - slot_found = false; - fis_addr = (void *)((unsigned long)flash_end - block_size); + if (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK < 0) { + fis_addr = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } else { + fis_addr = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK*block_size)); + } memcpy(fis_work_block, fis_addr, block_size); img = (struct fis_image_desc *)fis_work_block; - i = 0; + num_reserved = 0; #ifdef CYGOPT_REDBOOT_FIS_RESERVED_BASE - i++; + num_reserved++; #endif #ifdef CYGOPT_REDBOOT_FIS_REDBOOT - i++; + num_reserved++; #endif #ifdef CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP - i++; + num_reserved++; #endif #ifdef CYGOPT_REDBOOT_FIS_REDBOOT_POST - i++; + num_reserved++; #endif #ifdef CYGSEM_REDBOOT_FLASH_CONFIG - i++; + num_reserved++; #endif #if 1 // And the descriptor for the descriptor table itself - i++; + num_reserved++; #endif - img += i; // Skip reserved files - for ( /* i, img */; i < block_size/sizeof(*img); i++, img++) { + for (i = 0; i < block_size/sizeof(*img); i++, img++) { if ((img->name[0] != (unsigned char)0xFF) && (strcmp(name, img->name) == 0)) { + if (i < num_reserved) { + diag_printf("Sorry, '%s' is a reserved image and cannot be deleted\n", img->name); + return; + } if (!verify_action("Delete image '%s'", name)) { return; } else { @@ -1636,6 +1712,13 @@ flash_write_config(void) config.key1 = CONFIG_KEY1; config.key2 = CONFIG_KEY2; config.cksum = crc32((unsigned char *)&config, sizeof(config)-sizeof(config.cksum)); + if (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK < 0) { + cfg_base = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } else { + cfg_base = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } if (verify_action("Update RedBoot non-volatile configuration")) { #ifdef CYGSEM_REDBOOT_FLASH_LOCK_SPECIAL // Insure [quietly] that the config page is unlocked before trying to update @@ -1854,7 +1937,13 @@ load_flash_config(void) #define _roundup(n,s) ((((n)+(s-1))/s)*s) cfg_size = (block_size > sizeof(config)) ? sizeof(config) : _roundup(sizeof(config), block_size); - cfg_base = (void *)((unsigned long)flash_end - _roundup(cfg_size+fisdir_size, block_size)); + if (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK < 0) { + cfg_base = (void *)((unsigned long)flash_end + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } else { + cfg_base = (void *)((unsigned long)flash_start + + (CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK*block_size)); + } memcpy(&config, cfg_base, sizeof(config)); if ((crc32((unsigned char *)&config, sizeof(config)-sizeof(config.cksum)) != config.cksum) || (config.key1 != CONFIG_KEY1)|| (config.key2 != CONFIG_KEY2)) {
--- a/packages/redboot/current/src/main.c +++ b/packages/redboot/current/src/main.c @@ -184,6 +184,7 @@ cyg_start(void) int res = 0; bool prompt = true; static char line[CYGPKG_REDBOOT_MAX_CMD_LINE]; + char *command; struct cmd *cmd; int cur; struct init_tab_entry *init_entry; @@ -315,8 +316,9 @@ cyg_start(void) #ifdef CYGSEM_REDBOOT_FLASH_ALIASES expand_aliases(line, sizeof(line)); #endif - if (strlen(line) > 0) { - if ((cmd = parse(line, &argc, &argv[0])) != (struct cmd *)0) { + command = (char *)&line; + while (strlen(command) > 0) { + if ((cmd = parse(&command, &argc, &argv[0])) != (struct cmd *)0) { (cmd->fun)(argc, argv); } else { diag_printf("** Error: Illegal command: \"%s\"\n", argv[0]);
--- a/packages/redboot/current/src/parse.c +++ b/packages/redboot/current/src/parse.c @@ -56,16 +56,21 @@ extern struct cmd __RedBoot_CMD_TAB__[], // // Scan through an input line and break it into "arguments". These // are space delimited strings. Return a structure which points to -// the strings, similar to a Unix program. +// the strings, similar to a Unix program. Multiple commands in the line +// are separated by ; similar to sh. If we find a semi we stop processing the +// line, terminate the current command with a null and return the start +// of the next command in *line. parse() can then be called again to +// process the next command on the line. // Note: original input is destroyed by replacing the delimiters with // null ('\0') characters for ease of use. // struct cmd * -parse(char *line, int *argc, char **argv) +parse(char **line, int *argc, char **argv) { - char *cp = line; + char *cp = *line; char *pp; int indx = 0; + int semi = 0; while (*cp) { // Skip leading spaces @@ -73,6 +78,11 @@ parse(char *line, int *argc, char **argv if (!*cp) { break; // Line ended with a string of spaces } + if (*cp == ';') { + *cp = '\0'; + semi=1; + break; + } if (indx < MAX_ARGV) { argv[indx++] = cp; } else { @@ -82,7 +92,9 @@ parse(char *line, int *argc, char **argv if (*cp == ' ') { *cp++ = '\0'; break; - } else if (*cp == '"') { + } else if (*cp == ';') { + break; + } else if (*cp == '"') { // Swallow quote, scan till following one if (argv[indx-1] == cp) { argv[indx-1] = ++cp; @@ -108,6 +120,11 @@ parse(char *line, int *argc, char **argv } } } + if (semi) { + *line = cp + 1; + } else { + *line = cp; + } *argc = indx; return cmd_search(__RedBoot_CMD_TAB__, &__RedBoot_CMD_TAB_END__, argv[0]); }
--- a/packages/redboot/current/src/version.c +++ b/packages/redboot/current/src/version.c @@ -66,17 +66,20 @@ #if defined(CYGDAT_REDBOOT_CUSTOM_VERSION) #define _REDBOOT_VERSION CYGDAT_REDBOOT_CUSTOM_VERSION +#define _CERTIFICATE Non-certified #elif defined(CYGPKG_REDBOOT_current) #define _REDBOOT_VERSION UNKNOWN +#define _CERTIFICATE Non-certified #else #define _REDBOOT_VERSION CYGPKG_REDBOOT +#define _CERTIFICATE Red Hat certified #endif #define __s(x) #x #define _s(x) __s(x) char RedBoot_version[] CYGBLD_ATTRIB_WEAK = "\nRedBoot(tm) bootstrap and debug environment [" _s(CYG_HAL_STARTUP) "]" - "\n version " _s(_REDBOOT_VERSION) + "\n" _s(_CERTIFICATE) " release, version " _s(_REDBOOT_VERSION) " - built " __TIME__ ", " __DATE__ "\n\n"; // Override default GDB stubs 'info'
--- a/packages/services/memalloc/common/current/ChangeLog +++ b/packages/services/memalloc/common/current/ChangeLog @@ -1,3 +1,7 @@ +2001-09-07 Jesper Skov <jskov@redhat.com> + + * tests/heaptest.c: Added some extra output on failures. + 2001-08-01 Jonathan Larmour <jlarmour@redhat.com> * include/sepmetaimpl.inl: Define check_free_memdq and
--- a/packages/services/memalloc/common/current/tests/heaptest.c +++ b/packages/services/memalloc/common/current/tests/heaptest.c @@ -117,7 +117,8 @@ test_pat(unsigned char *buf, int size, if (addrpat) bpat = ((int)bufptr)&0xFF; if ( *bufptr != bpat ) { - diag_printf( "Failed to compare at 0x%08x\n", bufptr ); + diag_printf( "Failed to compare at 0x%08x (saw 0x%08x expected 0x%08x)\n", + bufptr, *bufptr, bpat ); if ( errors++ == ERRORTHRESHOLD ) CYG_TEST_FAIL_FINISH( testname ); } @@ -130,7 +131,8 @@ test_pat(unsigned char *buf, int size, if (addrpat) pat = (unsigned int)ibufptr; if ( *ibufptr != pat ) { - diag_printf( "Failed to compare at 0x%08x\n", bufptr ); + diag_printf( "Failed to compare at 0x%08x (saw 0x%08x expected 0x%08x)\n", + bufptr, *ibufptr, pat ); if ( errors++ == ERRORTHRESHOLD ) CYG_TEST_FAIL_FINISH( testname ); } @@ -142,7 +144,8 @@ test_pat(unsigned char *buf, int size, if (addrpat) bpat = ((int)bufptr)&0xFF; if ( *bufptr != bpat ) { - diag_printf( "Failed to compare at 0x%08x\n", bufptr ); + diag_printf( "Failed to compare at 0x%08x (saw 0x%08x expected 0x%08x)\n", + bufptr, *bufptr, bpat ); if ( errors++ == ERRORTHRESHOLD ) CYG_TEST_FAIL_FINISH( testname ); } @@ -193,8 +196,8 @@ cyg_start(void) CYG_TEST_FAIL_FINISH("heaptest"); } - diag_printf( "INFO:<Testing memory at 0x%08x of size %d>\n", - buf, info.maxfree ); + diag_printf( "INFO:<Testing memory at 0x%08x of size %d for %d iterations>\n", + buf, info.maxfree, ITERS ); for (i=0; i<ITERS; i++) { errors += test_pat( buf, info.maxfree, 0, 0, "all zeroes" ); errors += test_pat( buf, info.maxfree, allonesint, 0,