--- a/packages/hal/arm/xscale/pxa2x0/current/ChangeLog
+++ b/packages/hal/arm/xscale/pxa2x0/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-08  Gary Thomas  <gary@mind.be>
+
+	* src/pxa2x0_misc.c: 
+	* include/hal_pxa2x0.h: Support GPIO alternate functions.
+
 2003-07-18  Nick Garnett  <nickg@balti.calivar.com>
 
 	* cdl/hal_arm_xscale_pxa2x0.cdl:

--- a/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h
+++ b/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h
@@ -9,6 +9,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -434,6 +435,14 @@
 #define PXA2X0_GAFR2_L				PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 )
 #define PXA2X0_GAFR2_U				PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 )
 
+#define PXA2X0_GPIO_NORM 0x00
+#define PXA2X0_GPIO_AF1  0x01
+#define PXA2X0_GPIO_AF2  0x02
+#define PXA2X0_GPIO_AF3  0x03
+#define PXA2X0_GPIO_IN      0
+#define PXA2X0_GPIO_OUT     1
+
+
 // Power Manager and Reset Control
 #define PXA2X0_PM_BASE				( PXA2X0_PERIPHERALS_BASE + 0x0f00000 )
 #define PXA2X0_PMCR					PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0000 )

--- a/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c
+++ b/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c
@@ -9,6 +9,7 @@
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -101,6 +102,26 @@ void hal_hardware_init(void)
 #endif
 }
 
+//
+// GPIO support functions
+//
+void
+_pxa2x0_set_GPIO_mode(int bit, int mode, int dir)
+{
+    int bank = bit / 32;
+    unsigned long *gpdr, *gafr;
+
+    gpdr = &PXA2X0_GPDR0[bank];
+    gafr = &PXA2X0_GAFR0_L[(bit&0x30)>>4];
+    bit %= 32;
+    // Data direction registers have 1 bit per GPIO
+    *gpdr = (*gpdr & ~(1<<bit)) | (dir<<bit);
+    // Alternate function regusters have 2 bits per GPIO
+    bit = (bit & 0x0F) * 2;
+    *gafr = (*gafr & ~(3<<bit)) | (mode<<bit);
+}
+
+
 // Initialize the clock
 static cyg_uint32  clock_period;
 

--- a/packages/hal/arm/xscale/uE250/current/ChangeLog
+++ b/packages/hal/arm/xscale/uE250/current/ChangeLog
@@ -1,3 +1,11 @@
+2003-08-08  Gary Thomas  <gary@mind.be>
+
+	* src/uE250_pci.c: 
+	* src/uE250_misc.c: Improve PCI initialization, including support
+	for external bus masters.
+
+	* include/plf_io.h: Define CYGARC_PCI_DMA_ADDRESS()
+
 2003-05-28  Gary Thomas  <gary@mind.be>
 
 	* src/xilinx-load.c: Improve feedback during FPGA downloads.

--- a/packages/hal/arm/xscale/uE250/current/include/plf_io.h
+++ b/packages/hal/arm/xscale/uE250/current/include/plf_io.h
@@ -235,6 +235,7 @@ static inline unsigned cygarc_virtual_ad
 }
 
 #define CYGARC_VIRTUAL_ADDRESS(_x_) cygarc_virtual_address(_x_)
+#define CYGARC_PCI_DMA_ADDRESS(_x_) (_x_)
 
 //-----------------------------------------------------------------------------
 // end of plf_io.h

--- a/packages/hal/arm/xscale/uE250/current/src/uE250_misc.c
+++ b/packages/hal/arm/xscale/uE250/current/src/uE250_misc.c
@@ -133,12 +133,6 @@ plf_hardware_init(void)
     hal_if_init();
 
     cyg_hal_plf_pci_init();
-    // Set up to handle PCI interrupts
-    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_GPIO1, 0, 0);  // Falling edge
-    HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GPIO1);
-    PCICTL_INT_RESET = 0xFF;  // Clear all pending interrupts
-    PCICTL_INT_EDGE = 0xFF;   // Generate interrupts
-    PCICTL_IRQ_MASK = 0x00;   // All masked
 
     initialize_plx_bridge();
 }

--- a/packages/hal/arm/xscale/uE250/current/src/uE250_pci.c
+++ b/packages/hal/arm/xscale/uE250/current/src/uE250_pci.c
@@ -114,11 +114,15 @@ cyg_hal_plf_pci_init(void)
     *PXA2X0_GPCR1 |= (0x01 << (45-32));
   
     // Set busmastering
+    _pxa2x0_set_GPIO_mode(13, PXA2X0_GPIO_AF2, PXA2X0_GPIO_OUT);
+    _pxa2x0_set_GPIO_mode(14, PXA2X0_GPIO_AF1, PXA2X0_GPIO_IN);
+
 //    diag_printf("Activating PCI bridge.\n");
-    PCICTL_MISC |= (1 | PCI_SDRAM_128) | PCI_TIMER;
+    PCICTL_MISC |= (1 | PCI_SDRAM_256) | PCI_TIMER;
 
     // Set command master
-    cyg_hal_plf_pci_cfg_write_byte(0,0, CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MASTER);
+    cyg_hal_plf_pci_cfg_write_word(0, 0, CYG_PCI_CFG_COMMAND, 
+                                   CYG_PCI_CFG_COMMAND_MEMORY|CYG_PCI_CFG_COMMAND_MASTER);
 
 //    diag_printf("Scanning PCI bridge...\n");
 
@@ -129,6 +133,13 @@ cyg_hal_plf_pci_init(void)
     next_bus = 1;
     cyg_pci_configure_bus(0, &next_bus);
 
+    // Set up to handle PCI interrupts
+    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_GPIO1, 0, 0);  // Falling edge
+    HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GPIO1);
+    PCICTL_INT_RESET = 0xFF;  // Clear all pending interrupts
+    PCICTL_INT_EDGE = 0xFF;   // Generate interrupts
+    PCICTL_IRQ_MASK = 0x00;   // All masked
+
     if (0){
         cyg_uint8 devfn;
         cyg_pci_device_id devid;
@@ -146,6 +157,7 @@ cyg_hal_plf_pci_init(void)
             diag_printf("PCI Func  : %d\n", CYG_PCI_DEV_GET_FN(devfn));
             diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
             diag_printf("Device Id : 0x%08X\n", dev_info.device);
+            diag_printf("Command:    0x%04X\n", dev_info.command);
             for (i = 0; i < dev_info.num_bars; i++) {
                 diag_printf("  BAR[%d]    0x%08x /", i, dev_info.base_address[i]);
                 diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",