Mercurial > flash_v2
changeset 579:aa8519b22eb0
Add TI ARM9 OMAP Innovator board port.
Contributed by Patrick Doyle.
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,8 @@ +2003-02-05 Patrick Doyle <wpd@delcomsys.com> + + * ecos.db: Add Texas Instruments ARM9 OMAP Innovator port. Redboot + only for now. + 2003-01-29 John Dallaway <jld@ecoscentric.com> * ecosadmin.tcl: Accommodate UNIX-style paths under Cygwin when
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,5 @@ +* Port added for Texas Instruments ARM9 OMAP Innovator board. Contributed by + Patrick Doyle of Delphi Communication Systems. * Add XScale PXA2x0 support, with Microplex Printer control 5.0 (mpc50) target incorporating flash support. * Add support for Cogent CSB281 - PowerPC 8245 board.
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/innovator/current/cdl/innovator_eth_drivers.cdl @@ -0,0 +1,118 @@ +# ==================================================================== +# +# innovator_eth_drivers.cdl +# +# Ethernet drivers - support for LAN91CXX ethernet controller +# on the BSE Innovator/SA1110 board. +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Jordi Colomer <jco@ict.es>, Patrick Doyle <wpd@delcomsys.com> +# Contributors: Patrick Doyle <wpd@delcomsys.com> +# Date: 2001-06-18 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ARM_INNOVATOR { + + display "Innovator SMC91C96 ethernet driver" + + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_ARM_ARM9_INNOVATOR + + # chip wired in PCMCIA, 16-bit mode, no EEPROM + # -- the chip is probably not wired in PCMCIA mode & I saw an EEPROM for it + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGINT_DEVS_ETH_SMSC_LAN91CXX_REQUIRED +# implements CYGINT_DEVS_ETH_SMSC_LAN91CXX_STATIC_ESA + + requires CYGPKG_DEVS_ETH_SMSC_LAN91CXX + description "Ethernet driver for Innovator boards." + + include_dir cyg/io + compile if_innovator.c + + define_proc { + puts $::cdl_system_header "/***** ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN91CXX_INL <cyg/io/devs_eth_innovator.inl>" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN91CXX_CFG <pkgconf/devs_eth_arm_innovator.h>" + puts $::cdl_system_header "/***** ethernet driver proc output end *****/" + } + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + + cdl_interface CYGINT_DEVS_ETH_SMSC_LAN91CXX_REQUIRED { + display "SMSC LAN91CXX driver required" + } + + cdl_option CYGDAT_DEVS_ETH_ARM_INNOVATOR_NAME { + display "Device name for the ethernet driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the ethernet device for the + ethernet port." + } + + cdl_option CYGDAT_DEVS_ETH_ARM_INNOVATOR_ESA { + display "The ethernet station address (MAC)" + flavor data + default_value {"{0x12, 0x13, 0x14, 0x15, 0x16, 0x17}"} + description "A static ethernet station address. + Caution: Booting two systems with the same MAC on the same + network, will cause severe conflicts." + active_if !CYGSEM_DEVS_ETH_ARM_INNOVATOR_REDBOOT_ESA + } + + cdl_option CYGSEM_DEVS_ETH_ARM_INNOVATOR_REDBOOT_ESA { + display "Use the RedBoot ESA (MAC address)" + default_value 0 + flavor bool + description " + Use the ESA that is stored as a RedBoot variable instead of + a static ESA." + } + +} + +# EOF innovator_eth_drivers.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/innovator/current/include/devs_eth_innovator.inl @@ -0,0 +1,125 @@ +//========================================================================== +// +// devs/eth/arm/innovator/..../include/devs_eth_innovator.inl +// +// Innovator ethernet I/O definitions. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Jordi Colomer <jco@ict.es>, Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2001-06-18 +// Purpose: Innovator ethernet definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/devs_eth_arm_innovator.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/innovator.h> + +// #define CYGNUM_DEVS_ETH_SMSC_LAN91CXX_SHIFT_ADDR 2 + +// MAC address is stored as a Redboot config option +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#include <redboot.h> +#include <flash_config.h> + +RedBoot_config_option("Network hardware address [MAC]", + innovator_esa, + ALWAYS_ENABLED, true, + CONFIG_ESA, 0 + ); +#endif +#endif + +// ESA address fetch function +static void innovator_get_ESA(struct lan91cxx_priv_data *cpd) +{ + // Fetch hardware address from RedBoot config +#if defined(CYGSEM_DEVS_ETH_ARM_INNOVATOR_REDBOOT_ESA) +#if defined(CYGPKG_REDBOOT) && \ + defined(CYGSEM_REDBOOT_FLASH_CONFIG) + flash_get_config("innovator_esa", cpd->enaddr, CONFIG_ESA); +#else +#error "No RedBoot flash configuration to store ESA" +#endif +#else + unsigned char static_esa[] = CYGDAT_DEVS_ETH_ARM_INNOVATOR_ESA; + memcpy(cpd->enaddr, static_esa, 6); +#endif +} + +static lan91cxx_priv_data lan91cxx_eth0_priv_data = { + + config_enaddr : innovator_get_ESA, +#ifndef CYGSEM_DEVS_ETH_ARM_INNOVATOR_REDBOOT_ESA + enaddr: CYGDAT_DEVS_ETH_ARM_INNOVATOR_ESA, +#endif +#if 0 + base : (unsigned short *) SA1110_FHH_ETH_IOBASE, + attbase : (unsigned char *) SA1110_FHH_ETH_MMBASE, + interrupt : SA1110_IRQ_GPIO_ETH +#else + base : (unsigned short *) 0x08000300, +#endif +}; + +ETH_DRV_SC(lan91cxx_sc, + &lan91cxx_eth0_priv_data, // Driver specific data + CYGDAT_DEVS_ETH_ARM_INNOVATOR_NAME, // Name for device + lan91cxx_start, + lan91cxx_stop, + lan91cxx_control, + lan91cxx_can_send, + lan91cxx_send, + lan91cxx_recv, + lan91cxx_deliver, + lan91cxx_poll, + lan91cxx_int_vector +); + +NETDEVTAB_ENTRY(lan91cxx_netdev, + "lan91cxx_" CYGDAT_DEVS_ETH_ARM_INNOVATOR_NAME, + smsc_lan91cxx_init, + &lan91cxx_sc); + +//EOF devs_eth_innovator.inl + +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/innovator/current/src/if_innovator.c @@ -0,0 +1,73 @@ +//========================================================================== +// +// devs/eth/arm/innovator/if_innovator.c +// +// Ethernet device driver for Innovator using SMSC LAN91C96 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//####BSDCOPYRIGHTBEGIN#### +// +// ------------------------------------------- +// +// Portions of this software may have been derived from OpenBSD or other sources, +// and are covered by the appropriate copyright disclaimers included herein. +// +// ------------------------------------------- +// +//####BSDCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Jordi Colomer <jco@ict.es>, Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2001-07-01 +// Purpose: +// Description: hardware driver for Innovator/SMSC LAN91CXX ethernet +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/devs_eth_arm_innovator.h> +#include <pkgconf/io_eth_drivers.h> + +#if defined(CYGPKG_REDBOOT) +#include <pkgconf/redboot.h> +#endif + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h>
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/innovator/current/cdl/flash_innovator.cdl @@ -0,0 +1,71 @@ +# ==================================================================== +# +# flash_innovator.cdl +# +# FLASH memory - Hardware support on OMAP1510DC EVM +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Patrick Doyle <wpd@delcomsys.com> +# Contributors: Patrick Doyle <wpd@delcomsys.com> +# Date: 2002-11-26 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_ARM_INNOVATOR { + display "TI OMAP1510DC EVM FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_ARM9_INNOVATOR + + implements CYGHWR_IO_FLASH_DEVICE + + compile arm_innovator_flash.c + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED { + display "Generic Intel FlashFile driver required" + } + + implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED + + requires CYGHWR_DEVS_FLASH_AMD_AM29DL323D +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/innovator/current/src/arm_innovator_flash.c @@ -0,0 +1,72 @@ +//========================================================================== +// +// arm_innovator_flash.c +// +// Flash programming for AMD Flash devices on TI OMAP1510DC EVM board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-11-26 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/innovator.h> + +//-------------------------------------------------------------------------- +// Device properties + +// We use the one AMD Am29DL323D part on the Innovator. +#define CYGNUM_FLASH_INTERLEAVE (1) +#define CYGNUM_FLASH_SERIES (1) +#define CYGNUM_FLASH_WIDTH (16) +#define CYGNUM_FLASH_BASE (INNOVATOR_FLASH_VIRT_BASE) + +//-------------------------------------------------------------------------- +// Platform specific extras + +//-------------------------------------------------------------------------- +// Now include the driver code. +#include "cyg/io/flash_am29xxxxx.inl" + +// ------------------------------------------------------------------------ +// EOF arm_innovator_flash.c
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -392,6 +392,16 @@ package CYGPKG_DEVS_FLASH_ARM_EXCALIBUR on the Altera Excalibur platform." } +package CYGPKG_DEVS_FLASH_ARM_INNOVATOR { + alias { "FLASH memory support for the Innovator" flash_innovator } + directory devs/flash/arm/innovator + script flash_innovator.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the Innovator platform." +} + package CYGPKG_DEVS_FLASH_NANO { alias { "FLASH memory support for Intel SA1110 nanoEngine" flash_nano } directory devs/flash/arm/nano @@ -1221,6 +1231,15 @@ package CYGPKG_DEVS_ETH_ARM_FLEXANET { ethernet device on the Flexanet board." } +package CYGPKG_DEVS_ETH_ARM_INNOVATOR { + alias { "OMAP Innovator onboard ethernet support" devs_eth_arm_innovator } + hardware + directory devs/eth/arm/innovator + script innovator_eth_drivers.cdl + description "This package contains hardware support for onboard SMC91C96 + ethernet device on the Innovator board." +} + package CYGPKG_DEVS_ETH_ARM_INTEGRATOR { alias { "ARM INTEGRATOR with Intel PRO/100+ ethernet driver" devs_eth_arm_integrator integrator_eth_driver } @@ -1970,6 +1989,22 @@ package CYGPKG_HAL_ARM_ARM9_EXCALIBUR { eCos on an Altera Excalibur ARM9 board." } +package CYGPKG_HAL_ARM_ARM9_INNOVATOR { + alias { "Innovator (ARM)" hal_arm_arm9_innovator } + directory hal/arm/arm9/innovator + script hal_arm_arm9_innovator.cdl + hardware + description " + The Innovator HAL package provides the support needed to run + RedBoot on the ARM processor of the Innovator. + + NOTE: Full support for eCos is not provided yet. This HAL + contains only the minimum amount necessary to run RedBoot + on the Innovator. In particular, interrupts are not yet + supported. Watch this space for more details in the near + future." +} + package CYGPKG_HAL_ARM_SA11X0 { alias { "Intel SA11X0 Chipset" hal_arm_sa11x0 } directory hal/arm/sa11x0/var @@ -3310,6 +3345,25 @@ target excalibur_arm9 { eCos on an Altera Excalibur board." } +target innovator { + alias { "Innovator (ARM) board" innovator } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_ARM9 + CYGPKG_HAL_ARM_ARM9_INNOVATOR + CYGPKG_DEVS_FLASH_AMD_AM29XXXXX + CYGPKG_DEVS_FLASH_ARM_INNOVATOR + } + description " + The Innovator HAL package provides the support needed to run + RedBoot on the ARM processor of the Innovator. + + NOTE: Full support for eCos is not provided yet. This HAL + contains only the minimum amount necessary to run RedBoot + on the Innovator. In particular, interrupts are not yet + supported. Watch this space for more details in the near + future." +} + target assabet { alias { "Intel StrongARM SA1110 board" assabet } packages { CYGPKG_HAL_ARM
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/cdl/hal_arm_arm9_innovator.cdl @@ -0,0 +1,429 @@ +# ==================================================================== +# +# hal_arm_arm9_innovator.cdl +# +# TI Innovator platform HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Patrick Doyle <wpd@delcomsys.com> +# Contributors: Patrick Doyle <wpd@delcomsys.com> +# Date: 2002-11-22 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_ARM9_INNOVATOR { + display "Innovator" + parent CYGPKG_HAL_ARM_ARM9 + requires CYGPKG_HAL_ARM_ARM9_ARM925T + hardware + include_dir cyg/hal + define_header hal_arm_arm9_innovator.h + description " + This HAL platform package provides generic + support for the OMAP Innovator platform." + + compile innovator_misc.c hal_diag.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_arm9.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_arm9_innovator.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM9\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Innovator\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK innovator_program_new_stack" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 234" + + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the Innovator it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'RAM' when building programs to load into RAM using RedBoot. + Select 'ROM' when building a stand-alone application + which will be put into ROM, or for the special cases of + building the eCos GDB stubs or RedBoot." + + cdl_option DCSPRI_HAL_ROM_MLT { + display "Memory Layout for ROM Startup" + flavor data + legal_values {"FLASH" "SRAM"} + default_value {"FLASH"} + description " + This option selects which memory layout file should be + used when configuring the Innovator for ROM startup. + The FLASH option selects the memory layout for an image + stored at the beginning of the FLASH. It should be + used almost all of the time. + + The SRAM option is used to place the ROM image in + internal SRAM. It may be used in order to test startup + code without burning the code into FLASH first." } + } + + # Both PLLs are in bypass mode on startup. + # FIXME: Add proper configury + cdl_option CYGNUM_HAL_ARM_INNOVATOR_CPU_CLOCK { + display "CPU bus speed" + flavor data + calculated { 60000000 } + description " + This is the actual CPU operating frequency. Someday you + might be able to change this here." + } + +# cdl_option CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK { +# display "Peripheral bus speed" +# flavor data +# calculated { CYGNUM_HAL_ARM_INNOVATOR_CPU_CLOCK / 2 } +# description " +# This is the peripheral bus operating frequency +# (Traffic Controller)." +# } +# +# cdl_option CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE { +# display "Timer prescale" +# flavor data +# legal_values 0 to 255 +# default_value 16 +# description " +# This is the prescale value used on the clock used to drive +# the kernel counter. Note that some parts of the code may fail +# if this is changed due to over/underflows of expressions." +# } +# +# # Real-time clock/counter specifics +# cdl_component CYGNUM_HAL_RTC_CONSTANTS { +# display "Real-time clock constants. WARNING -- the Real Time Clock is not fully supported (if at all) yet." +# flavor none +# no_define +# +# cdl_option CYGNUM_HAL_RTC_NUMERATOR { +# display "Real-time clock numerator" +# flavor data +# calculated 1000000000 +# } +# cdl_option CYGNUM_HAL_RTC_DENOMINATOR { +# display "Real-time clock denominator" +# flavor data +# calculated 100 +# } +# cdl_option CYGNUM_HAL_RTC_PERIOD { +# display "Real-time clock period" +# flavor data +# calculated 1 +## calculated (CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/(CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE*CYGNUM_HAL_RTC_DENOMINATOR))-1 +# } +# } +# +# cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { +# display "Diagnostic serial port baud rate" +# flavor data +# legal_values 9600 19200 38400 57600 115200 +# default_value 115200 +# description " +# This option selects the baud rate used for the diagnostic port. +# Note: this should match the value chosen for the GDB port if the +# diagnostic and GDB port are the same." +# } +# +# cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { +# display "GDB serial port baud rate" +# flavor data +# legal_values 9600 19200 38400 57600 115200 +# default_value 115200 +# description " +# This option selects the baud rate used for the diagnostic port. +# Note: this should match the value chosen for the GDB port if the +# diagnostic and GDB port are the same." +# } +# + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The Innovator has two serial ports. When we add support + for the second one, you will be able to choose which one is + used to connect to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The Innovator has two serial ports. When we add support + for the second one, you will be able to choose which one is + used for diagnostic output." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "--no-target-default-spec -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors $< gdb_module.tmp + } + } + } + + cdl_component CYGPKG_HAL_ARM_ARM9_INNOVATOR_OPTIONS { + display "Innovator build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_ARM_ARM9_INNOVATOR_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Innovator HAL. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_ARM9_INNOVATOR_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Innovator HAL. These flags are + removed from the set of global flags if present." + } + + cdl_option CYGPKG_HAL_ARM_ARM9_INNOVATOR_TESTS { + display "Innovator tests" + flavor data + no_define + calculated { "" } + description " + This option specifies the set of tests for the Innovator." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_arm9_innovator_ram" : \ + "arm_arm9_innovator_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_arm9_innovator_ram.ldi>" : \ + DCSPRI_HAL_ROM_MLT == "FLASH" ? "<pkgconf/mlt_arm_arm9_innovator_rom.ldi>" : \ + "<pkgconf/mlt_arm_arm9_innovator_sram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_arm9_innovator_ram.h>" : \ + DCSPRI_HAL_ROM_MLT == "FLASH" ? "<pkgconf/mlt_arm_arm9_innovator_rom.h>" : \ + "<pkgconf/mlt_arm_arm9_innovator_sram.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + # RedBoot details + requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x10008000 } + define_proc { + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" + } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to the various relocated SREC images needed + for flash updating." + + compile -library=libextras.a redboot_cmds.c + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/hal_diag.h @@ -0,0 +1,77 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-01 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +// Not the best place for this, but ... +extern void hal_delay_us(cyg_int32 usecs); + +#define HAL_DELAY_US(n) hal_delay_us(n); + +#endif // CYGONCE_HAL_DIAG_H +//----------------------------------------------------------------------------- +// end of hal_diag.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/hal_platform_ints.h @@ -0,0 +1,89 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-01 +// Purpose: Define Interrupt support +// Description: The interrupt details for the Innovator will someday +// be defined here. +// Usage: +// #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/innovator.h> + +// These are interrupts on the Innovator +// TBD +#define CYGNUM_HAL_ISR_COUNT 1 // No interrupt support defined yet. + +// Placeholders +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 0 +// The vector used by the Real time clock -- fake, for now +#define CYGNUM_HAL_INTERRUPT_RTC 0 + + +//---------------------------------------------------------------------------- +// Reset. + +// Enable the watchdog timer to force a reset +#define HAL_PLATFORM_RESET() CYG_MACRO_START \ + cyg_uint16 tmp; \ + HAL_READ_UINT16(CLKM_ARM_IDLECT2, tmp); \ + HAL_WRITE_UINT16(CLKM_ARM_IDLECT2, tmp | 1); \ + HAL_DELAY_US(4); \ + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ + HAL_DELAY_US(4); \ + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ +CYG_MACRO_END + +#define HAL_PLATFORM_RESET_ENTRY 0x10000000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/hal_platform_setup.h @@ -0,0 +1,982 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H +//============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-02 +// Purpose: Innovator platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include CYGHWR_MEMORY_LAYOUT_H +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/innovator.h> // Platform specific hardware definitions + +#define nDEBUG + +#if defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU +#define CYGSEM_HAL_ROM_RESET_USES_JUMP + +// This is a trick. If the first two words of SRAM are 0x12345678 and +// 0x87654321, then, then the reset routine in FLASH branches to the +// third location in SRAM. This allows us to test startup code (which may +// be broken) without writing it to FLASH and rendering the board useless. +// (Well, not permanently useless. Just useless until we track down an +// emulator and reload a working copy of RedBoot.) The nifty thing with +// the innovator is that, if you press and hold the reset button for +// 2 seconds it triggers a power-on-reset. The contents of the internal +// SRAM are maintained across such a reset. Thus, we can write our +// new test version of RedBoot to SRAM (configured with DCSPRI_HAL_ROM_MLT +// set to SRAM) (more on that later), press and hold the reset button, +// and see if the new startup code works. +// +// Now for some notes about this +// 1) I am guessing about the "2 seconds" part. If you press and hold +// the reset button long enough, the FPGA triggers a power-on-reset. +// +// 2) In order to test the SRAM version of RedBoot, import the +// redboot_SRAM.ecm file (instead of redboot_RAM.ecm or redboot_ROM.ecm) +// and build RedBoot. If you already have RedBoot in FLASH, you can +// use that to load redboot.bin with a base address of 0x20000000. +// You will be prompted with a "Gee, I don't think 0x20000000 is +// a valid address in RAM, are you sure you want to do this?" message. +// You should answer "Yes". Here is the command I use: +// +// RedBoot> load -v -r -b 0x20000000 redboot.bin +// +// You can also use the "sloader" application (loaded via +// Code Composer Studio) to to load the S-Record file for the SRAM +// version of RedBoot. +// +// 3) I may have seen a case where the code tested fine in SRAM, but didn't +// work when I placed it in FLASH. But other things could have been +// going on. + +#ifdef DCSPRI_HAL_ROM_MLT_SRAM +#define PLATFORM_PREAMBLE _platform_preamble + .macro _platform_preamble + .long 0x12345678 + .long 0x87654321 + .endm +#endif + + +#if defined(DEBUG) && !defined(DCSPRI_HAL_ROM_MLT_SRAM) +// Don't enable these macro when we are executing from SRAM because +// they overwrite SRAM. + +#define FAKE_LED_MACRO_SETUP \ + ldr r0,=0x20000000; \ + ldr r1,[r0]; \ + subs r2,r1,#0x20000000; \ + movlo r1,#0x20000000; \ + ldr r4,=0x2002fff8; \ + subs r2,r1,r4; \ + movhi r1,#0x20000000; \ + bic r1,r1,#0x3; \ + add r1,r1,#4; \ + str r1, [r0]; + +#define FAKE_LED_MACRO(n) \ + ldr r11,=0x20000000; \ + ldr r11,[r11]; \ + ldr r12,=n; \ + str r12,[r11] +#else +#define FAKE_LED_MACRO_SETUP +#define FAKE_LED_MACRO(n) +#endif + +// This macro represents the initial startup code for the platform + .macro _platform_setup1 + // See if we should branch to an application stored in + // internal SRAM. We do this by checking for a magic cookie + // in the first two locations of SRAM and jumping to the + // third location in SRAM if we find it (after zeroing those + // two locations so we don't create an infinite reboot loop). + ldr r0,=0x12345678 + ldr r1,=0x87654321 + ldr r2,=0x20000000 + ldr r3,[r2] + cmp r3,r0 + ldr r3,[r2,#4] + cmpeq r3,r1 + ldr r3,=0 + streq r3,[r2],#4 + streq r3,[r2],#4 + moveq pc,r2 + + FAKE_LED_MACRO_SETUP + FAKE_LED_MACRO(1) + + //#define PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT +#ifdef PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT + // This is the version of _platform_setup adapted from the contents + // of the GEL script shipped with Code Composer Studio + + // This is all stolen from the ipaq setup + + // Make sure MMU is OFF + mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading + add r2,r0,#0x2000 // cache from the internal memory bank +123: ldr r1,[r0],#16 + cmp r0, r2 + bne 123b + mov r0,#0 + mov r1,#0x0070 // MMU Control System bit + mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache + mcr p15,0,r0,c8,c7,0 // Flush ID TLBs + mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer + mcr p15,0,r0,c7,c10,4 // Drain write buffer + mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping + mcr p15,0,r1,c1,c0,0 // Write MMU control register + nop; nop; nop; nop + + mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr,r0 + + // The rest of this is stolen from "init.c" in the sloader program. + // FIXME -- add configury + // Set up DPLL1: + // (reserved) 00 + // IOB = 1 Initialize on break 1 + // (reserved) 0 + // PLL_MULT = 5 60 MHz clock 0010 1 + // PLL_DIV = 00: CLKOUT = CLKREF 00 + // PLL_ENABLE = 1 Enable DPLL 1 + // BYPASS_DIV = 00: CLKOUT = CLKREF 00 + // (read only) 00 + // + // 0x2290: 0010 0010 1001 0000 + // + + ldr r1,=DPLL1_BASE + ldr r2,=0x2290 + str r2,[r1,#_DPLL_CTL_REG] + /* Wait for lock */ +1: ldr r2,[r1,#_DPLL_CTL_REG] + and r2,r2,#1 + cmp r2,#1 + bne 1b + + /* memif_init() */ + /* Configure ARM9 Memory Interface */ + /* Set up CS0 for memory & bus size of 16 bits, asynchronous read, + * 3 wait states, and a divide by 2 clock. + * Set up CS1, CS2, & CS3 the same way, except with 1 wait state. + */ +/* + TC_EMIFS_CS0_CONFIG = 0x00003339; + TC_EMIFS_CS1_CONFIG = 0x00001139; + TC_EMIFS_CS2_CONFIG = 0x00001139; + TC_EMIFS_CS3_CONFIG = 0x00001139; +*/ + ldr r1,=TC_BASE + ldr r2,=0x3339 + str r2,[r1,#0x10] + ldr r2,=0x1149 + str r2,[r1,#0x14] + ldr r2,=0x1139 + str r2,[r1,#0x18] + str r2,[r1,#0x1c] + + /* Configure the SDRAM */ + /* EMIFF (nCS4) configuration */ + /* TC_EMIFF_SDRAM_CONFIG = 0x000100F4; */ + /* MRS (nCS4) initialization */ + /* TC_EMIFF_MRS = 0x00000037; */ + ldr r2,=0x000100F4 + str r2,[r1,#0x20] + ldr r2,=0x00000037 + str r2,[r1,#0x24] + + /* Disable ARM9 Watchdog Timer by writing the special sequence to it */ +/* + WATCHDOG_TIMER_MODE = 0x00F5; + WATCHDOG_TIMER_MODE = 0x00A0; +*/ + ldr r1,=WATCHDOG_BASE + ldr r2,=0xF5 + strh r2,[r1,#0x08] + ldr r2,=0xA0 + strh r2,[r1,#0x08] + /* Select the 12MHz oscillator for the frequency reference for the + * internal timers. I am doing this today (12/19/02) to simplify my + * life -- This way, I don't care what the clock rate of the core is. + */ + ldr r1,=CLKM_BASE + ldrh r2,[r1,#0x00] // ARM_CKCTL + bic r2,r2,#0x1000 // Set ARM_TIMXO = 0 + strh r2,[r1,#0x00] + + /* Enable the MPUXOR_CK by: + * "MPUXOR_CK ... is derived from CK_REF ... and is enabled by EN_XORPCK" + * + * EN_XORPCK is bit 1 of ARM_IDLECT2 + */ +/* + CLKM_ARM_IDLECT2 |= 0x0002; +*/ + ldrh r2,[r1,#0x08] + orr r2,r2,#0x0082 // Bits 7 (EN_TIMCK) and 1 (EN_XORPCK) + strh r2,[r1,#0x08] + + /* Then set the PER_EN bit to 1 + * + * PER_EN is bit 0 of ARM_RSTCT2 + */ +/* + CLKM_ARM_RSTCT2 |= 0x0001; +*/ + ldrh r2,[r1,#0x14] + orr r2,r2,#0x0001 + strh r2,[r1,#0x14] + + /* Set the "BT_UART_GATING" bit to 1 in the FUNC_MUX_CTRL_0 register. + * This enables the TX1 and RTS1 pins. + */ +/* + CONFIG_FUNC_MUX_CTRL_0 |= BIT_25; +*/ + ldr r1,=CONFIG_BASE + ldr r3,=0x02000000 + ldr r2,[r1,#0x00] + orr r2,r2,r3 + str r2,[r1,#0x00] + + /* Set bit 6 of the FPGA Power Control Register. If I could find some + * documentation on this, I could explain better why I am doing this, but + * for now, emperical evidence suggests that this disables the "shutdown" + * signal to the RS232 level shifter. + */ +/* + FPGA_PWR_CTRL_REG |= BIT_06; +*/ + ldr r1,=FPGA_BASE + ldrb r2,[r1,#0x05] + orr r2,r2,#0x20 +#ifdef ADD_COMPATIBILITY_FOR_THE_EVM_SOMEDAY + orr r2,r2,#0x40 +#endif + strb r2,[r1,#0x05] + + // Set up a stack [for calling C code] +#if defined(CYG_HAL_STARTUP_SLOADER) || defined(CYG_HAL_STARTUP_ROM) + // The startup stack is in internal SRAM + ldr sp,=__startup_stack + // This _MOST_DEFINATELY_ needs to be fixed + orr sp,sp,#0x10000000 +#else + // The startup stack is in SDRAM, at some virtual address, but + // we have not set up the MMU yet, so we need to initialize SP + // with the physical address of '__startup_stack' +#error "Somehow" +#endif + bl hal_mmu_init + + // Enable MMU + ldr r2,=10f + ldr r1,=MMU_Control_Init|MMU_Control_M + mcr MMU_CP,0,r1,MMU_Control,c0 + mov pc,r2 + + // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache + // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs +10: + nop + nop + nop + +#if 0 + ldr r3,=0x20000000 + str r1,[r3] + mrc MMU_CP,0,r1,MMU_Control,c0 + str r1,[r3, #0x04] + mrc p15,0,r1,c15,c1,0 + str r1,[r3, #0x08] + +here: + // b here +#endif +#else // PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT + // This is all stolen from the ipaq setup + + // Make sure MMU is OFF + mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading + add r2,r0,#0x2000 // cache from the internal memory bank +123: ldr r1,[r0],#16 + cmp r0, r2 + bne 123b + mov r0,#0 + mov r1,#0x0070 // MMU Control System bit + mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache + mcr p15,0,r0,c8,c7,0 // Flush ID TLBs + mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer + mcr p15,0,r0,c7,c10,4 // Drain write buffer + mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping + mcr p15,0,r1,c1,c0,0 // Write MMU control register + nop; nop; nop; nop + FAKE_LED_MACRO(2) + + mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr,r0 + FAKE_LED_MACRO(3) + + // This is the platform setup adapted from the rrload setup implied + // by head_omap1510.S + +// Disable the Watchdog Timer. +// --------------------------- + mov r1, #0xF5 + ldr r0, REG_WDT_TIMER_MODE + strh r1, [r0] // Set WDTIM Mode + mov r1, #0xA0 + strh r1, [r0] // Set WDTIM Mode + FAKE_LED_MACRO(4) + +// setting for DPLL1 control register. +// ---------------------------------- + ldr r0, REG_DPLL1_CTL + mov r1, #0x10 + strh r1, [r0] +// Continue to loop if bit shows "not locked" +poll1: + ldrh r1, [r0] + ands r1, r1, #0x01 + beq poll1 + FAKE_LED_MACRO(5) + +// Init Arm9 processor. +// -------------------- + mrs r0, cpsr // Get current mode bits. + bic r0, r0, #0x1f // Clear mode bits. + orr r0, r0, #0xd3 // Disable IRQs/FIQs, supervisor mode. + msr cpsr, r0 // Enter Supervisor mode. + mov r1, #0x81 // Set ARM925T configuration. + mcr p15, 0, r1, c15, c1, 0 // Write ARM925T configuration register. + FAKE_LED_MACRO(6) + +// Disable All Interrupts +// ----------- + ldr r1, V_0xffffffff + ldr r0, REG_IHL1_MIR + str r1, [r0] + ldr r0, REG_IHL2_MIR + str r1, [r0] + FAKE_LED_MACRO(7) + +// Determine if this is a 1509 or 1510, then +// set the Configuration Registers accordingly +// 1509 shows 0, 1510 shows 0x1b47002f +// ------------------- + ldr r0, REG_IDCODE + ldr r1, [r0] + cmp r1, #0x0 + beq omap1509 + FAKE_LED_MACRO(8) + +// OK, so we're a 1510. +omap1510: +/* + Errata for ES1 says to do this: + + 1) Check for power-on or warm reset. + 2) Configure SDRAM controller depending on reset type. +*/ + // Check for reset type + ldr r0, REG_ARM_SYSST + ldrh r1, [r0] + mov r2, #0x20 + tst r2, r1 + beq zzz_warm_reset + FAKE_LED_MACRO(9) + +POR: + // Wait 100mS for SDRAM to stabilize before + // configuring SDRAM controller. + // Number guessed at. + mov r0, #0x2000 +1: subs r0, r0, #0x1 + bne 1b + FAKE_LED_MACRO(10) + + b after_initial_configure_SDRAM + +zzz_warm_reset: + FAKE_LED_MACRO(11) + + // Set auto-refresh counter value to 1. + // Program MRS to appropriate CAS latency + // Wait for SDRAM array to be completely + // refreshed, 1 cycle * #SDRAM rows. + ldr r0, REG_TC_EMIFF_SDRAM_CONFIG + mov r1, #0x100 + str r1, [r0] + ldr r0, REG_TC_EMIFF_MRS + ldr r1, VAL_TC_EMIFF_MRS + str r1, [r0] + mov r2, #0x2000 +1: subs r2, r2, #0x1 + bne 1b + ldr r0, REG_TC_EMIFF_SDRAM_CONFIG + mov r1, #0x10000 + str r1, [r0] + +after_initial_configure_SDRAM: + FAKE_LED_MACRO(12) + + +// Config Spec says to write values +// to each of the configuration registers, +// then take the chip out of 1509 compatibility mode. + + ldr r0, REG_PULL_DWN_CTRL_0 + ldr r1, VAL_PULL_DWN_CTRL_0 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_1 + ldr r1, VAL_PULL_DWN_CTRL_1 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_2 + ldr r1, VAL_PULL_DWN_CTRL_2 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_3 + ldr r1, VAL_PULL_DWN_CTRL_3 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_4 + ldr r1, VAL_FUNC_MUX_CTRL_4 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_5 + ldr r1, VAL_FUNC_MUX_CTRL_5 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_6 + ldr r1, VAL_FUNC_MUX_CTRL_6 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_7 + ldr r1, VAL_FUNC_MUX_CTRL_7 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_8 + ldr r1, VAL_FUNC_MUX_CTRL_8 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_9 + ldr r1, VAL_FUNC_MUX_CTRL_9 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_A + ldr r1, VAL_FUNC_MUX_CTRL_A + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_B + ldr r1, VAL_FUNC_MUX_CTRL_B + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_C + ldr r1, VAL_FUNC_MUX_CTRL_C + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_D + ldr r1, VAL_FUNC_MUX_CTRL_D + str r1, [r0] + ldr r0, REG_VOLTAGE_CTRL_0 + ldr r1, VAL_VOLTAGE_CTRL_0 + str r1, [r0] + ldr r0, REG_TEST_DBG_CTRL_0 + ldr r1, VAL_TEST_DBG_CTRL_0 + str r1, [r0] + ldr r0, REG_MOD_CONF_CTRL_0 + ldr r1, VAL_MOD_CONF_CTRL_0 + str r1, [r0] + FAKE_LED_MACRO(13) + + // Take out of compatibility mode + ldr r0, REG_COMP_MODE_CTRL_0 + ldr r1, VAL_COMP_MODE_CTRL_0 + str r1, [r0] + FAKE_LED_MACRO(14) + + b post_config_registers + +omap1509: + ldr r0, REG_FUNC_MUX_CTRL_0 + ldr r1, [r0] + orr r1, r1, #0x6000000 // UART_GIGA_GATE bit as well as UART_BT_GATE bit + str r1, [r0] +// Errata for ES5.5 says this must be done before DSP or MPU can +// access internal RAMs. This is benign for earlier revs. + ldr r0, REG_FUNC_MUX_CTRL_1 + mov r1, #0xc + str r1, [r0] + +post_config_registers: + FAKE_LED_MACRO(15) + mov r0, #0x1800 +again: + subs r0, r0, #0x1 + bne again + FAKE_LED_MACRO(16) + +// Invalidate cache +// ----------------- + mov r0,#0 + nop + mcr p15, 0x0, r0, c7, c5, 0x0 + nop + nop + nop + nop + FAKE_LED_MACRO(17) + +// Enable I-Cache +// ------------- + mrc p15, 0x0, r1, c1, c0, 0x0 + orr r1, r1, #0x1000 + nop + mcr p15, 0x0, r1, c1, c0, 0x0 + nop + nop + nop + nop + FAKE_LED_MACRO(18) + +// Initialize Traffic Controller (TC) +// ---------------------------------- + ldr r0, REG_TC_IMIF_PRIO + mov r1, #0x0 + str r1, [r0] + ldr r0, REG_TC_EMIFS_PRIO + str r1, [r0] + ldr r0, REG_TC_EMIFF_PRIO + str r1, [r0] + + ldr r0, REG_TC_EMIFS_CONFIG + ldr r1, [r0] + bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ + bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ + str r1, [r0] // EMIFS GlB Configuration. (value 0x12 most likely) + +// Set TC chip select registers +// SDRAM value based on 168MHz 1510. +// ---------------------------- + ldr r0, REG_TC_EMIFS_CS1_CONFIG + ldr r1, VAL_TC_EMIFS_CS1_CONFIG_PRELIM + str r1, [r0] + ldr r0, REG_TC_EMIFS_CS2_CONFIG + ldr r1, VAL_TC_EMIFS_CS2_CONFIG_PRELIM + str r1, [r0] + ldr r0, REG_TC_EMIFF_SDRAM_CONFIG + ldr r1, VAL_TC_EMIFF_SDRAM_CONFIG + str r1, [r0] + ldr r0, REG_TC_EMIFF_MRS + ldr r1, VAL_TC_EMIFF_MRS + str r1, [r0] + + mov r0,#0x1800 +again2: + subs r0,r0,#0x1 + bne again2 + FAKE_LED_MACRO(19) + + // Next, Enable the RS232 Line Drivers in the FPGA. + // Also, power on the audio CODEC's amplifier here, + // which will make a noise on the audio output. + // This is done here instead of in the kernel so there + // isn't a loud popping noise at the start of each + // song. + // Also, disable the CODEC's clocks. + // omap1510-HelenP1 [specific] + ldr r0, REG_FPGA_POWER + mov r1, #0 + ldr r2, REG_FPGA_DIP_SWITCH + ldrb r3, [r2] + cmp r3, #0x8 + movne r1, #0x62 // Enable the RS232 Line Drivers in the EPLD + strb r1, [r0] + ldr r0, REG_FPGA_AUDIO + mov r1, #0x0 // Disable sound driver (CODEC clocks) + strb r1, [r0] + + mov r0, #0x1800 +again0: + subs r0, r0, #0x1 + bne again0 + FAKE_LED_MACRO(20) + +// Init RHEA +// ---------- + ldr r1, V_0x0000ff22 + mov r0, #0x0 + str r1, [r0] // yep, that's really a write to address 0x00000000. + +// *revisit-skranz* is needed? + mov r0, #0x1800 +again12: + subs r0, r0, #0x1 + bne again12 + FAKE_LED_MACRO(21) + +// Misc 2 +// ------ + mov r1, #0xfb + ldr r0, REG_LB_CLOCK_DIV + str r1, [r0] + +// *revisit-skranz* is needed? + mov r0, #0x1800 +again4: + subs r0, r0, #0x1 + bne again4 + FAKE_LED_MACRO(22) + +// ARM Clock Module Setup +// ---------------------- + mov r1, #0x40 + ldr r0, REG_ARM_IDLECT2 + strh r1, [r0] // CLKM, Clock domain control. + + mov r1, #0x01 // PER_EN bit + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] // CLKM; Peripheral reset. + + // Reset CLKM +#ifdef ORIGINAL_CODE + mov r1, #0x06 // Needed for UART[12] +#else + mov r1, #0x86 // Needed for UART[12] +#endif + ldr r0, REG_ARM_IDLECT2 + strh r1, [r0] // CLKM, Clock domain control. + + // Set CLKM to Sync-Scalable + mov r1, #0x1000 // Needed for UART[12] + ldr r0, REG_ARM_SYSST + strh r1, [r0] + +// *revisit-skranz* is needed? + mov r0, #0x1800 +again6: + subs r0, r0, #0x1 + bne again6 + FAKE_LED_MACRO(23) + + ldr r1, VAL_ARM_CKCTL + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + +// setup DPLL1 Control Register +// ---------------------------- + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 // Check if PLL is enabled. + beq finish2 // Do not look for lock if BYPASS selected +poll2: + ldrh r1, [r0] + ands r1, r1, #0x01 // Check the LOCK bit. + beq poll2 // ...loop until bit goes hi. +finish2: + FAKE_LED_MACRO(24) + + // Setup TC EMIFS configuration. + // CS0 value based on 168MHz + // --------------------------------------------------- + ldr r1, VAL_TC_EMIFS_CS0_CONFIG // increase flash speed. + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] // Chip Select 0 + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] // Chip Select 1 + ldr r1, VAL_TC_EMIFS_CS2_CONFIG + ldr r0, REG_TC_EMIFS_CS2_CONFIG + str r1, [r0] // Chip Select 2 + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] // Chip Select 3 + +// *revisit-skranz* is needed? + mov r0, #0x1800 +again9: + subs r0, r0, #0x1 + bne again9 + FAKE_LED_MACRO(25) + + // The following was added by WPD + // Set up a stack [for calling C code] +#ifdef CYG_HAL_STARTUP_ROM + // The startup stack is in internal SRAM + ldr sp,=__startup_stack + // This _MOST_DEFINATELY_ needs to be fixed + orr sp,sp,#0x10000000 +#else + // The startup stack is in SDRAM, at some virtual address, but + // we have not set up the MMU yet, so we need to initialize SP + // with the physical address of '__startup_stack' +#error "Somehow" +#endif + bl hal_mmu_init + FAKE_LED_MACRO(26) + + // Enable MMU + ldr r2,=10f + ldr r1,=MMU_Control_Init|MMU_Control_M + mcr MMU_CP,0,r1,MMU_Control,c0 + mov pc,r2 + + // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache + // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs +10: + nop + nop + nop + FAKE_LED_MACRO(27) + +#if 0 + ldr r3,=0x20000000 + str r1,[r3] + mrc MMU_CP,0,r1,MMU_Control,c0 + str r1,[r3, #0x04] + mrc p15,0,r1,c15,c1,0 + str r1,[r3, #0x08] + +here: + // b here +#endif +#endif + .endm + +#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT) +#define PLATFORM_SETUP1 +#endif + +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h + +// ------------------------------------------------------ +// --------------Static Data Definitions----------------- +// ------------------------------------------------------ + +/* inernal OMAP registers */ + /* interrupt handler level 2 registers */ +REG_IHL2_MIR: /* 32 bits */ + .word 0xfffe0004 + /* OMAP configuration registers */ +REG_FUNC_MUX_CTRL_0: /* 32 bits */ + .word 0xfffe1000 +REG_FUNC_MUX_CTRL_1: /* 32 bits */ + .word 0xfffe1004 +REG_FUNC_MUX_CTRL_2: /* 32 bits */ + .word 0xfffe1008 +REG_COMP_MODE_CTRL_0: /* 32 bits */ + .word 0xfffe100c +REG_FUNC_MUX_CTRL_3: /* 32 bits */ + .word 0xfffe1010 +REG_FUNC_MUX_CTRL_4: /* 32 bits */ + .word 0xfffe1014 +REG_FUNC_MUX_CTRL_5: /* 32 bits */ + .word 0xfffe1018 +REG_FUNC_MUX_CTRL_6: /* 32 bits */ + .word 0xfffe101c +REG_FUNC_MUX_CTRL_7: /* 32 bits */ + .word 0xfffe1020 +REG_FUNC_MUX_CTRL_8: /* 32 bits */ + .word 0xfffe1024 +REG_FUNC_MUX_CTRL_9: /* 32 bits */ + .word 0xfffe1028 +REG_FUNC_MUX_CTRL_A: /* 32 bits */ + .word 0xfffe102C +REG_FUNC_MUX_CTRL_B: /* 32 bits */ + .word 0xfffe1030 +REG_FUNC_MUX_CTRL_C: /* 32 bits */ + .word 0xfffe1034 +REG_FUNC_MUX_CTRL_D: /* 32 bits */ + .word 0xfffe1038 +REG_PULL_DWN_CTRL_0: /* 32 bits */ + .word 0xfffe1040 +REG_PULL_DWN_CTRL_1: /* 32 bits */ + .word 0xfffe1044 +REG_PULL_DWN_CTRL_2: /* 32 bits */ + .word 0xfffe1048 +REG_PULL_DWN_CTRL_3: /* 32 bits */ + .word 0xfffe104c +REG_VOLTAGE_CTRL_0: /* 32 bits */ + .word 0xfffe1060 +REG_TEST_DBG_CTRL_0: /* 32 bits */ + .word 0xfffe1070 +REG_MOD_CONF_CTRL_0: /* 32 bits */ + .word 0xfffe1080 + /* local bus control registers */ +REG_LB_CLOCK_DIV: /* 32 bits */ + .word 0xfffec10c + /* watchdog timer registers */ +REG_WDT_TIMER_MODE: /* 16 bits */ + .word 0xfffec808 + /* interrupt handler level 1 registers */ +REG_IHL1_MIR: /* 32 bits */ + .word 0xfffecb04 + /* traffic controller memory interface registers */ +REG_TC_IMIF_PRIO: /* 32 bits */ + .word 0xfffecc00 +REG_TC_EMIFS_PRIO: /* 32 bits */ + .word 0xfffecc04 +REG_TC_EMIFF_PRIO: /* 32 bits */ + .word 0xfffecc08 +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c +REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ + .word 0xfffecc20 +REG_TC_EMIFF_MRS: /* 32 bits */ + .word 0xfffecc24 + /* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 + /* DPLL control registers */ +REG_DPLL1_CTL: /* 16 bits */ + .word 0xfffecf00 + /* identification code register */ +REG_IDCODE: /* 32 bits */ + .word 0xfffed404 + +/* board-specific registers */ + +REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ + .word 0x08000003 +REG_FPGA_POWER: /* 8 bits */ + .word 0x08000005 +REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ + .word 0x0800000c +REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ + .word 0x0800000e + +/* constants */ + +VAL_COMP_MODE_CTRL_0: + .word 0x0000eaef +VAL_FUNC_MUX_CTRL_4: + .word 0x00000000 +VAL_FUNC_MUX_CTRL_5: + .word 0x00000000 +VAL_FUNC_MUX_CTRL_6: + .word 0x00000001 +VAL_FUNC_MUX_CTRL_7: + .word 0x00000000 +VAL_FUNC_MUX_CTRL_8: + .word 0x10001200 +VAL_FUNC_MUX_CTRL_9: + .word 0x01201012 +VAL_FUNC_MUX_CTRL_A: + .word 0x00000248 +VAL_FUNC_MUX_CTRL_B: + .word 0x00000248 +VAL_FUNC_MUX_CTRL_C: + .word 0x09000000 +VAL_FUNC_MUX_CTRL_D: + .word 0x00000000 +VAL_PULL_DWN_CTRL_0: + .word 0x11a10000 +VAL_PULL_DWN_CTRL_1: + .word 0x2e047fff +VAL_PULL_DWN_CTRL_2: + .word 0xffd7d3e6 +VAL_PULL_DWN_CTRL_3: + .word 0x00003f03 +VAL_VOLTAGE_CTRL_0: + .word 0x00000007 +VAL_TEST_DBG_CTRL_0: + /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs + * says to write a 7. Don't know what the right thing is to do, so + * I'm leaving it at 7 since that's what was already here. + */ + .word 0x00000007 +VAL_MOD_CONF_CTRL_0: + .word 0x0b000008 +VAL_ARM_CKCTL: +#ifdef ORIGINAL_CODE + .word 0x110f +#else + .word 0x010f +#endif +VAL_DPLL1_CTL: + .word 0x2710 +VAL_TC_EMIFS_CS1_CONFIG_PRELIM: + .word 0x00001149 +VAL_TC_EMIFS_CS2_CONFIG_PRELIM: + .word 0x00004158 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x002130b0 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x0000f559 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0x000055f0 +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x00003331 +VAL_TC_EMIFF_SDRAM_CONFIG: + .word 0x010290fc +VAL_TC_EMIFF_MRS: + .word 0x00000027 + +V_0xffffffff: + .word 0xffffffff + +V_0x0000ff22: + .word 0x0000ff22 +#endif // CYGONCE_HAL_PLATFORM_SETUP_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/innovator.h @@ -0,0 +1,491 @@ +#ifndef CYGONCE_INNOVATOR_H +#define CYGONCE_INNOVATOR_H + +//============================================================================= +// +// innovator.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-01 +// Purpose: Innovator platform specific support definitions +// Description: +// Usage: #include <cyg/hal/innovator.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_arm_arm9_innovator.h> + +// Memory mapping +#define FLASH_CS0_BASE 0x00000000 +#define FLASH_CS1_BASE 0x04000000 +#define FLASH_CS2_BASE 0x08000000 +#define FLASH_CS3_BASE 0x0C000000 +#define SDRAM_BASE 0x10000000 +#define INTERNAL_SRAM_BASE 0x20000000 + +// Most of this should be moved to a separate omap.h or omap_1510.h file +// CLKM Registers +#define CLKM_BASE 0xFFFECE00 +#define _CLKM_ARM_CKCTL 0x00 +#define _CLKM_ARM_IDLECT1 0x04 +#define _CLKM_ARM_IDLECT2 0x08 +#define _CLKM_ARM_EWUPCT 0x0C +#define _CLKM_ARM_RSTCT1 0x10 +#define _CLKM_ARM_RSTCT2 0x14 +#define _CLKM_ARM_SYSST 0x18 + +#define CLKM_ARM_CKCTL (volatile short *)(CLKM_BASE + _CLKM_ARM_CKCTL) +#define CLKM_ARM_IDLECT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT1) +#define CLKM_ARM_IDLECT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT2) +#define CLKM_ARM_EWUPCT (volatile short *)(CLKM_BASE + _CLKM_ARM_EWUPCT) +#define CLKM_ARM_RSTCT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT1) +#define CLKM_ARM_RSTCT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT2) +#define CLKM_ARM_SYSST (volatile short *)(CLKM_BASE + _CLKM_ARM_SYSST) + +// Watchdog Registers +#define WATCHDOG_BASE 0xFFFEC800 +#define _WD_CNTL_TIMER 0x00 +#define _WD_LOAD_TIM 0x04 +#define _WD_READ_TIM 0x04 +#define _WD_TIMER_MODE 0x08 + +#define WATCHDOG_CNTL_TIMER (volatile short *)(WATCHDOG_BASE + _WD_CNTL_TIMER) +#define WATCHDOG_LOAD_TIM (volatile short *)(WATCHDOG_BASE + _WD_LOAD_TIM) +#define WATCHDOG_READ_TIM (volatile short *)(WATCHDOG_BASE + _WD_READ_TIM) +#define WATCHDOG_TIMER_MODE (volatile short *)(WATCHDOG_BASE + _WD_TIMER_MODE) + +/* Nothing below this line has been scrubbed yet */ +/* DPLL Registers */ +#define DPLL1_BASE 0xFFFECF00 +#define DPLL2_BASE 0xFFFED000 +#define DPLL3_BASE 0xFFFED100 + +#define _DPLL_CTL_REG 0x00 + +#define DPLL1_CTL_REG (volatile short *)(DPLL1_BASE + _DPLL_CTL_REG) +#define DPLL2_CTL_REG (volatile short *)(DPLL2_BASE + _DPLL_CTL_REG) +#define DPLL3_CTL_REG (volatile short *)(DPLL3_BASE + _DPLL_CTL_REG) + +#define FPGA_BASE 0x08000000 /* CS2_BASE */ +#define CONFIG_BASE 0xFFFE1000 +#define TC_BASE 0xFFFECC00 + +/* FPGA Registers */ +#define FPGA_PWR_CTRL_REG (*(volatile char *)(FPGA_BASE + 0x05)) + +/* Configuration Registers */ +#define CONFIG_FUNC_MUX_CTRL_0 (*(volatile unsigned *)(CONFIG_BASE + 0x00)) +#define CONFIG_FUNC_MUX_CTRL_1 (*(volatile unsigned *)(CONFIG_BASE + 0x04)) +#define CONFIG_FUNC_MUX_CTRL_2 (*(volatile unsigned *)(CONFIG_BASE + 0x08)) + +/* Traffic Controller Registers */ +#define TC_IMIF_PRIO (*(volatile unsigned *)(TC_BASE + 0x00)) +#define TC_EMIFS_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x04)) +#define TC_EMIFF_PRIO_REG (*(volatile unsigned *)(TC_BASE + 0x08)) +#define TC_EMIFS_CONFIG_REG (*(volatile unsigned *)(TC_BASE + 0x0C)) +#define TC_EMIFS_CS0_CONFIG (*(volatile unsigned *)(TC_BASE + 0x10)) +#define TC_EMIFS_CS1_CONFIG (*(volatile unsigned *)(TC_BASE + 0x14)) +#define TC_EMIFS_CS2_CONFIG (*(volatile unsigned *)(TC_BASE + 0x18)) +#define TC_EMIFS_CS3_CONFIG (*(volatile unsigned *)(TC_BASE + 0x1C)) +#define TC_EMIFF_SDRAM_CONFIG (*(volatile unsigned *)(TC_BASE + 0x20)) +#define TC_EMIFF_MRS (*(volatile unsigned *)(TC_BASE + 0x24)) +#define TC_TIMEOUT1 (*(volatile unsigned *)(TC_BASE + 0x28)) +#define TC_TIMEOUT2 (*(volatile unsigned *)(TC_BASE + 0x2C)) +#define TC_TIMEOUT3 (*(volatile unsigned *)(TC_BASE + 0x30)) +#define TC_ENDIANISM (*(volatile unsigned *)(TC_BASE + 0x34)) + +/* Believe it or not, these actually make the code more readable in a few + * places. + */ +#ifndef BIT_00 +#define BIT_00 0x00000001 +#define BIT_01 0x00000002 +#define BIT_02 0x00000004 +#define BIT_03 0x00000008 +#define BIT_04 0x00000010 +#define BIT_05 0x00000020 +#define BIT_06 0x00000040 +#define BIT_07 0x00000080 +#define BIT_08 0x00000100 +#define BIT_09 0x00000200 +#define BIT_10 0x00000400 +#define BIT_11 0x00000800 +#define BIT_12 0x00001000 +#define BIT_13 0x00002000 +#define BIT_14 0x00004000 +#define BIT_15 0x00008000 +#define BIT_16 0x00010000 +#define BIT_17 0x00020000 +#define BIT_18 0x00040000 +#define BIT_19 0x00080000 +#define BIT_20 0x00100000 +#define BIT_21 0x00200000 +#define BIT_22 0x00400000 +#define BIT_23 0x00800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 +#endif + +// We are using this +#define INNOVATOR_FLASH_VIRT_BASE 0x10000000 +// #define INNOVATOR_FLASH_PHYS_BASE 0x00000000 +#define INNOVATOR_SDRAM_PHYS_BASE 0x10000000 + +#if 0 +#define INNOVATOR_BASE INNOVATOR_REGS_PHYS_BASE + +//----------------------------------------------------------------------------- +// Boot control +// Note: this register is actually write-bit-to-clear-it +#define INNOVATOR_BOOT_CR (INNOVATOR_BASE + 0x0000) + +#define INNOVATOR_BOOT_CR_BM 0x00000001 +#define INNOVATOR_BOOT_CR_HM 0x00000002 +#define INNOVATOR_BOOT_CR_RE 0x00000004 + +//----------------------------------------------------------------------------- +// DPSRAM config +#define INNOVATOR_DPSRAM_BASE (INNOVATOR_BASE + 0x0030) +#define _DPSRAM0_SR 0x0000 +#define _DPSRAM0_LCR 0x0004 +#define _DPSRAM1_SR 0x0008 +#define _DPSRAM1_LCR 0x000c + +#define _DPSRAM0_LCR_INIT 0x00000000 +#define _DPSRAM1_LCR_INIT 0x00000000 + +//----------------------------------------------------------------------------- +// IO controller +#define INNOVATOR_IOCR_BASE (INNOVATOR_BASE + 0x0040) +#define _IOCR_SDRAM 0x0000 +#define _IOCR_EBI 0x0004 +#define _IOCR_UART 0x0008 +#define _IOCR_TRACE 0x000c + +#define _IOCR_OC_PCI 0x00000008 +#define _IOCR_OC_FAST 0x00000004 +#define _IOCR_OC_SLOW 0x00000000 +#define _IOCR_IO_STRIPE 0x00000002 +#define _IOCR_LOCK 0x00000001 + +#define INNOVATOR_IOCR_SDRAM_INIT (_IOCR_OC_FAST | _IOCR_IO_STRIPE | _IOCR_LOCK) +#define INNOVATOR_IOCR_EBI_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK) +#define INNOVATOR_IOCR_UART_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK) + + +//----------------------------------------------------------------------------- +// Memory mapping +#define INNOVATOR_MMAP_BASE (INNOVATOR_BASE + 0x0080) +#define _MMAP_REGISTERS 0x0000 +#define _MMAP_SRAM0 0x0010 +#define _MMAP_SRAM1 0x0014 +#define _MMAP_DPSRAM0 0x0020 +#define _MMAP_DPSRAM1 0x0024 +#define _MMAP_SDRAM0 0x0030 +#define _MMAP_SDRAM1 0x0034 +#define _MMAP_EBI0 0x0040 +#define _MMAP_EBI1 0x0044 +#define _MMAP_EBI2 0x0048 +#define _MMAP_EBI3 0x004c +#define _MMAP_PLD0 0x0050 +#define _MMAP_PLD1 0x0054 +#define _MMAP_PLD2 0x0058 +#define _MMAP_PLD3 0x005c + +#define _MMAP_SIZE_16K (13<<7) +#define _MMAP_SIZE_64K (15<<7) +#define _MMAP_SIZE_128K (16<<7) +#define _MMAP_SIZE_1M (19<<7) +#define _MMAP_SIZE_4M (21<<7) +#define _MMAP_SIZE_16M (23<<7) +#define _MMAP_SIZE_32M (24<<7) +#define _MMAP_SIZE_64M (25<<7) + +#define _MMAP_PREFETCH 0x00000000 +#define _MMAP_NOPREFETCH 0x00000002 + +#define _MMAP_ENABLE 0x00000001 +#define _MMAP_DISABLE 0x00000000 + +#define _MMAP_REGISTERS_INIT (INNOVATOR_REGS_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) +#define _MMAP_SRAM0_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_SRAM1_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00020000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_DPSRAM0_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00040000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_DPSRAM1_INIT (INNOVATOR_SRAM_PHYS_BASE + 0x00050000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_SDRAM0_INIT (INNOVATOR_SDRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_SDRAM1_INIT (INNOVATOR_SDRAM_PHYS_BASE + 0x04000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_EBI0_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00000000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_EBI1_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00400000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_EBI2_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00800000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_EBI3_INIT (INNOVATOR_FLASH_PHYS_BASE + 0x00c00000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE) +#define _MMAP_PLD0_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) +//#define _MMAP_PLD1_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00004000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) +#define _MMAP_PLD1_INIT (0x0f000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) +#define _MMAP_PLD2_INIT (INNOVATOR_PLD_PHYS_BASE + 0x00008000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) +#define _MMAP_PLD3_INIT (INNOVATOR_PLD_PHYS_BASE + 0x0000c000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE) + + + + + +//----------------------------------------------------------------------------- +// Timers +#define INNOVATOR_TIMER0_CR (INNOVATOR_BASE+0x0200) +#define INNOVATOR_TIMER0_PRE (INNOVATOR_BASE+0x0210) +#define INNOVATOR_TIMER0_LIMIT (INNOVATOR_BASE+0x0220) +#define INNOVATOR_TIMER0_READ (INNOVATOR_BASE+0x0230) + +#define INNOVATOR_TIMER1_CR (INNOVATOR_BASE+0x0240) +#define INNOVATOR_TIMER1_PRE (INNOVATOR_BASE+0x0250) +#define INNOVATOR_TIMER1_LIMIT (INNOVATOR_BASE+0x0260) +#define INNOVATOR_TIMER1_READ (INNOVATOR_BASE+0x0270) + +#define INNOVATOR_TIMER_CR_MODE_HEARBEAT 0x00000000 +#define INNOVATOR_TIMER_CR_MODE_ONE_SHOT 0x00000001 +#define INNOVATOR_TIMER_CR_IE 0x00000004 +#define INNOVATOR_TIMER_CR_CI 0x00000008 +#define INNOVATOR_TIMER_CR_S 0x00000010 + +//----------------------------------------------------------------------------- +// Serial +#define INNOVATOR_UART0_BASE (INNOVATOR_BASE+0x0280) +#define _UART_RSR 0x0000 +#define _UART_RDS 0x0004 +#define _UART_RD 0x0008 +#define _UART_TSR 0x000c +#define _UART_TD 0x0010 +#define _UART_FCR 0x0014 +#define _UART_IES 0x0018 +#define _UART_IEC 0x001c +#define _UART_ISR 0x0020 +#define _UART_IID 0x0024 +#define _UART_MC 0x0028 +#define _UART_MCR 0x002c +#define _UART_MSR 0x0030 +#define _UART_DIV_LO 0x0034 +#define _UART_DIV_HI 0x0038 + +#define _UART_RSR_RX_LEVEL 0x0000001f + +#define _UART_TSR_TXI 0x00000080 + +#define _UART_FCR_TC 0x00000001 +#define _UART_FCR_RC 0x00000002 +#define _UART_FCR_TX_THR_15 0x0000001c +#define _UART_FCR_RX_THR_1 0x00000000 + +#define _UART_INTS_RE 0x00000001 +#define _UART_INTS_RI _UART_INTS_RE +#define _UART_INTS_TE 0x00000002 +#define _UART_INTS_TI _UART_INTS_TE +#define _UART_INTS_TIE 0x00000004 +#define _UART_INTS_TII _UART_INTS_TIE +#define _UART_INTS_ME 0x00000008 +#define _UART_INTS_MI _UART_INTS_ME + + +#define _UART_MC_8BIT 0x00000003 +#define _UART_MC_1STOP 0x00000000 +#define _UART_MC_PARITY_NONE 0x00000000 + +//----------------------------------------------------------------------------- +// Clock controller +#define INNOVATOR_CLK_BASE (INNOVATOR_BASE + 0x0300) +#define _CLK_PLL1_NCNT 0x0000 +#define _CLK_PLL1_MCNT 0x0004 +#define _CLK_PLL1_KCNT 0x0008 +#define _CLK_PLL1_CTRL 0x000c +#define _CLK_PLL2_NCNT 0x0010 +#define _CLK_PLL2_MCNT 0x0014 +#define _CLK_PLL2_KCNT 0x0018 +#define _CLK_PLL2_CTRL 0x001c +#define _CLK_DERIVE 0x0020 +#define _CLK_STATUS 0x0024 +#define _CLK_AHB1_COUNT 0x0028 + +#define _CLK_PLL1_CTRL_P 0x00000001 +#define _CLK_PLL2_CTRL_P 0x00000001 + +#define _CLK_DERIVE_BP1 (1<<12) +#define _CLK_DERIVE_BP2 (1<<13) + +#define _CLK_STATUS_L1 0x00000001 +#define _CLK_STATUS_L2 0x00000002 +#define _CLK_STATUS_C1 0x00000004 +#define _CLK_STATUS_C2 0x00000008 + +// Settings from Altera example code. Note that this differs from the +// magic values described in the manual. I think the values are +// supposed to disable the PLLs, making the core run at 25MHz and +// peripherals at 12.5MHz +#define _CLK_PLL1_CTRL_INIT 0x00001064 +#define _CLK_PLL2_CTRL_INIT 0x00001064 +#define _CLK_DERIVE_INIT 0x00003010 + +//----------------------------------------------------------------------------- +// Expansion Bus Interface +#define INNOVATOR_EBI_CR (INNOVATOR_BASE + 0x0380) + +#define INNOVATOR_EBI_CR_EO 0x00000008 + +#define INNOVATOR_EBI_CR_INIT (INNOVATOR_EBI_CR_EO) + +//----------------------------------------------------------------------------- +// SDRAM controller +#define INNOVATOR_SDRAM_BASE (INNOVATOR_BASE + 0x0400) +#define _SDRAM_TIMING1 0x0000 +#define _SDRAM_TIMING2 0x0004 +#define _SDRAM_CONFIG 0x0008 +#define _SDRAM_REFRESH 0x000c +#define _SDRAM_ADDR 0x0010 +#define _SDRAM_INIT 0x001c +#define _SDRAM_MODE0 0x0020 +#define _SDRAM_MODE1 0x0024 +#define INNOVATOR_SDRAM_WIDTH (INNOVATOR_BASE + 0x007c) + + +#define _SDRAM_WIDTH_W 0x00000002 +#define _SDRAM_WIDTH_LK 0x00000001 + +#if 0 +// Max delays +#define _SDRAM_TIMING1_INIT 0x00009124 +// CAS-2, 8 words burst, 3 clock refresh +#define _SDRAM_TIMING2_INIT 0x00000788 +// SDR +#define _SDRAM_CONFIG_INIT 0x00000000 +// Refresh period of 15us - at a clock of 75MHz that's 1125 cycles +#define _SDRAM_REFRESH_INIT 1125 +// Rows (12) & columns (10) +#define _SDRAM_ADDR_INIT 0x0000ca80 +// SDRAM mode (from Micron MT48LC16M8A2 manual) +// M0-2: burst length = 3 (8 words) +// M3 : burst type = 0 (sequential vs interleaved) +// M4-6: CAS latency = 2 +// M7-8: operating mode = 0 +// M9 : write burst mode = 0 (writes are also in burst) +#define _SDRAM_MODE0_INIT ((2<<4)|3) +// Unused (for DDR) +#define _SDRAM_MODE1_INIT 0x00000000 +#endif + +#define _SDRAM_INIT_EN 0x00008000 +#define _SDRAM_INIT_PR 0x00004000 +#define _SDRAM_INIT_LM 0x00002000 +#define _SDRAM_INIT_LEM 0x00001000 +#define _SDRAM_INIT_RF 0x00000800 +#define _SDRAM_INIT_BS 0x00000400 +#define _SDRAM_INIT_SR 0x00000200 + +//----------------------------------------------------------------------------- +// Watchdog controller +#define INNOVATOR_WDOG_CR (INNOVATOR_BASE+0x0a00) +#define INNOVATOR_WDOG_COUNT (INNOVATOR_BASE+0x0a04) +#define INNOVATOR_WDOG_RELOAD (INNOVATOR_BASE+0x0a08) + +//----------------------------------------------------------------------------- +// Interrupt controller +#define INNOVATOR_INT_MASK_SET (INNOVATOR_BASE+0x0c00) +#define INNOVATOR_INT_MASK_CLEAR (INNOVATOR_BASE+0x0c04) +#define INNOVATOR_INT_SOURCE_STATUS (INNOVATOR_BASE+0x0c08) +#define INNOVATOR_INT_REQUEST_STATUS (INNOVATOR_BASE+0x0c0c) +#define INNOVATOR_INT_ID (INNOVATOR_BASE+0x0c10) +#define INNOVATOR_INT_PLD_PRIORITY (INNOVATOR_BASE+0x0c14) +#define INNOVATOR_INT_INT_MODE (INNOVATOR_BASE+0x0c18) +#define INNOVATOR_INT_PRIORITY_0 (INNOVATOR_BASE+0x0c80) +#define INNOVATOR_INT_PRIORITY_1 (INNOVATOR_BASE+0x0c84) +#define INNOVATOR_INT_PRIORITY_2 (INNOVATOR_BASE+0x0c88) +#define INNOVATOR_INT_PRIORITY_3 (INNOVATOR_BASE+0x0c8c) +#define INNOVATOR_INT_PRIORITY_4 (INNOVATOR_BASE+0x0c90) +#define INNOVATOR_INT_PRIORITY_5 (INNOVATOR_BASE+0x0c94) +#define INNOVATOR_INT_PRIORITY_6 (INNOVATOR_BASE+0x0c98) +#define INNOVATOR_INT_PRIORITY_7 (INNOVATOR_BASE+0x0c9c) +#define INNOVATOR_INT_PRIORITY_8 (INNOVATOR_BASE+0x0ca0) +#define INNOVATOR_INT_PRIORITY_9 (INNOVATOR_BASE+0x0ca4) +#define INNOVATOR_INT_PRIORITY_10 (INNOVATOR_BASE+0x0ca8) +#define INNOVATOR_INT_PRIORITY_11 (INNOVATOR_BASE+0x0cac) +#define INNOVATOR_INT_PRIORITY_12 (INNOVATOR_BASE+0x0cb0) +#define INNOVATOR_INT_PRIORITY_13 (INNOVATOR_BASE+0x0cb4) +#define INNOVATOR_INT_PRIORITY_14 (INNOVATOR_BASE+0x0cb8) +#define INNOVATOR_INT_PRIORITY_15 (INNOVATOR_BASE+0x0cbc) +#define INNOVATOR_INT_PRIORITY_16 (INNOVATOR_BASE+0x0cc0) + +#define INNOVATOR_INT_SOURCE_P0 0x00000001 +#define INNOVATOR_INT_SOURCE_P1 0x00000002 +#define INNOVATOR_INT_SOURCE_P2 0x00000004 +#define INNOVATOR_INT_SOURCE_P3 0x00000008 +#define INNOVATOR_INT_SOURCE_P4 0x00000010 +#define INNOVATOR_INT_SOURCE_P5 0x00000020 +#define INNOVATOR_INT_SOURCE_IP 0x00000040 +#define INNOVATOR_INT_SOURCE_UA 0x00000080 +#define INNOVATOR_INT_SOURCE_T0 0x00000100 +#define INNOVATOR_INT_SOURCE_T1 0x00000200 +#define INNOVATOR_INT_SOURCE_PS 0x00000400 +#define INNOVATOR_INT_SOURCE_EE 0x00000800 +#define INNOVATOR_INT_SOURCE_PE 0x00001000 +#define INNOVATOR_INT_SOURCE_AE 0x00002000 +#define INNOVATOR_INT_SOURCE_CT 0x00004000 +#define INNOVATOR_INT_SOURCE_CR 0x00008000 +#define INNOVATOR_INT_SOURCE_FC 0x00010000 + +#define INNOVATOR_INT_PRIORITY_FIQ 0x00000040 +#define INNOVATOR_INT_PRIORITY_LVL_mask 0x0000003f + +//----------------------------------------------------------------------------- +// PLD +#define INNOVATOR_PLD_BASE INNOVATOR_PLD_PHYS_BASE + +#define INNOVATOR_PLD_LEDS (INNOVATOR_PLD_BASE + 0x0100) + + +#endif +#endif // CYGONCE_INNOVATOR_H +//----------------------------------------------------------------------------- +// end of innovator.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x02000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (rom, 0x20000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x10000000) +#define CYGMEM_REGION_rom_SIZE (0x00400000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_rom.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x02000000 + rom : ORIGIN = 0x10000000, LENGTH = 0x00400000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x10000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING(.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_sram.h @@ -0,0 +1,20 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00030000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/pkgconf/mlt_arm_arm9_innovator_sram.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Tue Aug 07 11:15:51 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x02000000 + sram : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram, 0x20000000, LMA_EQ_VMA) + SECTION_text (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (sram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING(.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/plf_io.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_ARM_ARM9_INNOVATOR_PLF_IO_H +#define CYGONCE_HAL_ARM_ARM9_INNOVATOR_PLF_IO_H + +/*============================================================================= +// +// plf_io.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2003-01-15 +// Purpose: Platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_io.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <cyg/hal/innovator.h> + +#if 0 +#define CYGARC_PHYSICAL_ADDRESS(x) (x) +#else +#define HACK_SDRAM_VIRT_BASE 0x00000000 +#define HACK_SDRAM_SIZE 0x02000000 +#define HACK_SDRAM_MASK 0x01ffffff +#define HACK_SDRAM_PHYS_BASE 0x10000000 + +#define HACK_FLASH_VIRT_BASE 0x10000000 +#define HACK_FLASH_SIZE 0x00400000 +#define HACK_FLASH_MASK 0x003fffff +#define HACK_FLASH_PHYS_BASE 0x00000000 + +#define CYGARC_PHYSICAL_ADDRESS(_x_) \ +({ CYG_ADDRWORD _p = (CYG_ADDRWORD)(_x_); \ + if (_p >= HACK_SDRAM_VIRT_BASE && \ + _p < (HACK_SDRAM_VIRT_BASE+HACK_SDRAM_SIZE)) \ + _p = (_p & HACK_SDRAM_MASK) + HACK_SDRAM_PHYS_BASE; \ + else if (_p >= HACK_FLASH_VIRT_BASE && \ + _p < (HACK_FLASH_VIRT_BASE+HACK_FLASH_SIZE)) \ + _p = (_p & HACK_FLASH_MASK) + HACK_FLASH_PHYS_BASE; \ + _p; }) +#endif +#endif // CYGONCE_HAL_ARM_ARM9_INNOVATOR_PLF_IO_H +// EOF plf_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/include/plf_stub.h @@ -0,0 +1,84 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributor: Patrick Doyle <wpd@delcomsys.com> +// Date: 2003-01-15 +// Purpose: Platform HAL stub support for Innovator boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/arm_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/misc/redboot_RAM.ecm @@ -0,0 +1,114 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware innovator ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_ARM9 current ; + package -hardware CYGPKG_HAL_ARM_ARM9_INNOVATOR current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_INNOVATOR current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package CYGPKG_DEVS_ETH_ARM_INNOVATOR current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_ARM_ARM9_ARM925T { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00030000 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x10008000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL323D { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/misc/redboot_ROM.ecm @@ -0,0 +1,114 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware innovator ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_ARM9 current ; + package -hardware CYGPKG_HAL_ARM_ARM9_INNOVATOR current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_INNOVATOR current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package CYGPKG_DEVS_ETH_ARM_INNOVATOR current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_ARM_ARM9_ARM925T { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00030000 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x10008000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL323D { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/misc/redboot_SRAM.ecm @@ -0,0 +1,122 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware innovator ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_ARM9 current ; + package -hardware CYGPKG_HAL_ARM_ARM9_INNOVATOR current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_INNOVATOR current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package CYGPKG_DEVS_ETH_ARM_INNOVATOR current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_ARM_ARM9_ARM925T { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option DCSPRI_HAL_ROM_MLT { + user_value SRAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x10008000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL323D { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/src/hal_diag.c @@ -0,0 +1,572 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors:Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-17 +// Purpose: HAL diagnostic output +// This file contains the type definitions, constants, and function +// prototoypes that implement very simple access to the UART on the +// OMAP part. +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // basic machine info +#include <cyg/hal/hal_intr.h> // interrupt macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/innovator.h> // platform definitions + +//----------------------------------------------------------------------------- + +#define CYG_DEVICE_SERIAL_BAUD_DIV (CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD/16) +#define CYG_DEVICE_SERIAL_BAUD_LSB (CYG_DEVICE_SERIAL_BAUD_DIV&0xff) +#define CYG_DEVICE_SERIAL_BAUD_MSB ((CYG_DEVICE_SERIAL_BAUD_DIV>>8)&0xff) + +//----------------------------------------------------------------------------- +typedef struct { + cyg_int32 msec_timeout; +#ifdef LATER + cyg_uint32 base; + int isr_vector; +#endif +} channel_data_t; + +/************************************************************************ + * Useful definitions -- note that 'USE_MODEM_UART' has not been extensively + * tested nor debugged (read -- it probably doesn't work). + ************************************************************************/ +/*#define USE_MODEM_UART*/ +#ifdef USE_MODEM_UART +#define BASE_ADDR 0xfffce800 +#define STRIDE 1 +#else +#define BASE_ADDR 0xfffb0000 +#define STRIDE 4 +#endif + +#define RHR 0x00 +#define THR 0x00 +#define DLL 0x00 +#define DLH 0x01 +#define IER 0x01 +#define FCR 0x02 +#define EFR 0x02 +#define IIR 0x02 +#define LCR 0x03 +#define MCR 0x04 +#define XON1 0x04 +#define LSR 0x05 +#define XON2 0x05 +#define MSR 0x06 +#define TCR 0x06 +#define XOFF1 0x06 +#define SPR 0x07 +#define TLR 0x07 +#define XOFF2 0x07 +#define MDR1 0x08 +#define UASR 0x0e +#define SCR 0x10 +#define SSR 0x11 +#define OSC_12M 0x13 + + +/************************************************************************ + * Data local to this file + ************************************************************************/ +#define write_serial(offset, value) \ + *(volatile char *)(BASE_ADDR + STRIDE * (offset)) = value + +#define read_serial(offset) \ + (*(volatile char *)(BASE_ADDR + STRIDE * (offset))) + +/************************************************************************ + * Forward References + ************************************************************************/ + +/************************************************************************ + * Function: + * init_uart() + * + * Purpose: + * This procedure may be called in order to initialize the UART + * prior to use. + * + * Operation: + * Set up the UART for 115,200 baud, 8 bits, 1 stop bit, no parity. + * + * The UART is defined by the 'BASE_ADDR' macro. + * + * Notes/Issues: + * This pays some lip service to being able to use UART3, but since + * it seems to me that the use of UART3 requires that the DSP do + * some setup (at least, until I learn more), it probably won't + * work for UART3. + ************************************************************************/ +static void +quick_init_uart(void) +{ + /* UART Software Reset */ + write_serial(LCR, 0xBF); /* Access to EFR & UART break is removed */ + write_serial(EFR, BIT_04); /* Set EFR[4] = 0x1 */ + write_serial(LCR, 0x00); /* Access to IER & MCR is allowed */ + + write_serial(IER, 0x00); /* Disable all interrupts */ + write_serial(MCR, 0x00); /* DTR, RTS, XON, loopbback inactive */ + + write_serial(MDR1,0x07); /* UART is in reset */ + + /* UART FIFO Configuration */ + write_serial(MCR, read_serial(MCR) | BIT_06); /* Set MCR[6] = 1 */ + write_serial(TCR, 0x0F); /* RTS off when Rx FIFO at 60 bytes, on at 0 */ + write_serial(TLR, 0x88); /* set TX & RX trigger levels each to 32 */ + write_serial(FCR, 0x07); /* Enable & reset FIFOs, triggers at 8 */ + write_serial(LCR, 0xBF); /* Access EFR */ + write_serial(EFR, 0xC0); /* Enable auto RTS & CTS */ + write_serial(LCR, 0x00); /* Access to IER & MCR is allowed */ + write_serial(MCR, read_serial(MCR) & ~BIT_06); /* Clear MCR[6] */ + + /* Baud Rate and Stop Configuration */ + write_serial(LCR, 0x03); /* 8,N,1 */ +#ifdef USE_MODEM_UART + write_serial(LCR, 0x83); /* gain access to DLH and DLL */ + write_serial(DLH, 0x00); /* Divisor value = Operating Freq/(16 x Baud Rate) */ + write_serial(DLL, 0x0D); /* DPLL2 configured for Operating Freq = 24 MHz */ + /* Baud Rate = 115,200 bps */ +#else + write_serial(OSC_12M, 1);/* Set divisor value to 6.5 */ + write_serial(LCR, 0x83); /* gain access to DLH and DLL */ + write_serial(DLH, 0x00); /* Divisor value = + * Operating Freq/(16 x 6.5 x Baud Rate) */ + write_serial(DLL, 0x01); /* DPLL2 configured for Operating Freq = 12 MHz */ + /* Baud Rate = 115,200 bps */ +#endif + write_serial(LCR, 0x03); /* restore LCR */ + + write_serial(MDR1,0x00); /* enable UART */ +} + +/************************************************************************ + * Function: + * putchar(c) + * + * Purpose: + * This procedure may be called in order to output a character on + * the serial port. It blocks until the serial port TX FIFO is + * empty. + * + * Operation: + * Write character to the Transmit Holding Register (THR). Can + * optionally map the Linefeed character to a Carriage Return + * character and/or output a Carriage Return character whenever + * a Linefeed character is seen, depending on #ifdefs. + * + * Notes/Issues: + * This could be optimized to block only when the serial port TX + * FIFO is full. + ************************************************************************/ +static void +quick_putchar(char c) +{ +/* #define MAP_LF_TO_CR */ +#ifdef MAP_LF_TO_CR + if (c == '\n') { + c = '\r'; + } +#endif + while ((read_serial(LSR) & 0x20) == 0) ; + write_serial(THR, c); + +/* #define DO_CRLF */ +#ifdef DO_CRLF + if (c == '\n') { + quick_putchar('\r'); + } +#endif +} + +/************************************************************************ + * Function: + * getchar() + * + * Purpose: + * This function may be called in order to read a character from + * the serial port. + * + * Operation: + * Poll the Line Status register until it indicates a character has + * been received. Return the character to the caller. + * + * Notes/Issues: + * + ************************************************************************/ +static int +quick_getchar(void) +{ + while ((read_serial(LSR) & 0x01) == 0) ; + return(read_serial(RHR)); +} + +/************************************************************************ + * Function: + * getchar_nonblock() + * + * Purpose: + * This function may be called in order to read a character from + * the serial port. + * + * Operation: + * Poll the Line Status register until it indicates a character has + * been received. Return the character to the caller. + * + * Notes/Issues: + * + ************************************************************************/ +static int +quick_getchar_nonblock(char *c) +{ + if ((read_serial(LSR) & 0x01) == 0) { + return(0); + } else { + *c = read_serial(RHR); + return(1); + } +} + +//----------------------------------------------------------------------------- + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ +#ifdef LATER + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + + // 8-1-no parity. + HAL_WRITE_UINT32(base+_UART_MC, _UART_MC_8BIT | _UART_MC_1STOP | _UART_MC_PARITY_NONE); + + HAL_WRITE_UINT32(base+_UART_DIV_LO, CYG_DEVICE_SERIAL_BAUD_LSB); + HAL_WRITE_UINT32(base+_UART_DIV_HI, CYG_DEVICE_SERIAL_BAUD_MSB); + HAL_WRITE_UINT32(base+_UART_FCR, (_UART_FCR_TC | _UART_FCR_RC | + _UART_FCR_TX_THR_15 | _UART_FCR_RX_THR_1)); // clear & enableFIFO + + // enable RX interrupts - otherwise ISR cannot be polled. Actual + // interrupt control of serial happens via INT_MASK + HAL_WRITE_UINT32(base+_UART_IES, _UART_INTS_RE); +#endif +} + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c) +{ +#ifdef LATER + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 tsr; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT32(base+_UART_TSR, tsr); + // Wait for TXI flag to be set - or for the register to be + // zero (works around a HW bug it seems). + } while (tsr && (tsr & _UART_TSR_TXI) == 0); + + HAL_WRITE_UINT32(base+_UART_TD, (cyg_uint32)(unsigned char)c); + + CYGARC_HAL_RESTORE_GP(); +#else + quick_putchar(c); +#endif +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ +#ifdef LATER + cyg_uint32 base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 rsr, isr, data; + + HAL_READ_UINT32(base+_UART_ISR, isr); + if (0 == (isr & _UART_INTS_RI)) { + HAL_READ_UINT32(base+_UART_RSR, rsr); + if (0 == rsr) + return false; + } + + HAL_READ_UINT32(base+_UART_RD, data); + *ch = (cyg_uint8)(data & 0xff); + + // Read RSR to clear interrupt, and RDS to clear errors + HAL_READ_UINT32(base+_UART_RSR, data); + HAL_READ_UINT32(base+_UART_RDS, data); + + return true; +#else + return(quick_getchar_nonblock(ch)); +#endif +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ +#ifdef LATER + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +#else + return(quick_getchar()); +#endif +} + +static channel_data_t innovator_ser_channels[1] = { + { 1000 } +}; + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + // Need to keep it enabled to allow polling using ISR + //HAL_WRITE_UINT32(chan->base+_UART_IES, _UART_INTS_RE); + +#ifdef LATER + HAL_INTERRUPT_UNMASK(chan->isr_vector); +#endif + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + // Need to keep it enabled to allow polling using ISR + // HAL_WRITE_UINT32(chan->base+_UART_IEC, _UART_INTS_RE); + +#ifdef LATER + HAL_INTERRUPT_MASK(chan->isr_vector); +#endif + break; + case __COMMCTL_DBG_ISR_VECTOR: +#ifdef LATER + ret = chan->isr_vector; +#else + ret = 0; +#endif + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ +#ifdef LATER + int res = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint32 isr, ch, rsr; + char c; + CYGARC_HAL_SAVE_GP(); + + cyg_drv_interrupt_acknowledge(chan->isr_vector); + + *__ctrlc = 0; + HAL_READ_UINT32(chan->base+_UART_ISR, isr); + HAL_READ_UINT32(chan->base+_UART_RSR, rsr); + + // Again, check both RI and the RX FIFO count. + if ( ((isr & _UART_INTS_RI) != 0 ) || (rsr) ) { + + HAL_READ_UINT32(chan->base+_UART_RD, ch); + + c = (char)ch; + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +#else + return 0; +#endif +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + +#ifdef LATER + // Disable interrupts. + HAL_INTERRUPT_MASK(innovator_ser_channels[0].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel(&innovator_ser_channels[0]); +#else + quick_init_uart(); +#endif + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &innovator_ser_channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// LEDs +void +hal_diag_led(int n) +{ +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/src/innovator_misc.c @@ -0,0 +1,452 @@ +//========================================================================== +// +// innovator_misc.c +// +// HAL misc board support code for ARM9/INNOVATOR +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-12-17 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/innovator.h> // Platform specifics + +#include <cyg/infra/diag.h> // diag_printf + +externC void *memset(void*, int, size_t); + +// ------------------------------------------------------------------------- +// MMU initialization: +// +// These structures are laid down in memory to define the translation +// table. +// + +// ARM Translation Table Base Bit Masks +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +// ARM Domain Access Control Bit Masks +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + int id : 2; + int imp : 2; + int domain : 4; + int sbz : 1; + int base_address : 23; +}; +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + int id : 2; + int b : 1; + int c : 1; + int imp : 1; + int domain : 4; + int sbz0 : 1; + int ap : 2; + int sbz1 : 8; + int base_address : 12; +}; +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + int id : 2; + int sbz : 30; +}; +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + CYG_MACRO_START \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.imp = 1; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + CYG_MACRO_END + +#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \ + { int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--,j++,k++) \ + { \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +void +hal_mmu_init(void) +{ + unsigned long ttb_base = INNOVATOR_SDRAM_PHYS_BASE + 0x4000; + unsigned long i; + + // Set the TTB register + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + // Set the Domain Access Control Register + i = ARM_ACCESS_TYPE_MANAGER(0) | + ARM_ACCESS_TYPE_NO_ACCESS(1) | + ARM_ACCESS_TYPE_NO_ACCESS(2) | + ARM_ACCESS_TYPE_NO_ACCESS(3) | + ARM_ACCESS_TYPE_NO_ACCESS(4) | + ARM_ACCESS_TYPE_NO_ACCESS(5) | + ARM_ACCESS_TYPE_NO_ACCESS(6) | + ARM_ACCESS_TYPE_NO_ACCESS(7) | + ARM_ACCESS_TYPE_NO_ACCESS(8) | + ARM_ACCESS_TYPE_NO_ACCESS(9) | + ARM_ACCESS_TYPE_NO_ACCESS(10) | + ARM_ACCESS_TYPE_NO_ACCESS(11) | + ARM_ACCESS_TYPE_NO_ACCESS(12) | + ARM_ACCESS_TYPE_NO_ACCESS(13) | + ARM_ACCESS_TYPE_NO_ACCESS(14) | + ARM_ACCESS_TYPE_NO_ACCESS(15); + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + // First clear all TT entries - ie Set them to Faulting + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + // Actual Virtual Size Attributes Function + // Base Base MB cached? buffered? access permissions + // xxx00000 xxx00000 + X_ARM_MMU_SECTION(0x000, 0x100, 4, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // FLASH CS0 + X_ARM_MMU_SECTION(0x100, 0x000, 32, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SDRAM + X_ARM_MMU_SECTION(0x080, 0x080, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // FPGA + X_ARM_MMU_SECTION(0x200, 0x200, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Internal SRAM + X_ARM_MMU_SECTION(0xE00, 0xE00, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Internal Peripherals +} + +//---------------------------------------------------------------------------- +// Platform specific initialization + +void +plf_hardware_init(void) +{ +#ifdef LATER + // Disable PLD interrupts + HAL_WRITE_UINT32(INNOVATOR_INT_MASK_CLEAR, + INNOVATOR_INT_SOURCE_P0 | INNOVATOR_INT_SOURCE_P1 | + INNOVATOR_INT_SOURCE_P2 | INNOVATOR_INT_SOURCE_P3 | + INNOVATOR_INT_SOURCE_P4 | INNOVATOR_INT_SOURCE_P5); + // Make PLD0 generate IRQ + HAL_WRITE_UINT32(INNOVATOR_INT_PRIORITY_0, 0); +#endif + cyg_uint8 tmp; + // This should be protected by some sort of #ifdef to test to see if + // the ethernet has been enabled or not. I'll add that later. + HAL_READ_UINT8(0x0800000B, tmp); + HAL_WRITE_UINT8(0x0800000B, tmp & ~1); + HAL_DELAY_US(750); + +} + +// ------------------------------------------------------------------------- +void +hal_clock_initialize(cyg_uint32 period) +{ +#ifdef LATER + cyg_uint32 cr; + + HAL_WRITE_UINT32(INNOVATOR_TIMER0_CR, 0); + HAL_WRITE_UINT32(INNOVATOR_TIMER0_PRE, CYGNUM_HAL_ARM_INNOVATOR_TIMER_PRESCALE - 1); + HAL_WRITE_UINT32(INNOVATOR_TIMER0_LIMIT, period); + cr = INNOVATOR_TIMER_CR_MODE_HEARBEAT | INNOVATOR_TIMER_CR_IE; + HAL_WRITE_UINT32(INNOVATOR_TIMER0_CR, cr); + HAL_WRITE_UINT32(INNOVATOR_TIMER0_CR, cr | INNOVATOR_TIMER_CR_S); + + // Unmask timer 0 interrupt + HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 ); + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC ); +#endif +} + +// This routine is called during a clock interrupt. +void +hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ +#ifdef LATER + cyg_uint32 cr; + + // Clear pending interrupt bit + HAL_READ_UINT32(INNOVATOR_TIMER0_CR, cr); + cr |= INNOVATOR_TIMER_CR_CI; + HAL_WRITE_UINT32(INNOVATOR_TIMER0_CR, cr); +#endif +} + +// Read the current value of the clock, returning the number of hardware +// "ticks" that have occurred (i.e. how far away the current value is from +// the start) + +void +hal_clock_read(cyg_uint32 *pvalue) +{ +#ifdef LATER + cyg_uint32 ctr; + + HAL_READ_UINT32(INNOVATOR_TIMER0_READ, ctr); + *pvalue = ctr; +#endif +} + +// +// Delay for some number of micro-seconds +// +void +hal_delay_us(cyg_int32 usecs) +{ +#ifdef LATER + // Use timer 2 + cyg_uint32 cr; + // Divide by 1000000 in two steps to preserve precision. + cyg_uint32 wait_clocks = ((CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/100000)*usecs)/10; + + HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, 0); + HAL_WRITE_UINT32(INNOVATOR_TIMER1_PRE, 0); + HAL_WRITE_UINT32(INNOVATOR_TIMER1_LIMIT, wait_clocks); + cr = INNOVATOR_TIMER_CR_MODE_ONE_SHOT|INNOVATOR_TIMER_CR_CI; + HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, cr); + HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, cr | INNOVATOR_TIMER_CR_S); + + // wait for start bit to clear + do { + HAL_READ_UINT32(INNOVATOR_TIMER1_CR, cr); + } while ((INNOVATOR_TIMER_CR_S & cr) != 0); + + //clear interrupt flag + HAL_WRITE_UINT32(INNOVATOR_TIMER1_CR, 0); +#else +#if 0 + volatile unsigned long long x; + volatile unsigned long long loop_count = usecs / 10 + 1; + + for (x = 0; x < loop_count; x++) ; +#else + volatile cyg_uint32 *CNTL_TIMER = (volatile cyg_uint32 *)(0xFFFEC500 + 0x00); + volatile cyg_uint32 *LOAD_TIM = (volatile cyg_uint32 *)(0xFFFEC500 + 0x04); + volatile cyg_uint32 *READ_TIM = (volatile cyg_uint32 *)(0xFFFEC500 + 0x08); + cyg_uint32 timer_val, prev_val; + int too_long = 0; + + if (usecs <= 0) { + return; + } else if (usecs > 357913941) { + /* Clamp at MAX_INT32 / 6 */ + usecs = 357913941; + } + /* Enable the clock and halt the timer */ + HAL_WRITE_UINT32(CNTL_TIMER, 0x00000020); + + /* Load the timer */ + HAL_WRITE_UINT32(LOAD_TIM, 6 * usecs); + + /* Start the timer */ + HAL_READ_UINT32(READ_TIM, prev_val); + HAL_WRITE_UINT32(CNTL_TIMER, 0x00000021); + + /* Wait for it to load (but not too long) */ + do { + HAL_READ_UINT32(READ_TIM, timer_val); + if (++too_long >= 100) { + break; + } + } while (timer_val == prev_val); + + /* Wait for it to count down to zero */ + do { + HAL_READ_UINT32(READ_TIM, timer_val); + } while (timer_val > 0); +#endif +#endif +} + +// ------------------------------------------------------------------------- + +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. +int +hal_IRQ_handler(void) +{ +#ifdef LATER + int vec; + cyg_uint32 isr; + + HAL_READ_UINT32(INNOVATOR_INT_REQUEST_STATUS, isr); + for (vec = CYGNUM_HAL_INTERRUPT_PLD_0; + vec <= CYGNUM_HAL_INTERRUPT_FAST_COMMS; vec++) { + if (isr & (1<<vec)) { + return vec; + } + } +#endif + return CYGNUM_HAL_INTERRUPT_NONE; +} + +//---------------------------------------------------------------------------- +// Interrupt control +// +void +hal_interrupt_mask(int vector) +{ +#ifdef LATER + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_WRITE_UINT32(INNOVATOR_INT_MASK_CLEAR, 1<<vector); +#endif +} + +void +hal_interrupt_unmask(int vector) +{ +#ifdef LATER + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + HAL_WRITE_UINT32(INNOVATOR_INT_MASK_SET, 1<<vector); +#endif +} + +void +hal_interrupt_acknowledge(int vector) +{ +#ifdef LATER + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); +#endif + +} + +void +hal_interrupt_configure(int vector, int level, int up) +{ +#ifdef LATER + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); + CYG_ASSERT(level || up, "Cannot do falling edge"); +#endif +} + +void +hal_interrupt_set_level(int vector, int level) +{ +#ifdef LATER + cyg_uint32 reg; + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); + CYG_ASSERT(level <= 63 && level >= 0, "Invalid level"); + + HAL_READ_UINT32(INNOVATOR_INT_PRIORITY_0+4*vector, reg); + reg &= ~INNOVATOR_INT_PRIORITY_LVL_mask; + reg |= (level & INNOVATOR_INT_PRIORITY_LVL_mask); + HAL_WRITE_UINT32(INNOVATOR_INT_PRIORITY_0+4*vector, reg); +#endif +} + +#include CYGHWR_MEMORY_LAYOUT_H +typedef void code_fun(void); +void innovator_program_new_stack(void *func) +{ + register CYG_ADDRESS stack_ptr asm("sp"); + register CYG_ADDRESS old_stack asm("r4"); + register code_fun *new_func asm("r0"); + old_stack = stack_ptr; + stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS); + new_func = (code_fun*)func; + new_func(); + stack_ptr = old_stack; + return; +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/arm9/innovator/current/src/redboot_cmds.c @@ -0,0 +1,301 @@ +#if 0 +//========================================================================== +// +// redboot_cmds.c +// +// OMAP1510DC EVM [platform] specific RedBoot commands +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Patrick Doyle <wpd@delcomsys.com> +// Contributors: Patrick Doyle <wpd@delcomsys.com> +// Date: 2002-11-27 +// Purpose: +// Description: +// +// This code is part of RedBoot (tm). It was modified from "redboot_cmds" +// for the iPaq by wpd in order to add some platform specific commands to +// the OMAP1510DC EVM platform. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <redboot.h> + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/innovator.h> + +static void do_mem(int argc, char *argv[]); +static void do_try_reset(int argc, char *argv[]); +static void do_testsdram(int argc, char *argv[]); +static void do_delay(int argc, char *argv[]); + +RedBoot_cmd("mem", + "Set a memory location", + "[-h|-b] [-n] [-a <address>] <data>", + do_mem + ); + +RedBoot_cmd("try_reset", + "try to reset the platform", + "[-1|-2|-3|-4]", + do_try_reset + ); + + +RedBoot_cmd("testsdram", + "test SDRAM (very simply)", + "[-l length]", + do_testsdram + ); + +RedBoot_cmd("delay", + "delay specified number of usecs", + "[-c count] amount", + do_delay + ); + + +static void +do_mem(int argc, + char *argv[]) +{ + struct option_info opts[4]; + bool mem_half_word, mem_byte; + bool no_verify = false; + static int address = 0x00000000; + int value; + init_opts(&opts[0], 'b', false, OPTION_ARG_TYPE_FLG, + (void**)&mem_byte, 0, "write a byte"); + init_opts(&opts[1], 'h', false, OPTION_ARG_TYPE_FLG, + (void**)&mem_half_word, 0, "write a half-word"); + init_opts(&opts[2], 'a', true, OPTION_ARG_TYPE_NUM, + (void**)&address, NULL, "address to write at"); + init_opts(&opts[3], 'n', false, OPTION_ARG_TYPE_FLG, + (void**)&no_verify, 0, "noverify"); + + if (!scan_opts(argc, argv, + 1, + opts, sizeof(opts) / sizeof(opts[0]), + (void*)&value, OPTION_ARG_TYPE_NUM, "address to set")) { + return; + } + + if ( mem_byte && mem_half_word ) { + diag_printf("*ERR: Should not specify both byte and half-word access\n"); + } else if ( mem_byte ) { + *(cyg_uint8*)address = (cyg_uint8)(value & 255); + if (no_verify) { + diag_printf(" Set 0x%08X to 0x%02X\n", + address, value & 255); + } else { + diag_printf(" Set 0x%08X to 0x%02X (result 0x%02X)\n", + address, value & 255, (int)*(cyg_uint8*)address ); + } + } else if ( mem_half_word ) { + if ( address & 1 ) { + diag_printf( "*ERR: Badly aligned address 0x%08X for half-word store\n", + address ); + } else { + *(cyg_uint16*)address = (cyg_uint16)(value & 0xffff); + if (no_verify) { + diag_printf(" Set 0x%08X to 0x%04X\n", + address, value & 0xffff); + } else { + diag_printf(" Set 0x%08X to 0x%04X (result 0x%04X)\n", + address, value & 0xffff, (int)*(cyg_uint16*)address ); + } + } + } else { + if ( address & 3 ) { + diag_printf( "*ERR: Badly aligned address 0x%08X for word store\n", + address ); + } else { + *(cyg_uint32*)address = (cyg_uint32)value; + if (no_verify) { + diag_printf(" Set 0x%08X to 0x%08X\n", + address, value); + } else { + diag_printf(" Set 0x%08X to 0x%08X (result 0x%08X)\n", + address, value, (int)*(cyg_uint32*)address ); + } + } + } +} + +static void +do_try_reset(int argc, + char *argv[]) +{ + struct option_info opts[4]; + bool flag_1 = false; + bool flag_2 = false; + bool flag_3 = false; + bool flag_4 = false; + + cyg_uint16 tmp = 0; + + init_opts(&opts[0], '1', false, OPTION_ARG_TYPE_FLG, + (void**)&flag_1, 0, "only try phase 1"); + init_opts(&opts[1], '2', false, OPTION_ARG_TYPE_FLG, + (void**)&flag_2, 0, "try phase 1 & phase 2"); + init_opts(&opts[2], '3', false, OPTION_ARG_TYPE_FLG, + (void**)&flag_3, 0, "try phase 1 through phase 3"); + init_opts(&opts[3], '4', false, OPTION_ARG_TYPE_FLG, + (void**)&flag_4, 0, "try phase 1 through phase 4"); + + if (!scan_opts(argc, argv, + 1, + opts, sizeof(opts) / sizeof(opts[0]), + 0, 0, 0)) { + return; + } + diag_printf("flag_4 = %d, flag_3 = %d, flag_2 = %d, flag_1 = %d\n", + flag_4, flag_3, flag_2, flag_1); + if (flag_4) { + flag_3 = flag_2 = flag_1 = true; + } else if (flag_3) { + flag_2 = flag_1 = true; + } else if (flag_2) { + flag_1 = true; + } + diag_printf("flag_4 = %d, flag_3 = %d, flag_2 = %d, flag_1 = %d\n", + flag_4, flag_3, flag_2, flag_1); + + if (flag_1) { + HAL_READ_UINT16(CLKM_ARM_IDLECT2, tmp); + diag_printf("tmp = %04X\n", tmp); + } + + if (flag_2) { + tmp |= 1; + diag_printf("Writing %04X to %08X\n", tmp, CLKM_ARM_IDLECT2); + HAL_WRITE_UINT16(CLKM_ARM_IDLECT2, tmp | 1); + } + + if (flag_3) { + diag_printf("Writing %04X to %08X\n", 0x80F5, WATCHDOG_TIMER_MODE); + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ + } + + if (flag_4) { + diag_printf("Writing %04X to %08X\n", 0x80F5, WATCHDOG_TIMER_MODE); + HAL_WRITE_UINT16(WATCHDOG_TIMER_MODE, 0x80F5); \ + } + + diag_printf("try_reset: done\n"); +} + +#define SDRAM_BASE 0x10000000 +#define SDRAM_LEN (32*1024*1024) /* 32 Mbytes */ +static void +do_testsdram(int argc, + char *argv[]) +{ + cyg_uint32 *mem_addr = (cyg_uint32 *)SDRAM_BASE; + unsigned len; + bool len_set; + + register int i; + struct option_info opts[1]; + + init_opts(&opts[0], 'l', true, OPTION_ARG_TYPE_NUM, + (void**)&len, &len_set, "length"); + + if (!scan_opts(argc, argv, + 1, + opts, 1, + 0, 0, 0)) { + return; + } + if (!len_set) { + len = SDRAM_LEN / 4; + } + + diag_printf("Length = 0x%08X\n", len); + + diag_printf("Writing data-equals-address pattern to SDRAM\n"); + for (i = 0; i < len; i++) { + mem_addr[i] = ~(cyg_uint32)(mem_addr + i); + } + diag_printf("Reading back pattern\n"); + for (i = 0; i < len; i++) { + if (mem_addr[i] != ~(cyg_uint32)(mem_addr + i)) { + diag_printf("Error: mismatch at address %p, read back 0x%08x\n", + mem_addr + i, + mem_addr[i]); + break; + } + } + diag_printf("Done\n"); +} + +static void +do_delay(int argc, + char *argv[]) +{ + struct option_info opts[1]; + int count = 0x00000000; + bool count_set; + int value; + register int i; + + init_opts(&opts[0], 'c', true, OPTION_ARG_TYPE_NUM, + (void**)&count, &count_set, "Number of times to delay"); + + if (!scan_opts(argc, argv, + 1, + opts, sizeof(opts) / sizeof(opts[0]), + (void*)&value, OPTION_ARG_TYPE_NUM, "amount of time to delay (usec)")) { + return; + } + + if (!count_set) { + count = 1; + } + for (i = 0; i < count; i++) { + diag_printf("Delaying %d useconds...", value); + HAL_DELAY_US(value); + diag_printf("Done\n"); + } +} + +#endif