Mercurial > flash_v2
changeset 461:aae52574f8c5
Add support for PowerPC/8260 based platforms. Contributed by Patrick Doyle <wpd@delcomsys.com>
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,9 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * ecos.db: Add packages for MPC8260 based systems - VADS + and TS6 (Delphi Communications). + 2002-12-10 Gary Thomas <gthomas@ecoscentric.com> * ecos.db: Enable serial devices for A&M 'adder' platform.
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,5 @@ +* Add support for PowerPC 8260 based systems - one from Motorola (VADS) + and another from Delphi Communications. Contributed by Delphi. * Add support for Analogue & Micro Adder (PowerPC 850) boards * Update MN10300 ASB2303 HAL to support RedBoot * New package for application level profiling (histogram only)
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/ChangeLog @@ -0,0 +1,49 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/types.h: + * src/if_fec.c: + * src/fec.h: + * src/EnetPHY.h: + * src/EnetPHY.c: + * cdl/quicc2_eth_drivers.cdl: New package; ethernet drivers for + PowerPC/QUICC2 based systems (like MPC8260). + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + + +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/cdl/quicc2_eth_drivers.cdl @@ -0,0 +1,115 @@ +# ==================================================================== +# +# fec_eth_drivers.cdl +# +# Ethernet drivers - platform dependent support for PowerPC MPC8260 +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): mtek +# Original data: gthomas +# Contributors: +# Date: 2002-02-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_POWERPC_QUICC2 { + display "MPC8260 FEC ethernet driver" + + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_POWERPC + active_if CYGPKG_HAL_POWERPC_MPC8260 + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + include_dir . + include_files ; # none _exported_ whatsoever + + description "Fast ethernet driver for PowerPC MPC8260 boards." + compile -library=libextras.a if_fec.c EnetPHY.c + + cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE { + display "Buffer size" + flavor data + default_value 1540 + description " + This option specifies the size of the internal buffers used + for the PowerPC FEC/ethernet device." + } + + cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM { + display "Number of output buffers" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC FEC/ethernet device." + } + + cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM { + display "Number of input buffers" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC FEC/ethernet device." + } + + cdl_component CYGPKG_DEVS_ETH_POWERPC_QUICC2_OPTIONS { + display "MPC8260 FEC ethernet driver build options" + flavor none + no_define + + cdl_option CYGPKG_DEVS_ETH_POWERPC_QUICC2_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-D_KERNEL -D__ECOS" } + description " + This option modifies the set of compiler flags for + building the MPC8260 FEC ethernet driver package. + These flags are used in addition to the set of global + flags." + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.c @@ -0,0 +1,362 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +/*------------------------------------------------------------------- +* +* FILE: enetPHY.c +* +* DESCRIPTION: GPIO Management Pins driver for the LXT970a +* +* +* Modified for the mpc8260 VADS board +*--------------------------------------------------------------------*/ +#include "types.h" +#include "EnetPHY.h" + +/* Internal functions */ +void MdioSend(UINT32, UINT16); +UINT16 MdioReceive(UINT16); +UINT16 MdioFrame(MDIORW, UINT16, UINT16, UINT32); + +VUINT32 * pPortDir; +VUINT32 * pPortData; + +/*------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: +* +* EXTERNAL EFFECT: Turns on the LXT970 transciever +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*-------------------------------------------------------------------*/ +void +EnableResetPHY(volatile t_BCSR *pBCSR) +{ + // active low FETHIEN on BSCR1, assert reset low + pBCSR->bcsr1 &= ~(FETHIEN_ | FETHRST_); + // de-assert reset + pBCSR->bcsr1 |= FETHRST_; + +} + + +/*------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: Writes parameters to the control registers of LXT970 +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*-------------------------------------------------------------------*/ +UINT16 +InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link) +{ + + VUINT16 FrameValue; + + /* 8101 Ethernet Management Pin Assignments */ + pPortDir = pdir; + pPortData = pdat; + + (*pPortDir) |= MDC_PIN_MASK; /* MD_Clock will always be output only */ + + /* Test MDC & MDIO Pin Connection to PHY */ + MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame + MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame + FrameValue = MdioFrame(READ, 0, MIRROR_REG, 0); //read test frame + + if (FrameValue != MD_TEST_FRAME) + return LINKERROR; //test data integrity + + /* General Configuration */ + MdioFrame(WRITE, 0, CONFIG_REG, 0x0000); + + if(link == HUNDRED_HD) + MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0081); //100 Mbps Half, 802.3 + else + MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0021); //10 Mbps Half, 802.3 + + // 100 Mbps full duplex not supported + // MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0101); //100 Mbps Full, 802.3 + + MdioFrame(WRITE, 0, CONTROL_REG, 0x1300); + + return 0; +} + +/*------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*-------------------------------------------------------------------*/ +UINT16 +EthernetPHYInterruptHandler() +{ + // Reading registers 1 and 18 in sequence + // clears the transceiver interrupt + + MdioFrame(READ, 0, STATUS_REG, 0); + MdioFrame(READ, 0, INT_STAT_REG, 0); + + return LinkTestPHY(); +} /* end EthernetPHYInterruptHandler */ + +/*------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*-------------------------------------------------------------------*/ +UINT16 +LinkTestPHY() +{ + UINT32 j, cnt; + UINT16 FrameValue; + + //for (j = 0; j < 10; j++) { + for (j = 0; j < 5; j++) { + + for (cnt = 0; cnt < 1000000; cnt ++) { + + asm("nop"); + asm("nop"); + asm("nop"); + } + + FrameValue = MdioFrame(READ,0,CHIP_STAT_REG,0); + + if ( (FrameValue & 0x0200) != 0 ) + break; + } + + FrameValue &= 0x3800; + + switch (FrameValue) { + + case 0x3800: return HUNDRED_FD; + case 0x2800: return HUNDRED_HD; + case 0x3000: return TEN_FD; + case 0x2000: return TEN_HD; + default: return NOTLINKED; + } + +} + +/*------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*-------------------------------------------------------------------*/ +void EnablePHYinterrupt(UINT8 enable) +{ + MdioFrame(WRITE, 0, INT_EN_REG, enable?0x2:0x0); +} + +/*---------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: generic READ/WRITE function of LXT970 +* through the MDC/MDIO interface. +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*---------------------------------------------------------------------*/ +UINT16 +MdioFrame(MDIORW R_W, UINT16 PhyAddr, UINT16 RegAddr, UINT32 PutData) { + + UINT16 GetData; + + *pPortDir |= MDIO_PIN_MASK; //set to output mode + + MdioSend(0xFFFFFFFF,32); //PreAmble + MdioSend(0x1,2); //Start Frame Delimiter + if (R_W==READ) + MdioSend(0x2,2); //Read OpCode + else + MdioSend(0x1,2); //Write OpCode + + MdioSend(PhyAddr,5); //Send PHY transciever Address + MdioSend(RegAddr,5); //Send Register Address + + if (R_W==READ) { + *pPortDir &= ~MDIO_PIN_MASK; //set to input mode + GetData = MdioReceive(17); //Drive TurnAround and Data + MdioReceive(2); + } + else { + MdioSend(0x2,2); //Drive TurnAround + MdioSend(PutData, 16); //Send Data + GetData = 0; + *pPortDir &= ~MDIO_PIN_MASK; //set to input mode + } + + return GetData; + +} +/*---------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: Shift out bits of data +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: None +* +* ASSUMPTIONS: +* +*----------------------------------------------------------------------*/ +void +MdioSend(UINT32 txF, UINT16 size) { + + UINT32 dmask; + INT_NATIVE i, j; + + dmask = 1 << (size-1); // msbit out first + + for (i = 0; i < size; i++) { // for "size" bits + + if ( txF & dmask ) //output data bit high + *pPortData |= MDIO_PIN_MASK; + else //output data bit low > 400ns + *pPortData &= ~MDIO_PIN_MASK; + // >10ns + *pPortData |= MDC_PIN_MASK; // clock rise + + txF = (UINT32)(txF << 1); // >160ns + + for (j=0; j<MDC_HOLD_TIME; j++); + + *pPortData &= ~MDC_PIN_MASK; // clock fall + + for (j=0; j<MDC_HOLD_TIME; j++); + + } + + return; +} + + +/*--------------------------------------------------------------------- +* +* FUNCTION NAME: +* +* DESCRIPTION: Shifts in bits of data +* +* EXTERNAL EFFECT: +* +* PARAMETERS: +* +* RETURNS: +* +* ASSUMPTIONS: +* +*---------------------------------------------------------------------*/ +UINT16 +MdioReceive(UINT16 size) { + + UINT16 i,j, rxF = 0; + + for (i = 0; i < size; i++) { // 16 bits + + *pPortData |= MDC_PIN_MASK; // clock rise + + if ( *pPortData & MDIO_PIN_MASK ) // if read in a high bit + rxF = ( (UINT16)(rxF << 1) | 1 ); // shift in a one + else // if read in a low bit + rxF = ( (UINT16)(rxF << 1) & ~(UINT16)1 ); // shift in a zero + + + for (j=0; j<MDC_HOLD_TIME; j++); + + *pPortData &= ~MDC_PIN_MASK; // clock fall + + for (j=0; j<MDC_HOLD_TIME; j++); + + } + + return rxF; +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/src/EnetPHY.h @@ -0,0 +1,111 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +/*------------------------------------------------------------------ +* +* FILE: EnetPHY.c +* +* DESCRIPTION: LXT970a driver header file +* +* +* Modified for MPC8260 VADS board +*-------------------------------------------------------------------*/ + +#ifndef _EnetPHY_H +#define _EnetPHY_H + +#include "types.h" + +// Board control and status registers +typedef struct bcsr { + UINT32 bcsr0; + UINT32 bcsr1; + UINT32 bcsr2; + UINT32 bcsr3; +} t_BCSR; + +// Fast ethernet enable/reset pins on bcsr +#define FETHIEN_ 0x08000000 +#define FETHRST_ 0x04000000 + + +/**************************/ +/* The API for PHY Device */ +/**************************/ + +void EnableResetPHY(volatile t_BCSR *pBCSR); +UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link); +UINT16 EthernetPHYInterruptHandler(void); +void EnablePHYinterrupt(UINT8 enable); +UINT16 LinkTestPHY(void); + + +typedef enum MDIORW {READ, WRITE} MDIORW; + + +#define LINKERROR 0xFFFF +#define NOTLINKED 0x0000 +#define TEN_HD 0x0020 +#define TEN_FD 0x0040 +#define HUNDRED_HD 0x0080 +#define HUNDRED_FD 0x0100 + +#define MD_TEST_FRAME 0xDEAD + +//8260 VADS Pin Connections +#define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS +#define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS + +//#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS +//#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS + +//IEEE 802.3 PHY Register Definitions +#define CONTROL_REG 0 +#define STATUS_REG 1 +#define PHY_ID_REG_A 2 +#define PHY_ID_REG_B 3 +#define AUTONEG_AD_REG 4 +#define AUTONEG_LINKPARTNER_REG 5 +#define AUTONEG_EXP_REG 6 + +//LXT970a Specific Register Definitions +#define MIRROR_REG 16 +#define INT_EN_REG 17 +#define INT_STAT_REG 18 +#define CONFIG_REG 19 +#define CHIP_STAT_REG 20 + +//Clock Timing Control +#define MDC_HOLD_TIME 50 + +#endif
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/src/fec.h @@ -0,0 +1,173 @@ +//========================================================================== +// +// fec.h +// +// PowerPC MPC8260 fast ethernet (FEC) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: pfine +// Date: 2002-02-20 +// Purpose: +// Description: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// The port connected to the ethernet +#define QUICC2_VADS_IMM_BASE 0x04700000 +#define FCC2 1 + +/* ------------------------ */ +/* FCC REGISTER CONSTANTS */ +/* ------------------------ */ + +// GFMR masks (RESET: 0x00000000) +#define FEC_GFMR_EN_Rx 0x00000020 // Receive enable +#define FEC_GFMR_EN_Tx 0x00000010 // Transmit enable +#define FEC_GFMR_INIT 0x0000000C // mode=ethernet +#define FEC_GFMR_OFFSET 0x11320 + +//PSMR masks (RESET: 0x00000000) +#define FEC_PSMR_INIT 0x00000080 // 32-bit CRC +#define FEC_PSMR_OFFSET 0x11324 + +//TODR masks (RESET: 0x0000) +#define FEC_TOD_INIT 0x0000 +#define FEC_TOD_SET 0x8000 +#define FEC_TOD_OFFSET 0x11328 + +//DSR masks (RESET: 0x7E7E) +#define FEC_DSR_INIT 0xD555 +#define FEC_DSR_OFFSET 0x1132C + +//FCCE & FCCM (RESET: 0x0000) +#define FEC_EV_GRA 0x00800000 // Graceful stop +#define FEC_EV_RXC 0x00400000 // A control frame has been received +#define FEC_EV_TXC 0x00200000 // Out of sequence frame sent +#define FEC_EV_TXE 0x00100000 // Error in transmission channel +#define FEC_EV_RXF 0x00080000 // A complete frame received +#define FEC_EV_BSY 0x00040000 // A received frame discarded due to lack + // of buffers +#define FEC_EV_TXB 0x00020000 // A buffer sent to ethernet +#define FEC_EV_RXB 0x00010000 // A buffer that is a non-complete frame + // is received +#define FEC_FCCE_OFFSET 0x11330 +#define FEC_FCCM_OFFSET 0x11334 + +/* ------------------------------ */ +/* FCC PARAMETER RAM CONSTANTS */ +/* ------------------------------ */ + +#define FEC_PRAM_RIPTR 0x3000 // 32 byte buffer in dual port RAM +#define FEC_PRAM_TIPTR 0xB000 // 32 byte buffer in dual port RAM +#define FEC_FCR_INIT 0x00000000 // Clear the reserved bits +#define FEC_FCR_MOT_BO 0x10000000 // Motorola byte ordering +#define FEC_PRAM_C_MASK 0xDEBB20E3 // Constant MASK for CRC +#define FEC_PRAM_C_PRES 0xFFFFFFFF // CRC Preset +#define FEC_PRAM_RETLIM 15 // Retry limit +#define FEC_PRAM_PER_LO 5 // Persistance +#define FEC_PRAM_PER_HI 0 +#define FEC_PRAM_MRBLR 1536 +#define FEC_MAX_FLR 1518 // Max frame length +#define FEC_MIN_FLR 64 // Min frame length +#define FEC_PRAM_PAD_CH 0x8888 +#define FEC_PRAM_MAXD 1520 +#define FEC_PRAM_OFFSET 0x8500 // Offset of t_Fcc_Pram in 82xx + +/* ------------------------------ */ +/* BUFFER DESCRIPTOR CONSTANTS */ +/* ------------------------------ */ +#define FEC_PRAM_RxBD_Base (FEC_PRAM_RIPTR + 0x400) +#define FEC_BD_Rx_Empty 0x8000 // Buffer is empty, FEC can fill +#define FEC_BD_Rx_Wrap 0x2000 // Wrap: Last buffer in ring +#define FEC_BD_Rx_Int 0x1000 // Interrupt +#define FEC_BD_Rx_Last 0x0800 // Last buffer in frame +#define FEC_BD_Rx_Miss 0x0100 // Miss: promiscious mode +#define FEC_BD_Rx_BC 0x0080 // Broadcast address +#define FEC_BD_Rx_MC 0x0040 // Multicast address +#define FEC_BD_Rx_LG 0x0020 // Frame length violation +#define FEC_BD_Rx_NO 0x0010 // Non-octet aligned frame +#define FEC_BD_Rx_SH 0x0008 // Short frame +#define FEC_BD_Rx_CR 0x0004 // CRC error +#define FEC_BD_Rx_OV 0x0002 // Overrun +#define FEC_BD_Rx_TR 0x0001 // Frame truncated. late collision + +#define FEC_PRAM_TxBD_Base (FEC_PRAM_TIPTR + 0x400) +#define FEC_BD_Tx_Ready 0x8000 // Frame ready +#define FEC_BD_Tx_Pad 0x4000 // Pad short frames +#define FEC_BD_Tx_Wrap 0x2000 // Wrap: Last buffer in ring +#define FEC_BD_Tx_Int 0x1000 // Interrupt +#define FEC_BD_Tx_Last 0x0800 // Last buffer in frame +#define FEC_BD_Tx_TC 0x0400 // Send CRC after data +#define FEC_BD_Tx_DEF 0x0200 // Defer indication +#define FEC_BD_Tx_HB 0x0100 // Heartbeat +#define FEC_BD_Tx_LC 0x0080 // Late collision +#define FEC_BD_Tx_RL 0x0040 // Retransmission limit +#define FEC_BD_Tx_RC 0x003C // Retry count +#define FEC_BD_Tx_UN 0x0002 // Underrun +#define FEC_BD_Tx_CSL 0x0001 // Carrier sense lost + + +// Buffer descriptor +struct fec_bd { + volatile unsigned short ctrl; + volatile unsigned short length; + volatile unsigned char *buffer; +}; + + +struct fec_eth_info { + volatile struct fcc_regs *fcc_reg; // See "mpc8260.h" + struct fec_bd *txbd, *rxbd; // Next Tx,Rx descriptor to use + struct fec_bd *tbase, *rbase; // First Tx,Rx descriptor + struct fec_bd *tnext, *rnext; // Next descriptor to check for interrupt + int txsize, rxsize; // Length of individual buffers + unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM]; +}; + +// CPM_CPCR masks +#define CPCR_FLG 0x00010000 +#define CPCR_FCC2_CH 0x16200000 +#define CPCR_GRSTOP_TX 0x00000005 +#define CPCR_INIT_TX_RX_PARAMS 0x00000000 +#define CPCR_MCN_FEC 0x00000300 +#define CPCR_READY_TO_RX_CMD 0 /* Ready to receive a command */
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/src/if_fec.c @@ -0,0 +1,721 @@ +//========================================================================== +// +// dev/if_fec.c +// +// Fast ethernet device driver for PowerPC MPC8260 boards +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: pfine +// Date: 2002-02-20 +// Purpose: +// Description: hardware driver for MPC8260 FEC +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/devs_eth_powerpc_quicc2.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/diag.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/var_intr.h> +#include <cyg/hal/drv_api.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/mpc8260.h> + +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> + +#ifdef CYGPKG_NET +#include <pkgconf/net.h> +#endif + +#include "fec.h" +#include "EnetPHY.h" + +#define ALIGN_TO_CACHE_LINES(x) ( (long)((x) + 31) & 0xffffffe0 ) + +static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM * + (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)]; +static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM * + (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)]; + +// Buffer descriptors are in dual ported RAM, which is marked non-cached +#define FEC_BDs_NONCACHED +static struct fec_bd *const fec_eth_rxring = (struct fec_bd *) + (QUICC2_VADS_IMM_BASE + FEC_PRAM_RxBD_Base); +static struct fec_bd *const fec_eth_txring = (struct fec_bd *) + (QUICC2_VADS_IMM_BASE + FEC_PRAM_TxBD_Base); + +static struct fec_eth_info fec_eth0_info; + +static unsigned short _default_enaddr[] = {0x1234, 0x5678, 0x90a1}; +static unsigned char enaddr[6]; + +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#include <redboot.h> +#include <flash_config.h> +RedBoot_config_option("Network hardware address [MAC]", + fec_esa, + ALWAYS_ENABLED, true, + CONFIG_ESA, 0 + ); +RedBoot_config_option("Attempt to find 100 Mbps Ethernet", + fec_100, + ALWAYS_ENABLED, true, + CONFIG_BOOL, 0 + ); +#endif +#endif + +#define os_printf diag_printf + +// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h +#ifndef CONFIG_ESA +#define CONFIG_ESA 6 // ethernet address length ... +#endif + +#ifndef CONFIG_BOOL +#define CONFIG_BOOL 1 +#endif + +ETH_DRV_SC(fec_eth0_sc, + &fec_eth0_info, // Driver specific data + "eth0", // Name for this interface + fec_eth_start, + fec_eth_stop, + fec_eth_control, + fec_eth_can_send, + fec_eth_send, + fec_eth_recv, + fec_eth_deliver, + fec_eth_int, + fec_eth_int_vector); + +NETDEVTAB_ENTRY(fec_netdev, + "fec_eth", + fec_eth_init, + &fec_eth0_sc); + +#ifdef CYGPKG_NET +static cyg_interrupt fec_eth_interrupt; +static cyg_handle_t fec_eth_interrupt_handle; +#endif +static void fec_eth_int(struct eth_drv_sc *data); + +#define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_FCC2 + +// This ISR is called when the ethernet interrupt occurs +#ifdef CYGPKG_NET +static int +fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) +{ + cyg_drv_interrupt_mask(FEC_ETH_INT); + return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR +} +#endif + +// Deliver function (ex-DSR) handles the ethernet [logical] processing +static void +fec_eth_deliver(struct eth_drv_sc * sc) +{ + fec_eth_int(sc); +#ifdef CYGPKG_NET + // Clearing the event register acknowledges FCC2 interrupt ... + // cyg_drv_interrupt_acknowledge(FEC_ETH_INT); + cyg_drv_interrupt_unmask(FEC_ETH_INT); +#endif + +} + + +// Initialize the interface - performed at system startup +// This function must set up the interface, including arranging to +// handle interrupts, etc, so that it may be "started" cheaply later. +static bool +fec_eth_init(struct cyg_netdevtab_entry *tab) +{ + struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; + volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET); + volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e); +#ifdef CYGPKG_HAL_POWERPC_VADS + volatile t_BCSR *CSR = (t_BCSR *) 0x04500000; +#endif + + int cache_state; + int i; + bool esa_ok; + bool fec_100; + unsigned char *c_ptr; + UINT16 link_speed; + + // Ensure consistent state between cache and what the FEC sees + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_DISABLE(); + HAL_DCACHE_INVALIDATE_ALL(); + } + + // Link the memory to the driver control memory + qi->fcc_reg = & (IMM->fcc_regs[FCC2]); + + // just in case : disable Transmit and Receive + qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); + + // Via BCSR, (re)start LXT970 +#ifdef CYGPKG_HAL_POWERPC_VADS + EnableResetPHY(CSR); +#endif + + // Try to read the ethernet address of the transciever ... +#ifdef CYGPKG_REDBOOT + esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL); +#else + esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, + "fec_100", &fec_100, CONFIG_BOOL); +#endif + + link_speed = NOTLINKED; + if(esa_ok && fec_100){ + // Via MII Management pins, tell LXT970 to initialize + os_printf("Attempting to acquire 100 Mbps half_duplex link ..."); + InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir), + (VUINT32 *) &(IMM->io_regs[PORT_C].pdat), + HUNDRED_HD); + + link_speed = LinkTestPHY(); + os_printf("\n"); + if(link_speed == NOTLINKED){ + os_printf("Failed to get 100 Mbps half_duplex link.\n"); + } + } + if(link_speed == NOTLINKED){ + os_printf("Attempting to acquire 10 Mbps half_duplex link ..."); + InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir), + (VUINT32 *) &(IMM->io_regs[PORT_C].pdat), + TEN_HD); + link_speed = LinkTestPHY(); + os_printf("\n"); + if(link_speed == NOTLINKED){ + link_speed = LinkTestPHY(); + os_printf("Failed to get 10 Mbps half_duplex link.\n"); + } + + } + switch ( link_speed ) { + + case HUNDRED_FD: + os_printf("100 MB full-duplex ethernet link \n"); + break; + case HUNDRED_HD: + os_printf("100 MB half-duplex ethernet link \n"); + break; + case TEN_FD: + os_printf("10 MB full-duplex ethernet link \n"); + break; + case TEN_HD: + os_printf("10 MB half-duplex ethernet link \n"); + break; + default: + os_printf("NO ethernet link \n"); + } + + // Connect PORTC pins: (C19) to clk13, (C18) to clk 14 + IMM->io_regs[PORT_C].ppar |= 0x00003000; + IMM->io_regs[PORT_C].podr &= ~(0x00003000); + IMM->io_regs[PORT_C].psor &= ~(0x00003000); + IMM->io_regs[PORT_C].pdir &= ~(0x00003000); + + // Connect clk13 to RxClk and clk14 to TxClk on FCC2 + IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks + IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14) + IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear + + // Initialize parallel port registers to connect FCC2 to MII + IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31 + IMM->io_regs[PORT_B].psor &= 0xffffc000; + IMM->io_regs[PORT_B].pdir &= 0xffffc000; + + IMM->io_regs[PORT_B].psor |= 0x00000004; + IMM->io_regs[PORT_B].pdir |= 0x000003c5; + IMM->io_regs[PORT_B].ppar |= 0x00003fff; + + // Initialize Receive Buffer Descriptors + qi->rbase = fec_eth_rxring; + qi->rxbd = fec_eth_rxring; + qi->rnext = fec_eth_rxring; + c_ptr = fec_eth_rxbufs; + + for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) { + + fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int); + fec_eth_rxring[i].length = 0; // reset + c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr); + fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr; + c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE; + } + + fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap; + + // Initialize Transmit Buffer Descriptors + qi->tbase = fec_eth_txring; + qi->txbd = fec_eth_txring; + qi->tnext = fec_eth_txring; + c_ptr = fec_eth_txbufs; + + for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) { + + fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int); + fec_eth_txring[i].length = 0; // reset : Write before send + c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr); + fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr; + c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE; + } + + fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap; + + // Common FCC Parameter RAM initialization + fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11) + fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11) + fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ... + fcc->rstate &= FEC_FCR_INIT; + fcc->rstate |= FEC_FCR_MOT_BO; + fcc->rbase = (long) fec_eth_rxring; + fcc->tstate &= FEC_FCR_INIT; + fcc->tstate |= FEC_FCR_MOT_BO; + fcc->tbase = (long) fec_eth_txring; + + // Ethernet Specific FCC Parameter RAM Initialization + E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9) + E_fcc->c_pres = FEC_PRAM_C_PRES; + E_fcc->crcec = 0; + E_fcc->alec = 0; + E_fcc->disfc = 0; + E_fcc->ret_lim = FEC_PRAM_RETLIM; + E_fcc->p_per = FEC_PRAM_PER_LO; + E_fcc->gaddr_h = 0; + E_fcc->gaddr_l = 0; + E_fcc->tfcstat = 0; + E_fcc->mflr = FEC_MAX_FLR; + + // Try to read the ethernet address of the transciever ... +#ifdef CYGPKG_REDBOOT + esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA); +#else + esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, + "fec_esa", enaddr, CONFIG_ESA); +#endif + if (!esa_ok) { + // If can't use the default ... + os_printf("FEC_ETH - Warning! ESA unknown\n"); + memcpy(enaddr, _default_enaddr, sizeof(enaddr)); + } + + E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2]; + E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1]; + E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0]; + + E_fcc->iaddr_h = 0; + E_fcc->iaddr_l = 0; + E_fcc->minflr = FEC_MIN_FLR; + E_fcc->taddr_h = 0; + E_fcc->taddr_m = 0; + E_fcc->taddr_l = 0; + E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ... + E_fcc->cf_type = 0; + E_fcc->maxd1 = FEC_PRAM_MAXD; + E_fcc->maxd2 = FEC_PRAM_MAXD; + + // FCC register initialization + IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT; + IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT; + IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT; + +#ifdef CYGPKG_NET + // clear the events of FCC2 + IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000; + IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF; + + // Set up to handle interrupts + cyg_drv_interrupt_create(FEC_ETH_INT, + 0, // Highest //CYGARC_SIU_PRIORITY_HIGH, + (cyg_addrword_t)sc, // Data passed to ISR + (cyg_ISR_t *)fec_eth_isr, + (cyg_DSR_t *)eth_drv_dsr, + &fec_eth_interrupt_handle, + &fec_eth_interrupt); + cyg_drv_interrupt_attach(fec_eth_interrupt_handle); + cyg_drv_interrupt_acknowledge(FEC_ETH_INT); + cyg_drv_interrupt_unmask(FEC_ETH_INT); +#else + + // Mask the interrupts + IMM->fcc_regs[FCC2].fcc_fccm = 0; +#endif + + // Issue Init RX & TX Parameters Command for FCC2 + while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); + + IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS | + CPCR_FCC2_CH | + CPCR_MCN_FEC | + CPCR_FLG; /* ISSUE COMMAND */ + + while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); + + if (cache_state) + HAL_DCACHE_ENABLE(); + + // Initialize upper level driver for ecos + (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr); + + return true; +} + +// +// This function is called to "start up" the interface. It may be called +// multiple times, even when the hardware is already running. It will be +// called whenever something "hardware oriented" changes and should leave +// the hardware ready to send/receive packets. +// +static void +fec_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + + // Enable the device : + // Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive + qi->fcc_reg->fcc_gfmr |= (FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); + +} + +// +// This function is called to shut down the interface. +// +static void +fec_eth_stop(struct eth_drv_sc *sc) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + + // Disable the device : + // Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive + qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); +} + + +// +// This function is called for low level "control" operations +// +static int +fec_eth_control(struct eth_drv_sc *sc, unsigned long key, + void *data, int length) +{ + switch (key) { + case ETH_DRV_SET_MAC_ADDRESS: + return 0; + break; + default: + return 1; + break; + } +} + + +// +// This function is called to see if another packet can be sent. +// It should return the number of packets which can be handled. +// Zero should be returned if the interface is busy and can not send any more. +// +static int +fec_eth_can_send(struct eth_drv_sc *sc) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + volatile struct fec_bd *txbd = qi->txbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_INVALIDATE(fec_eth_txring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); + } +#endif + + return ((txbd->ctrl & FEC_BD_Tx_Ready) == 0); +} + +// +// This routine is called to send data to the hardware. +static void +fec_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, + int total_len, unsigned long key) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + struct fec_bd *txbd, *txfirst; + volatile char *bp; + int i, txindex, cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_INVALIDATE(fec_eth_txring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); + } +#endif + + // Find a free buffer + txbd = txfirst = qi->txbd; + while (txbd->ctrl & FEC_BD_Tx_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & FEC_BD_Tx_Wrap) { + txbd = qi->tbase; + } else { + txbd++; + } + if (txbd == txfirst) { +#ifdef CYGPKG_NET + panic ("No free xmit buffers"); +#else + os_printf("FEC Ethernet: No free xmit buffers\n"); +#endif + } + } + + // Remember the next buffer to try + if (txbd->ctrl & FEC_BD_Tx_Wrap) { + qi->txbd = qi->tbase; + } else { + qi->txbd = txbd+1; + } + + txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd); + qi->txkey[txindex] = key; + + // Set up buffer + txbd->length = total_len; + bp = txbd->buffer; + for (i = 0; i < sg_len; i++) { + memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len); + bp += sg_list[i].len; + } + + // Make sure no stale data buffer ... + if (cache_state) { + HAL_DCACHE_FLUSH(txbd->buffer, txbd->length); + } + // Send it on it's way + txbd->ctrl |= FEC_BD_Tx_Ready | FEC_BD_Tx_Last | FEC_BD_Tx_TC; +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_FLUSH(fec_eth_txring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); + } +#endif + +} + +// +// This function is called when a packet has been received. It's job is +// to prepare to unload the packet from the hardware. Once the length of +// the packet is known, the upper layer of the driver can be told. When +// the upper layer is ready to unload the packet, the internal function +// 'fec_eth_recv' will be called to actually fetch it from the hardware. +// +static void +fec_eth_RxEvent(struct eth_drv_sc *sc) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + struct fec_bd *rxbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_INVALIDATE(fec_eth_rxring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM); + } +#endif + + rxbd = qi->rnext; + while ((rxbd->ctrl & FEC_BD_Rx_Empty) == 0) { + qi->rxbd = rxbd; // Save for callback + + // This is the right way of doing it, but dcbi has a bug ... + // if (cache_state) { + // HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length); + // } + (sc->funs->eth_drv->recv)(sc, rxbd->length); + if (cache_state) { + HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length); + } + + rxbd->ctrl |= FEC_BD_Rx_Empty; + if (rxbd->ctrl & FEC_BD_Rx_Wrap) { + rxbd = qi->rbase; + } else { + rxbd++; + } + } + // Remember where we left off + qi->rnext = (struct fec_bd *)rxbd; + + // Make sure no stale data +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_FLUSH(fec_eth_rxring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM); + } +#endif + +} + +// +// This function is called as a result of the "eth_drv_recv()" call above. +// It's job is to actually fetch data for a packet from the hardware once +// memory buffers have been allocated for the packet. Note that the buffers +// may come in pieces, using a scatter-gather list. This allows for more +// efficient processing in the upper layers of the stack. +// +static void +fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + unsigned char *bp; + int i; + + bp = (unsigned char *)qi->rxbd->buffer; + + for (i = 0; i < sg_len; i++) { + if (sg_list[i].buf != 0) { + memcpy((void *)sg_list[i].buf, bp, sg_list[i].len); + bp += sg_list[i].len; + } + } + +} + +static void +fec_eth_TxEvent(struct eth_drv_sc *sc, int stat) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + struct fec_bd *txbd; + int txindex, cache_state; + + // Make sure no stale data + HAL_DCACHE_IS_ENABLED(cache_state); +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_INVALIDATE(fec_eth_txring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); + } +#endif + + txbd = qi->tnext; + // Note: TC field is used to indicate the buffer has/had data in it + while ( (txbd->ctrl & (FEC_BD_Tx_TC | FEC_BD_Tx_Ready)) == FEC_BD_Tx_TC ) { + txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd); + (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0); + txbd->ctrl &= ~FEC_BD_Tx_TC; + if (txbd->ctrl & FEC_BD_Tx_Wrap) { + txbd = qi->tbase; + } else { + txbd++; + } + } + // Remember where we left off + qi->tnext = (struct fec_bd *)txbd; + + // Make sure no stale data +#ifndef FEC_BDs_NONCACHED + if (cache_state) { + HAL_DCACHE_FLUSH(fec_eth_txring, + 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); + } +#endif + +} + +// +// Interrupt processing +// +static void +fec_eth_int(struct eth_drv_sc *sc) +{ + struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; + unsigned long iEvent; + + while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){ + + // Writing 1's clear fcce, Writing 0's have no effect + qi->fcc_reg->fcc_fcce = iEvent; + + // Tx Done or Tx Error + if ( iEvent & (FEC_EV_TXB | FEC_EV_TXE) ) { + fec_eth_TxEvent(sc, iEvent); + } + + // Complete or non-complete frame receive + if (iEvent & (FEC_EV_RXF | FEC_EV_RXB) ) { + fec_eth_RxEvent(sc); + } + + } + + +} + +// +// Interrupt vector +// +static int +fec_eth_int_vector(struct eth_drv_sc *sc) +{ + return (FEC_ETH_INT); +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/powerpc/quicc2/current/src/types.h @@ -0,0 +1,100 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +/********************************************************************** + * Copyright (c) 1999 Delphi Communication Systems + * Maynard, MA. ALL RIGHTS RESERVED + ***********************************************************************/ +/********************************************************************** + * File: + * $RCSfile: types.h,v $ + * $Revision: 1.1.1.2 $ + * $Date: 2002/03/14 17:54:24 $ + * + * Purpose: + * This file defines basic types used in the ITU-T G.729A Speech + * codec. These are defined here so that we may control + * how many bits of precision a type has on a particular + * platform. + * + * Operation: + * We define the following in this file: + * + * typedef ... INT16 + * This type definition defines the data type used for + * variables that must hold exactly 16 bits (signed). + * + * typedef ... INT32 + * This type definition defines the data type used for + * variables that must hold exactly 32 bits (signed). + * + * Notes/Issues: + * This file is correct for the following platforms (so far): + * + * GNUWIN32 compiled with GCC + * + * $Log: types.h,v $ + * Revision 1.1.1.2 2002/03/14 17:54:24 pfine + * Fixed CR/LF Problem + * + * Revision 1.1.1.1 2002/03/13 18:20:24 pfine + * DCS Ecos with Device Drivers + * + * + ***********************************************************************/ +#ifndef TYPES_H +#define TYPES_H + +typedef char INT8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef long INT32; +typedef unsigned long UINT32; + +typedef volatile char VINT8; +typedef volatile unsigned char VUINT8; +typedef volatile short VINT16; +typedef volatile unsigned short VUINT16; +typedef volatile long VINT32; +typedef volatile unsigned long VUINT32; + +typedef char OCTET; +typedef int INT_NATIVE; +typedef unsigned int UINT_NATIVE; + +#endif /* TYPES_H */ + + + +
--- a/packages/devs/flash/intel/28fxxx/current/ChangeLog +++ b/packages/devs/flash/intel/28fxxx/current/ChangeLog @@ -1,3 +1,10 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * include/flash_28fxxx_parts.inl: + * include/flash_28fxxx.inl: + * cdl/flash_intel_28fxxx.cdl: Add SHARP 28F016 parts. + 2002-08-05 Gary Thomas <gary@chez-thomas.org> 2002-08-05 Jani Monoses <jani@iv.ro>
--- a/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl +++ b/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl @@ -115,4 +115,30 @@ cdl_package CYGPKG_DEVS_FLASH_INTEL_28FX able to recognize and handle the 28F320S3 part in the family." } + + cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 { + display "Sharp LH28F016SCT-Z4 flash memory support" + default_value 0 + implements CYGHWR_IO_FLASH_BLOCK_LOCKING + implements CYGINT_DEVS_FLASH_INTEL_VARIANTS + description " + When this option is enabled, the Intel flash driver will be + able to recognize and handle the Sharp LH28F016SCT-Z4 + part. Although this part is not an Intel part, the driver + is implemented using the same command status definitions." + + } + + cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 { + display "Sharp LH28F016SCT-95 flash memory support" + default_value 0 + implements CYGHWR_IO_FLASH_BLOCK_LOCKING + implements CYGINT_DEVS_FLASH_INTEL_VARIANTS + description " + When this option is enabled, the Intel flash driver will be + able to recognize and handle the Sharp LH28F016SCT-95 + part. Although this part is not an Intel part, the driver + is implemented using the same command status definitions." + + } }
--- a/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl +++ b/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -533,6 +534,108 @@ flash_unlock_block(void* block, int bloc int timeout = 5000000; volatile flash_data_t* b_p = (flash_data_t*) block; volatile flash_data_t *b_v; + +#if (defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4) || defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95) ) + // The Sharp device follows all the same rules as the Intel 28x part, + // except that the unlocking mechanism unlocks all blocks at once. This + // is the way the Strata part seems to work. I will replace the + // flash_unlock_block function with one similar to the Strata function. + // As the Sharp part does not have the bootlock characteristics, I + // will ignore them. +// +// The difficulty with this operation is that the hardware does not support +// unlocking single blocks. However, the logical layer would like this to +// be the case, so this routine emulates it. The hardware can clear all of +// the locks in the device at once. This routine will use that approach and +// then reset the regions which are known to be locked. +// + +#define MAX_FLASH_BLOCKS (flash_dev_info->block_count * CYGNUM_FLASH_SERIES) + + unsigned char is_locked[MAX_FLASH_BLOCKS]; + int i; + + // Get base address and map addresses to virtual addresses +#ifdef DEBUG + d_print("\nNow inside low level driver\n"); +#endif + ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE; + block = FLASH_P2V(block); + + // Clear any error conditions + ROM[0] = FLASH_Clear_Status; + + // Get current block lock state. This needs to access each block on + // the device so currently locked blocks can be re-locked. + b_p = ROM; + for (i = 0; i < blocks; i++) { + b_v = FLASH_P2V( b_p ); + *b_v = FLASH_Read_ID; + if (b_v == block) { + is_locked[i] = 0; + } else { + if(b_v[2]){ /* it is possible that one of the interleaved devices + * is locked, but others are not. Coming out of this + * function, if one was locked, all will be locked. + */ + is_locked[i] = 1; + }else{ + is_locked[i] = 0; + } + } +#ifdef DEBUG +#endif + b_p += block_size / sizeof(*b_p); + } + ROM[0] = FLASH_Reset; +#ifdef DEBUG + for (i = 0; i < blocks; i++) { + d_print("\nblock %d %s", i, + is_locked[i] ? "LOCKED" : "UNLOCKED"); + } + d_print("\n"); +#endif + + // Clears all lock bits + ROM[0] = FLASH_Clear_Lock; + ROM[0] = FLASH_Clear_Lock_Confirm; // Confirmation + timeout = 5000000; + while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) { + if (--timeout == 0) break; + } + + // Restore the lock state + b_p = ROM; + for (i = 0; i < blocks; i++) { + b_v = FLASH_P2V( b_p ); + if (is_locked[i]) { + *b_v = FLASH_Set_Lock; + *b_v = FLASH_Set_Lock_Confirm; // Confirmation + timeout = 5000000; + while(((state = ROM[0]) & FLASH_Status_Ready) + != FLASH_Status_Ready) { + if (--timeout == 0){ + res = FLASH_ERR_DRV_TIMEOUT; + break; + } + } + if (FLASH_ErrorLock == (state & FLASH_ErrorLock)) + res = FLASH_ERR_LOCK; + + if (res != FLASH_ERR_OK) + break; + + } + b_p += block_size / sizeof(*b_p); + } + + // Restore ROM to "normal" mode + ROM[0] = FLASH_Reset; + + return res; + +#else // not CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 + cyg_bool bootblock; int len, len_ix = 1; @@ -656,6 +759,7 @@ flash_unlock_block(void* block, int bloc // Restore ROM to "normal" mode ROM[0] = FLASH_Reset; #endif +#endif // #CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 } #endif // CYGHWR_IO_FLASH_BLOCK_LOCKING
--- a/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl +++ b/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl @@ -56,6 +56,33 @@ //========================================================================== #if CYGNUM_FLASH_WIDTH == 8 +#ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 + { // LH28F016SCT_Z4 + device_id : FLASHWORD(0xA0), + block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE, + block_count: 32, + device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE, + base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1), + buffered_w : false, + locking : true, + bootblock : false, + banked : false + }, +#endif + +#ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 + { // LH28F016SCT_95 + device_id : FLASHWORD(0xAA), + block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE, + block_count: 32, + device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE, + base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1), + buffered_w : false, + locking : true, + bootblock : false, + banked : false + }, +#endif #else // 16 bit devices
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/ts6/current/ChangeLog @@ -0,0 +1,42 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/powerpc_ts6_flash.c: + * cdl/flash_ts6.cdl: New package - FLASH support on Delphi + Communications TS6 board. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/ts6/current/cdl/flash_ts6.cdl @@ -0,0 +1,72 @@ +# ==================================================================== +# +# flash_ts6.cdl +# +# FLASH memory - Hardware support on Delphi MPC8260 TS6 Board +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): pfine +# Original data: gthomas +# Contributors: +# Date: 2002-02-27 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_TS6 { + display "Delphi TS6 FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_POWERPC_TS6 + + implements CYGHWR_IO_FLASH_DEVICE + + compile powerpc_ts6_flash.c + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED { + display "Generic INTEL 28FXXX driver required" + } + + implements CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED + requires (CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 || CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4) +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/ts6/current/src/powerpc_ts6_flash.c @@ -0,0 +1,71 @@ +//========================================================================== +// +// powerpc_ts6_flash.c +// +// Flash programming for SHARP device on DELPHI TS6 board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Original: jskov +// Contributors: +// Date: 2002-02-27 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Device properties + +#define CYGNUM_FLASH_INTERLEAVE (4) +#define CYGNUM_FLASH_SERIES (1) +#define CYGNUM_FLASH_WIDTH (8) +#define CYGNUM_FLASH_BASE (0xff800000u) + +//-------------------------------------------------------------------------- +// Platform specific extras + +//-------------------------------------------------------------------------- +// Now include the driver code. +#include "cyg/io/flash_28fxxx.inl" + +// ------------------------------------------------------------------------ +// EOF powerpc_ts6_flash.c
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/vads/current/ChangeLog @@ -0,0 +1,42 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/powerpc_vads_flash.c: + * cdl/flash_vads.cdl: New package - FLASH support on Motorola + VADS (MPC8260) system. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/vads/current/cdl/flash_vads.cdl @@ -0,0 +1,73 @@ +# ==================================================================== +# +# flash_vads.cdl +# +# FLASH memory - Hardware support on Motorola MPC8260 Voyager Board +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): pfine +# Original data: gthomas +# Contributors: +# Date: 2002-01-11 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_VADS { + display "Motorola MPC8260 Voyager ADS FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_POWERPC_VADS + + implements CYGHWR_IO_FLASH_DEVICE +# implements CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM + + compile powerpc_vads_flash.c + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED { + display "Generic INTEL 28FXXX driver required" + } + + implements CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED + requires (CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 || CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95) +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/powerpc/vads/current/src/powerpc_vads_flash.c @@ -0,0 +1,77 @@ +//========================================================================== +// +// powerpc_vads_flash.c +// +// Flash programming for SHARP device on POWERPC MPC8260 Voyager +// ADS board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Original: jskov +// Contributors: +// Date: 2002-01-11 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +// Device properties + +#define CYGNUM_FLASH_INTERLEAVE (4) +#define CYGNUM_FLASH_SERIES (1) +#define CYGNUM_FLASH_WIDTH (8) +#define nPF_HACK +#ifdef PF_HACK +#define CYGNUM_FLASH_BASE (0xfe000000u) +#else +#define CYGNUM_FLASH_BASE (0xff800000u) +#endif + +//-------------------------------------------------------------------------- +// Platform specific extras + +//-------------------------------------------------------------------------- +// Now include the driver code. +#include "cyg/io/flash_28fxxx.inl" + +// ------------------------------------------------------------------------ +// EOF powerpc_vads_flash.c
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/powerpc/quicc2/current/ChangeLog @@ -0,0 +1,43 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/quicc2_scc_serial.h: + * src/quicc2_scc_serial.c: + * cdl/ser_quicc2_scc.cdl: New package - serial I/O suport on + PowerPC/QUICC2 based systems (like MPC8260). + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl @@ -0,0 +1,290 @@ +# ==================================================================== +# +# ser_quicc2_scc.cdl +# +# eCos serial PowerPC/QUICC2 SCC configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): mtek +# Original data: gthomas +# Contributors: +# Date: 2002-02-27 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + + +cdl_package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC { + display "PowerPC QUICC2/SCC serial device drivers" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + active_if CYGPKG_HAL_POWERPC_MPC8260 + + requires CYGPKG_ERROR + include_dir cyg/io + include_files ; # none _exported_ whatsoever + description " + This option enables the serial device drivers for the + PowerPC QUICC2/SCC." + doc redirect/ecos-device-drivers.html + + compile -library=libextras.a quicc2_scc_serial.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_quicc2_scc.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 { + display "PowerPC QUICC2/SCC serial port 1 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC2/SCC port 1." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME { + display "Device name for PowerPC QUICC2/SCC serial port 1" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the device name for the PowerPC + QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD { + display "Baud rate for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE { + display "Buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BRG { + display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 1 to 4 + default_value 1 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE { + display "Output buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE { + display "Input buffer size for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC2/SCC port 1." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM { + display "Number of input buffers for the PowerPC QUICC2/SCC serial port 1" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC2/SCC port 1." + } +} + +cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 { + display "PowerPC QUICC2/SCC serial port 2 driver" + flavor bool + default_value 1 + description " + This option includes the serial device driver for the PowerPC + QUICC2/SCC port 2." + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME { + display "Device name for PowerPC QUICC2/SCC serial port 2" + flavor data + default_value {"\"/dev/ser2\""} + description " + This option specifies the device name for the PowerPC + QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD { + display "Baud rate for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE { + display "Buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 0 to 8192 + default_value 256 + description " + This option specifies the size of the internal buffers used + for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BRG { + display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 1 to 4 + default_value 2 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE { + display "Output buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per + transmit request to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE { + display "Input buffer size for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 16 to 128 + default_value 16 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC2/SCC port 2." + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM { + display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2" + flavor data + legal_values 2 to 16 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC2/SCC port 2." + } +} + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are removed from + the set of global flags if present." + } + } +} + +# EOF ser_quicc_smc.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c @@ -0,0 +1,851 @@ +//========================================================================== +// +// io/serial/powerpc/quicc2_scc_serial.c +// +// PowerPC QUICC2 (SCC) Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: gthomas +// Date: 1999-06-20 +// Purpose: QUICC2 SCC Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/var_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/mpc8260.h> +#include CYGBLD_HAL_PLATFORM_H + +#include "quicc2_scc_serial.h" +#define QUICC2_VADS_IMM_BASE 0x04700000 +#define QUICC2_VADS_BCSR_BASE 0x04500000 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +static bool +quicc2_scc_serial_init(struct cyg_devtab_entry *tab); +static bool +quicc2_scc_serial_putc(serial_channel *chan, + unsigned char c); +static Cyg_ErrNo +quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char +quicc2_scc_serial_getc(serial_channel *chan); +static Cyg_ErrNo +quicc2_scc_serial_set_config(serial_channel *chan, + cyg_uint32 key, const void *xbuf, + cyg_uint32 *len); +static void +quicc2_scc_serial_start_xmit(serial_channel *chan); +static void +quicc2_scc_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 +quicc2_scc_serial_ISR(cyg_vector_t vector, + cyg_addrword_t data); +static void +quicc2_scc_serial_DSR(cyg_vector_t vector, + cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(quicc2_scc_serial_funs, + quicc2_scc_serial_putc, + quicc2_scc_serial_getc, + quicc2_scc_serial_set_config, + quicc2_scc_serial_start_xmit, + quicc2_scc_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 +static quicc2_scc_serial_info quicc2_scc_serial_info1; + +#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE > 0 +static unsigned char quicc2_scc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE]; +static unsigned char quicc2_scc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel1, + quicc2_scc_serial_funs, + quicc2_scc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc2_scc_serial_out_buf1[0], sizeof(quicc2_scc_serial_out_buf1), + &quicc2_scc_serial_in_buf1[0], sizeof(quicc2_scc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(quicc2_scc_serial_channel1, + quicc2_scc_serial_funs, + quicc2_scc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +static unsigned char quicc2_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1]; +static unsigned char quicc2_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1]; + +DEVTAB_ENTRY(quicc2_scc_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc2_scc_serial_init, + quicc2_scc_serial_lookup, // Serial driver may need initializing + &quicc2_scc_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 +static quicc2_scc_serial_info quicc2_scc_serial_info2; + +#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE > 0 +static unsigned char quicc2_scc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE]; +static unsigned char quicc2_scc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel2, + quicc2_scc_serial_funs, + quicc2_scc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc2_scc_serial_out_buf2[0], sizeof(quicc2_scc_serial_out_buf2), + &quicc2_scc_serial_in_buf2[0], sizeof(quicc2_scc_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(quicc2_scc_serial_channel2, + quicc2_scc_serial_funs, + quicc2_scc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc2_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1]; +static unsigned char quicc2_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM] + [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1]; + +DEVTAB_ENTRY(quicc2_scc_serial_io2, + CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + quicc2_scc_serial_init, + quicc2_scc_serial_lookup, // Serial driver may need initializing + &quicc2_scc_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +#ifdef CYGDBG_DIAG_BUF +extern int enable_diag_uart; +#endif // CYGDBG_DIAG_BUF + +// Internal function to actually configure the hardware to +// desired baud rate, stop bits and parity ... +static bool +quicc2_scc_serial_config_port(serial_channel *chan, + cyg_serial_info_t *new_config, + bool init) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; + + unsigned long b_rate = select_baud[new_config->baud]; + + if (b_rate == 0) return false; + + // Stop the transmitter while changing baud rate + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_STOP_TX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + // Disable Tx, RX and put them in a reset state + scc_chan->scc_regs->gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + // Set the baud rate + *(scc_chan->brg) = (UART_BIT_RATE(b_rate) << 1) | QUICC2_BRG_EN; + + // Set stop bits, word length and parity + scc_chan->scc_regs->psmr = QUICC2_SCC_PSMR_ASYNC | + select_stop_bits[new_config->stop] | + select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_parity[new_config->parity]; + + // Support fractional stop bits + scc_chan->scc_regs->dsr = (new_config->stop & 1) ? QUICC2_SCC_DSR_FULL : QUICC2_SCC_DSR_HALF; + + // Initialize the parameters + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + // Enable Tx and Rx + scc_chan->scc_regs->gsmr_l |= (QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +quicc2_scc_serial_init_info(quicc2_scc_serial_info *scc_chan, + int SCC_index, + int BRG_index, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF) +{ + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; +#ifdef CYGPKG_HAL_POWERPC_VADS + volatile t_BCSR *bcsr = (volatile t_BCSR *) QUICC2_VADS_BCSR_BASE; +#endif + t_UartScc_Pram *uart_pram; + scc_bd *txbd, *rxbd; + int i; + + // Disable the channel, just in case + IMM->scc_regs[SCC_index-1].gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR); + + switch (SCC_index) { + + case 1: + // Put the data into the info structure + scc_chan->scc_cpcr = QUICC2_CPCR_SCC1; + scc_chan->scc_regs = &(IMM->scc_regs[0]); + scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[0]); + scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC1; + + // Set-up the PORT D pins + IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].psor |= QUICC2_SCC1_PORTD_PDIR; + IMM->io_regs[PORT_D].ppar |= QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC1_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir |= QUICC2_SCC1_PORTD_PDIR; + IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC1_PORTD_PPAR; + + // Set-up the PORT C pins + IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].ppar |= QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC1_PORTC_PPAR; + IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC1_PORTC_PPAR; + + // Select the baud rate generator and connect it + IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC1_CLR; + + switch (BRG_index) { + case 1: + scc_chan->brg = &(IMM->brgs_brgc1); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG1; + break; + case 2: + scc_chan->brg = &(IMM->brgs_brgc2); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG2; + break; + case 3: + scc_chan->brg = &(IMM->brgs_brgc3); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG3; + break; + case 4: + scc_chan->brg = &(IMM->brgs_brgc4); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG4; + break; + } +#ifdef CYGPKG_HAL_POWERPC_VADS + // Enable the transciever + bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC1); +#endif + break; + + case 2: + // Put the data into the info structure + scc_chan->scc_cpcr = QUICC2_CPCR_SCC2; + scc_chan->scc_regs = &(IMM->scc_regs[1]); + scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[1]); + scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC2; + + // Set-up the PORT D pins + IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].ppar |= QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC2_PORTD_PPAR; + IMM->io_regs[PORT_D].pdir |= QUICC2_SCC2_PORTD_PDIR; + IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC2_PORTD_PPAR; + + // Set-up the PORT C pins + IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].ppar |= QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC2_PORTC_PPAR; + IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC2_PORTC_PPAR; + + // Select the baud rate generator and connect it + IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC2_CLR; + + switch (BRG_index) { + case 1: + scc_chan->brg = &(IMM->brgs_brgc1); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG1; + break; + case 2: + scc_chan->brg = &(IMM->brgs_brgc2); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG2; + break; + case 3: + scc_chan->brg = &(IMM->brgs_brgc3); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG3; + break; + case 4: + scc_chan->brg = &(IMM->brgs_brgc4); + IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG4; + break; + } +#ifdef CYGPKG_HAL_POWERPC_VADS + // Enable the transciever + bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC2); +#endif + break; + + default: + diag_printf("Incorrect SCC index in quicc2_scc_serial_init_info \n"); + break; + } + + // Initialize common SCC PRAM + scc_chan->tbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD); + scc_chan->rbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD); + scc_chan->txbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD); + scc_chan->rxbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD); + scc_chan->txsize = TxSIZE; + scc_chan->rxsize = RxSIZE; + + scc_chan->scc_pram->rbase = RxBD; + scc_chan->scc_pram->tbase = TxBD; + scc_chan->scc_pram->rfcr = 0x10; + scc_chan->scc_pram->tfcr = 0x10; + scc_chan->scc_pram->mrblr = RxSIZE; + + // Initialize UART PRAM + uart_pram = &(scc_chan->scc_pram->SpecificProtocol.u); + + uart_pram->max_idl = 4; + uart_pram->brkcr = 1; + uart_pram->brkln = 0; + uart_pram->parec = 0; + uart_pram->frmec = 0; + uart_pram->nosec = 0; + uart_pram->brkec = 0; + uart_pram->uaddr1 = 0; + uart_pram->uaddr2 = 0; + uart_pram->toseq = 0; + uart_pram->cc[0] = 0x8000; + uart_pram->cc[1] = 0x8000; + uart_pram->cc[2] = 0x8000; + uart_pram->cc[3] = 0x8000; + uart_pram->cc[4] = 0x8000; + uart_pram->cc[5] = 0x8000; + uart_pram->cc[6] = 0x8000; + uart_pram->cc[7] = 0x8000; + uart_pram->rccm = 0xC0FF; + + // Initialize registers + scc_chan->scc_regs->gsmr_l = QUICC2_SCC_GSMR_L_INIT; + scc_chan->scc_regs->gsmr_h = QUICC2_SCC_GSMR_H_INIT; + // scc_chan->scc_regs->psmr = 0x8000; // Set by config + scc_chan->scc_regs->todr = 0; + // scc_chan->scc_regs->dsr = 0x7e7e; // Set by config + scc_chan->scc_regs->scce = 0xffff; + scc_chan->scc_regs->sccm = (QUICC2_SCCE_BSY | QUICC2_SCCE_TX | QUICC2_SCCE_RX); + + /* setup RX buffer descriptors */ + rxbd = (struct scc_bd *)((char *) QUICC2_VADS_IMM_BASE + RxBD); + + for (i = 0; i < RxNUM; i++) { + rxbd->ctrl = QUICC2_BD_CTL_Ready | QUICC2_BD_CTL_Int; + rxbd->length = 0; + rxbd->buffer = RxBUF; + + RxBUF += RxSIZE; + rxbd++; + } + + rxbd--; + rxbd->ctrl |= QUICC2_BD_CTL_Wrap; // Last buffer + + /* setup TX buffer descriptors */ + txbd = (struct scc_bd *)((char *) QUICC2_VADS_IMM_BASE + TxBD); + + for (i = 0; i < TxNUM; i++) { + txbd->ctrl = 0; + txbd->length = 0; + txbd->buffer = TxBUF; + TxBUF += TxSIZE; + txbd++; + } + + txbd--; + txbd->ctrl |= QUICC2_BD_CTL_Wrap; // Last buffer + + // Issue Init RX & TX Parameters Command + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + return; + +} + +// Function to initialize the device. Called at bootstrap time. +static bool +quicc2_scc_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; + int TxBD, RxBD; + static int first_init = 1; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + +#ifdef CYGDBG_IO_INIT + diag_printf("QUICC2_SCC SERIAL init - dev: %x\n", + scc_chan->channel); +#endif + if (first_init) { + // Set up tables since many fields are dynamic [computed at runtime] + first_init = 0; +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 + + // Totally reset the CP + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + IMM->cpm_cpcr = QUICC2_CPCR_RESET | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + + TxBD = 0x2800; // Note: this should be configurable + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM*8; + quicc2_scc_serial_init_info(&quicc2_scc_serial_info1, + 1, // indicates SCC1 + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BRG, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc1_txbuf[0][0]), + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc1_rxbuf[0][0]) + ); +#else +#ifdef CYGPKG_HAL_POWERPC_MPC8260 + // Ensure that SCC1 side is initialized first + diag_init(); // (pull in constructor that inits diag channel) + TxBD = 0x2900; // Note : this should be inferred from the + // chip state +#else + // there is no diag device wanting to use the QUICC, so prepare it + // for SCC2 use only. + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); // Totally reset the CP + IMM->cpm_cpcr = QUICC2_CPCR_RESET | QUICC2_CPCR_READY; + while (IMM->cpm_cpcr & QUICC2_CPCR_READY); + TxBD = 0x2800; // Note: this should be configurable +#endif +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 + + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM*8; + quicc2_scc_serial_init_info(&quicc2_scc_serial_info2, + 2, // indicates SCC2 + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BRG, + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc2_txbuf[0][0]), + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE, + ALIGN_TO_CACHELINES(&quicc2_scc2_rxbuf[0][0]) + ); +#endif + } + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(scc_chan->int_vector, + 0, // CYGARC_SIU_PRIORITY_HIGH, - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + quicc2_scc_serial_ISR, + quicc2_scc_serial_DSR, + &scc_chan->serial_interrupt_handle, + &scc_chan->serial_interrupt); + cyg_drv_interrupt_attach(scc_chan->serial_interrupt_handle); + cyg_drv_interrupt_acknowledge(scc_chan->int_vector); + cyg_drv_interrupt_unmask(scc_chan->int_vector); + } + quicc2_scc_serial_config_port(chan, &chan->config, true); + if (cache_state) + HAL_DCACHE_ENABLE(); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Force the current transmit buffer to be sent +static void +quicc2_scc_serial_flush(quicc2_scc_serial_info *scc_chan) +{ + volatile struct scc_bd *txbd = scc_chan->txbd; + int cache_state; + + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_FLUSH(txbd->buffer, scc_chan->txsize); + } + + if ((txbd->length > 0) && + ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == 0)) { + txbd->ctrl |= QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int; // Signal buffer ready + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + } else { + txbd++; + } + scc_chan->txbd = (scc_bd *) txbd; + } +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +quicc2_scc_serial_putc(serial_channel *chan, unsigned char c) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile struct scc_bd *txbd, *txfirst; + bool res; + + cyg_drv_dsr_lock(); // Avoid race condition testing pointers + + txbd = (scc_bd *)(QUICC2_VADS_IMM_BASE + ((int) scc_chan->scc_pram->tbptr)); + txfirst = txbd; + + // Scan for a non-busy buffer + while (txbd->ctrl & QUICC2_BD_CTL_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + } else { + txbd++; + } + if (txbd == txfirst) break; // Went all the way around + } + + scc_chan->txbd = (scc_bd *) txbd; + if ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == 0) { + // Transmit buffer is not full/busy + txbd->buffer[txbd->length++] = c; + if (txbd->length == scc_chan->txsize) { + // This buffer is now full, tell SCC to start processing it + quicc2_scc_serial_flush(scc_chan); + } + res = true; + } else { + // No space + res = false; + } + + cyg_drv_dsr_unlock(); + return res; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +quicc2_scc_serial_getc(serial_channel *chan) +{ + unsigned char c; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile scc_bd *rxbd = scc_chan->rxbd; + + while ((rxbd->ctrl & QUICC2_BD_CTL_Ready) != 0) ; // WAIT ... + + c = rxbd->buffer[0]; + rxbd->length = scc_chan->rxsize; + rxbd->ctrl |= QUICC2_BD_CTL_Ready; + if (rxbd->ctrl & QUICC2_BD_CTL_Wrap) { + rxbd = scc_chan->rbase; + } else { + rxbd++; + } + scc_chan->rxbd = (scc_bd *) rxbd; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static Cyg_ErrNo +quicc2_scc_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + // FIXME - The documentation says that you can't change the baud rate + // again until at least two BRG input clocks have occurred. + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if ( *len < sizeof(cyg_serial_info_t) ) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if ( true != quicc2_scc_serial_config_port(chan, config, false) ) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +// Enable the transmitter (interrupt) on the device +static void +quicc2_scc_serial_start_xmit(serial_channel *chan) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + + cyg_drv_dsr_lock(); + + if (scc_chan->txbd->length == 0) { + // See if there is anything to put in this buffer, just to get it going + (chan->callbacks->xmt_char)(chan); + } + if (scc_chan->txbd->length != 0) { + // Make sure it gets started + quicc2_scc_serial_flush(scc_chan); + } + + cyg_drv_dsr_unlock(); +} + +// Disable the transmitter on the device +static void +quicc2_scc_serial_stop_xmit(serial_channel *chan) +{ + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + // If anything is in the last buffer, need to get it started + if (scc_chan->txbd->length != 0) { + quicc2_scc_serial_flush(scc_chan); + } +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +quicc2_scc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(scc_chan->int_vector); + return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +quicc2_scc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv; + volatile struct scc_regs_8260 *regs = scc_chan->scc_regs; + volatile scc_bd *txbd; + volatile scc_bd *rxbd = scc_chan->rxbd; + scc_bd *rxlast; + int i, cache_state; + +#ifdef CYGDBG_DIAG_BUF + int _time, _stime; + externC cyg_tick_count_t cyg_current_time(void); + cyg_drv_isr_lock(); + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR start - CE: %x, time: %x.%x\n", + regs->scce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + + if (regs->scce & QUICC2_SCCE_TX) { // Tx Event + +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + txbd = scc_chan->tbase; + for (i = 0; i < CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM; i++, txbd++) { + diag_printf("Tx BD: %x, length: %d, ctl: %x\n", txbd, txbd->length, txbd->ctrl); + } + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + + regs->scce = QUICC2_SCCE_TX; // Reset Tx Event + txbd = scc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (QUICC2_BD_CTL_Ready|QUICC2_BD_CTL_Int)) == QUICC2_BD_CTL_Int) { +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("TX Done - Tx: %x, length: %d, time: %x.%x\n", + txbd, txbd->length, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + txbd->length = 0; + txbd->ctrl &= ~QUICC2_BD_CTL_Int; // Reset interrupt bit + } + + if (txbd->ctrl & QUICC2_BD_CTL_Wrap) { + txbd = scc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + + while (regs->scce & QUICC2_SCCE_RX) { // Rx Event + + regs->scce = QUICC2_SCCE_RX; // Reset interrupt state; + rxlast = (scc_bd *) ((char *)QUICC2_VADS_IMM_BASE + scc_chan->scc_pram->rbptr ); + +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("Scan RX - rxbd: %x, rbptr: %x, time: %x.%x\n", + rxbd, rxlast, _stime, _time); +#endif // CYGDBG_DIAG_BUF + while (rxbd != rxlast) { + if ((rxbd->ctrl & QUICC2_BD_CTL_Ready) == 0) { +#ifdef CYGDBG_DIAG_BUF + diag_printf("rxbuf: %x, flags: %x, length: %d\n", + rxbd, rxbd->ctrl, rxbd->length); + diag_dump_buf(rxbd->buffer, rxbd->length); +#endif // CYGDBG_DIAG_BUF + + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, scc_chan->rxsize); // Make sure no stale data + } + + rxbd->length = 0; + rxbd->ctrl |= QUICC2_BD_CTL_Ready; + } + + if (rxbd->ctrl & QUICC2_BD_CTL_Wrap) { + rxbd = scc_chan->rbase; + } else { + rxbd++; + } + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + scc_chan->rxbd = (scc_bd *) rxbd; + } + + if (regs->scce & QUICC2_SCCE_BSY) { +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + diag_printf("RX BUSY interrupt\n"); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + regs->scce = QUICC2_SCCE_BSY; // Reset interrupt state; + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR done - CE: %x, time: %x.%x\n", + regs->scce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + cyg_drv_interrupt_acknowledge(scc_chan->int_vector); + cyg_drv_interrupt_unmask(scc_chan->int_vector); +#ifdef CYGDBG_DIAG_BUF + cyg_drv_isr_unlock(); +#endif // CYGDBG_DIAG_BUF +} + +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + +// ------------------------------------------------------------------------ +// EOF powerpc/quicc2_scc_serial.c
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.h @@ -0,0 +1,209 @@ +#ifndef CYGONCE_POWERPC_QUICC2_SCC_SERIAL_H +#define CYGONCE_POWERPC_QUICC2_SCC_SERIAL_H + +// ==================================================================== +// +// quicc2_scc_serial.h +// +// Device I/O - Description of PowerPC QUICC2/SCC serial hardware +// +// ==================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek +// Contributors: gthomas +// Date: 2002-2-27 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports using QUICC2/SCC + +// macro for aligning buffers to cache lines +#define ALIGN_TO_CACHELINES(b) ((cyg_uint8 *)(((CYG_ADDRESS)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1))) + +#define UART_BIT_RATE(n) \ + (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64)) + +// SCC PSMR masks .... +#define QUICC2_SCC_PSMR_ASYNC 0x8000 +#define QUICC2_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb) +#define QUICC2_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8) +#define QUICC2_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled) +#define QUICC2_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high) +#define QUICC2_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high) + +// SCC DSR masks +#define QUICC2_SCC_DSR_FULL 0x7e7e +#define QUICC2_SCC_DSR_HALF 0x467e + +// SCC GSMR masks ... +#define QUICC2_SCC_GSMR_H_INIT 0x00000060 +#define QUICC2_SCC_GSMR_L_INIT 0x00028004 +#define QUICC2_SCC_GSMR_L_ENT 0x00000010 +#define QUICC2_SCC_GSMR_L_ENR 0x00000020 + +// SCC Events (interrupts) +#define QUICC2_SCCE_BRK 0x0040 +#define QUICC2_SCCE_BSY 0x0004 +#define QUICC2_SCCE_TX 0x0002 +#define QUICC2_SCCE_RX 0x0001 + +// CP commands for SCC1 and SCC2 +#define QUICC2_CPCR_SCC1 0x00800000 +#define QUICC2_CPCR_SCC2 0x04A00000 +#define QUICC2_CPCR_READY 0x00010000 +#define QUICC2_CPCR_INIT_TX_RX 0x0 +#define QUICC2_CPCR_INIT_RX 0x1 +#define QUICC2_CPCR_INIT_TX 0x2 +#define QUICC2_CPCR_STOP_TX 0x4 +#define QUICC2_CPCR_RESTART_TX 0x6 +#define QUICC2_CPCR_RESET 0x80000000 + +// SCC Buffer descriptor control bits +#define QUICC2_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx) +#define QUICC2_BD_CTL_Wrap 0x2000 // Last buffer in list +#define QUICC2_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx) + +// PORT configuration masks for SCC1 and SCC2 +#define QUICC2_SCC1_PORTC_PPAR (0x00020000) +#define QUICC2_SCC1_PORTD_PPAR (0x00000003) +#define QUICC2_SCC1_PORTD_PDIR (0x00000002) + +#define QUICC2_SCC2_PORTC_PPAR (0x00080000) +#define QUICC2_SCC2_PORTD_PPAR (0x00000018) +#define QUICC2_SCC2_PORTD_PDIR (0x00000010) + +// SCC clock Route register constants +#define QUICC2_CMX_SCC1_CLR 0x00ffffff +#define QUICC2_CMX_SCC1_BRG1 0x00000000 +#define QUICC2_CMX_SCC1_BRG2 0x09000000; +#define QUICC2_CMX_SCC1_BRG3 0x12000000; +#define QUICC2_CMX_SCC1_BRG4 0x1b000000; + +#define QUICC2_CMX_SCC2_CLR 0xff00ffff; +#define QUICC2_CMX_SCC2_BRG1 0x00000000; +#define QUICC2_CMX_SCC2_BRG2 0x00090000; +#define QUICC2_CMX_SCC2_BRG3 0x00120000; +#define QUICC2_CMX_SCC2_BRG4 0x001b0000; + +static unsigned int select_word_length[] = { + QUICC2_SCC_PSMR_CLEN(5), // 5 bits / word (char) + QUICC2_SCC_PSMR_CLEN(6), + QUICC2_SCC_PSMR_CLEN(7), + QUICC2_SCC_PSMR_CLEN(8) +}; + +static unsigned int select_stop_bits[] = { + QUICC2_SCC_PSMR_SB(1), // 0.5 stop bit ?? + QUICC2_SCC_PSMR_SB(1), // 1 stop bit + QUICC2_SCC_PSMR_SB(2), // 1.5 stop bit + QUICC2_SCC_PSMR_SB(2) // 2 stop bits +}; + + +static unsigned int select_parity[] = { + QUICC2_SCC_PSMR_PE(0), // No parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(2)|QUICC2_SCC_PSMR_RPM(2), // Even parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(0)|QUICC2_SCC_PSMR_RPM(0), // Odd parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(3)|QUICC2_SCC_PSMR_RPM(3), // High (mark) parity + QUICC2_SCC_PSMR_PE(1)|QUICC2_SCC_PSMR_TPM(1)|QUICC2_SCC_PSMR_RPM(1), // Low (space) parity +}; + + +// Baud rate values, will be used by the macro ... +#define QUICC2_BRG_EN 0x00010000 +static unsigned long select_baud[] = { + 0, // unused + 50, + 75, + 110, + 134, + 150, + 200, + 300, + 600, + 1200, + 1800, + 2400, + 3600, + 4800, + 7200, + 9600, + 14400, + 19200, + 38400, + 57600, + 115200, + 230400 +}; + +// Board control and status registers +#define QUICC2_BCSR_EN_SCC1 0x02000000 +#define QUICC2_BCSR_EN_SCC2 0x01000000 + +typedef struct bcsr { + volatile unsigned long bcsr0; + volatile unsigned long bcsr1; + volatile unsigned long bcsr2; + volatile unsigned long bcsr3; +} t_BCSR; + + +typedef struct scc_bd{ + cyg_int16 ctrl; + cyg_int16 length; + cyg_int8 *buffer; +} scc_bd; + +typedef struct quicc2_scc_serial_info { + unsigned long scc_cpcr; // Selects scc for cpcr + volatile struct scc_regs_8260 *scc_regs; // Ptr to scc registers + volatile t_Scc_Pram *scc_pram; // Ptr to scc pram + volatile int *brg; // Ptr to baud rate generator + struct scc_bd *txbd, *rxbd; // Next Tx, Rx descriptor to use + struct scc_bd *tbase, *rbase; // First Tx, Rx descriptor + int txsize, rxsize; // Length of individual buffers + unsigned int int_vector; + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; +} quicc2_scc_serial_info; + +#endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -453,6 +453,26 @@ package CYGPKG_DEVS_FLASH_MBX { on the Motorola PowerPC/860 MBX platform." } +package CYGPKG_DEVS_FLASH_TS6 { + alias { "FLASH memory support for Delphi Communication Systems, Inc. TigerSHARC6 Board" flash_ts6 } + directory devs/flash/powerpc/ts6 + script flash_ts6.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the Delphi Communication Systems TigerSHARC6 platform." +} + +package CYGPKG_DEVS_FLASH_VADS { + alias { "FLASH memory support for Motorola MPC8260 Voyager ADS board" flash_vads } + directory devs/flash/powerpc/vads + script flash_vads.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the Motorola MPC8260 Voyager ADS platform." +} + package CYGPKG_DEVS_FLASH_CME555 { alias { "FLASH memory support for Axiom's CME555" flash_cme555 } directory devs/flash/powerpc/cme555 @@ -746,6 +766,17 @@ package CYGPKG_IO_SERIAL_POWERPC_QUICC_S description "PowerPC QUICC/SMC serial device drivers" } +package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC { + alias { "PowerPC VADS QUICC2/SCC serial device drivers" + devs_serial_quicc2_scc quicc2_scc_serial_driver + devs_serial_powerpc_quicc2_scc + devs_serial_powerpc_quicc2 quicc2_serial_driver } + hardware + directory devs/serial/powerpc/quicc2 + script ser_quicc2_scc.cdl + description "PowerPC VADS QUICC2/SCC serial device drivers" +} + package CYGPKG_IO_SERIAL_SPARCLITE_SLEB { alias { "SPARClite SLEB serial device drivers" devs_serial_sparclite_sleb sleb_serial_driver } @@ -1189,6 +1220,14 @@ package CYGPKG_DEVS_ETH_POWERPC_MBX { description "Ethernet driver specifics for Motorola MBX PowerPC (MPC8xx) based boards." } +package CYGPKG_DEVS_ETH_POWERPC_QUICC2 { + alias { "QUICC2 ethernet driver" quicc_eth_driver } + hardware + directory devs/eth/powerpc/quicc2 + script quicc2_eth_drivers.cdl + description "Fast ethernet driver for PowerPC QUICC2 (MPC8260) based boards." +} + package CYGPKG_DEVS_ETH_POWERPC_FEC { alias { "FEC ethernet driver" fec_eth_driver } hardware @@ -2414,6 +2453,17 @@ package CYGPKG_HAL_POWERPC { package." } +package CYGPKG_HAL_POWERPC_MPC8260 { + alias { "PowerPC MPC8260 variant HAL" hal_mpc8260 } + directory hal/powerpc/mpc8260/ + script hal_powerpc_mpc8260.cdl + hardware + description " + The PowerPC MPC8260 PowerQUICCII variant HAL package provides + support for this processor variant. It is also necessary to + select a specific target platform HAL package." +} + package CYGPKG_HAL_POWERPC_MPC8xx { alias { "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal } directory hal/powerpc/mpc8xx/ @@ -2527,6 +2577,28 @@ package CYGPKG_HAL_POWERPC_ADDER { eCos on a A&M ADDER board equipped with a PowerPC processor." } +package CYGPKG_HAL_POWERPC_TS6 { + alias { "Delphi TigerSHARC-6 board" hal_powerpc_ts6 powerpc_ts6_hal } + directory hal/powerpc/ts6 + script hal_powerpc_ts6.cdl + hardware + description " + The TS6 HAL package provides the support needed to run + eCos on a Delphi TigerSHARC-6 board equipped with a + PowerPC processor." +} + +package CYGPKG_HAL_POWERPC_VADS { + alias { "Motorola MPC8260 VADS board" hal_powerpc_vads powerpc_vads_hal } + directory hal/powerpc/vads + script hal_powerpc_vads.cdl + hardware + description " + The VADS HAL package provides the support needed to run + eCos on a Motorola MPC8260 VADS board equipped with a + PowerPC processor." +} + package CYGPKG_HAL_QUICC { alias { "Motorola MBX860/821 QUICC support" hal_quicc quicc_hal quicc } directory hal/powerpc/quicc @@ -3725,6 +3797,36 @@ target mbx { eCos on a Motorola MBX860 or MBX821 board." } +target ts6 { + alias { "Delphi TigerSHARC-6 board" Pleiades sixpack } + packages { CYGPKG_HAL_POWERPC + CYGPKG_HAL_POWERPC_MPC8260 + CYGPKG_HAL_POWERPC_TS6 + CYGPKG_DEVS_ETH_POWERPC_QUICC2 + CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + CYGPKG_DEVS_FLASH_TS6 + CYGPKG_DEVS_FLASH_INTEL_28FXXX + } + description " + The ts6 target provides the packages needed to run + eCos on a Delphi TigerSHARC-6 board." +} + +target vads { + alias { "Motorola MPC8260 VADS board" } + packages { CYGPKG_HAL_POWERPC + CYGPKG_HAL_POWERPC_MPC8260 + CYGPKG_HAL_POWERPC_VADS + CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC + CYGPKG_DEVS_ETH_POWERPC_QUICC2 + CYGPKG_DEVS_FLASH_VADS + CYGPKG_DEVS_FLASH_INTEL_28FXXX + } + description " + The vads target provides the packages needed to run + eCos on a Motorola MPC8260 VADS board." +} + target viper { alias { "A&M Viper PPC860 board" viper860 } packages { CYGPKG_HAL_POWERPC
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/ChangeLog @@ -0,0 +1,50 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/variant.S: + * src/var_misc.c: + * src/var_intr.c: + * src/quicc2_diag.c: + * include/variant.inc: + * include/var_regs.h: + * include/var_intr.h: + * include/var_cache.h: + * include/mpc8260.h: + * cdl/hal_powerpc_mpc8260.cdl: New package - variant support for + Motorola MPC8260 based systems. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/cdl/hal_powerpc_mpc8260.cdl @@ -0,0 +1,145 @@ +# ==================================================================== +# +# hal_powerpc_mpc8260.cdl +# +# PowerPC/MPC8260 variant architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): pfine +# Contributors: jskov +# Date: 2001-12-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_POWERPC_MPC8260 { + display "PowerPC MPC8260 variant HAL" + parent CYGPKG_HAL_POWERPC + hardware + include_dir cyg/hal + define_header hal_powerpc_mpc8260.h + description " + The PowerPC MPC8260 variant HAL package provides generic support + for this processor variant. It is also necessary to + select a specific target platform HAL package." + + # Note: This should be sub-variant specific to reduce memory use. + define_proc { + puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)" + puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)" + } + + implements CYGINT_HAL_POWERPC_VARIANT + + cdl_option CYGHWR_HAL_POWERPC_FPU { + display "Variant FPU support" + calculated 1 + } + + cdl_option CYGPKG_HAL_POWERPC_MSBFIRST { + display "CPU Variant big-endian" + calculated 1 + } + + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_powerpc.h>" + } + + cdl_option CYGNUM_HAL_DIAG_BAUD { + display "Baud rate for the HAL diagnostic port" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value 38400 + description " + This option specifies the default baud rate (speed) for the + HAL diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } +# Ultimately, I would like to change this to 2. + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The MPC8260 TS6 board has two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The MPC8260 TS6 board has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + # This option is only used when USE_ROM_MONITOR is enabled - but + # it cannot be a sub-option to that option, since the code uses the + # definition in a preprocessor comparison. + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL { + display "Debug serial port used by ROM monitor" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The MPC8260 TS6 board has two serial ports. This + option tells the code which port is in use by the ROM + monitor. It should only be necessary to change this + option if a non-standard configurated eCos GDB stub is + used." + } + + compile var_intr.c var_misc.c variant.S quicc2_diag.c +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/include/mpc8260.h @@ -0,0 +1,1234 @@ +#ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H +#define CYGONCE_HAL_PPC_QUICC2_MPC8260_H + +//========================================================================== +// +// mpc8260.h +// +// PowerPC QUICC2 register definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: Provide PPC QUICC2 definitions +// Description: Provide PPC QUICC2 definitions +// Usage: THIS IS NOT AN EXTERNAL API +// This file is in the include dir to share it between +// QUICCII serial code and MPC8260 initialization code. +// #include <cyg/hal/quicc/mpc8260.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +/*-------------------------*/ +/* Single buffer component */ +/*-------------------------*/ + +typedef struct BufferPool + +{ + CYG_BYTE RxBuffer; + CYG_BYTE TxBuffer; + +} LB; + + +/*--------------------------*/ +/* Buffer Descriptor Format */ +/*--------------------------*/ + +typedef struct BufferDescriptor + +{ + CYG_WORD16 bd_cstatus; /* control and status */ + CYG_WORD16 bd_length; /* transfer length */ + volatile CYG_BYTE *bd_addr; /* buffer address */ + +} BD; + + +/*-------------------------------*/ +/* Buffer Descriptor Ring format */ +/*-------------------------------*/ + +typedef struct BufferDescRings + +{ + BD RxBD; /* Rx BD ring */ + BD TxBD; /* Tx BD ring */ + +} BDRINGS; + +#define _Packed +#define _PackedType __attribute__((packed)) + +/****************************************************************************** +* +* PARAMETER RAM (PRAM) FOR EACH PERIPHERAL +* +* Each subsection contains protocol-specific PRAM for each peripheral, +* followed by the PRAM common to all protocols for that peripheral. These +* structs are used as needed in the main MPC8260 memory map structure. Note +* that different modes of operation will require the use of different PRAM +* structs, and that certain structs may overlay and conflict with the use of +* other PRAM areas. Consult the MPC8260 User Manual for details as to what +* is unavailable when certain protocols are run on certain peripherals. +* +******************************************************************************/ + + + +/*---------------------------------------------------------------------------*/ +/* SERIAL COMMUNICATION CONTROLLER (SCC) */ +/*---------------------------------------------------------------------------*/ + +/*----------*/ +/* SCC HDLC */ +/*----------*/ + +typedef _Packed struct +{ + CYG_BYTE reserved1[4]; /* Reserved area */ + CYG_WORD c_mask; /* CRC constant */ + CYG_WORD c_pres; /* CRC preset */ + CYG_WORD16 disfc; /* discarded frame counter */ + CYG_WORD16 crcec; /* CRC error counter */ + CYG_WORD16 abtsc; /* abort sequence counter */ + CYG_WORD16 nmarc; /* nonmatching address rx cnt */ + CYG_WORD16 retrc; /* frame transmission counter. */ + /* For FCC this area is reserved.*/ + CYG_WORD16 mflr; /* maximum frame length reg */ + CYG_WORD16 max_cnt; /* maximum length counter */ + CYG_WORD16 rfthr; /* received frames threshold */ + CYG_WORD16 rfcnt; /* received frames count */ + CYG_WORD16 hmask; /* user defined frm addr mask */ + CYG_WORD16 haddr1; /* user defined frm address 1 */ + CYG_WORD16 haddr2; /* user defined frm address 2 */ + CYG_WORD16 haddr3; /* user defined frm address 3 */ + CYG_WORD16 haddr4; /* user defined frm address 4 */ + CYG_WORD16 tmp; /* temp */ + CYG_WORD16 tmp_mb; /* temp */ +} _PackedType t_HdlcScc_Pram; + + +/*--------------*/ +/* SCC Ethernet */ +/*--------------*/ + +typedef _Packed struct +{ + CYG_WORD c_pres; /* CRC preset */ + CYG_WORD c_mask; /* CRC constant mask*/ + CYG_WORD crcec; /* CRC error counter */ + CYG_WORD alec; /* alignment error counter */ + CYG_WORD disfc; /* discarded frame counter */ + CYG_WORD16 pads; /* Short frame pad character. */ + CYG_WORD16 ret_lim; /* Retry limit threshold. */ + CYG_WORD16 ret_cnt; /* Retry limit counter. */ + CYG_WORD16 mflr; /* maximum frame length reg */ + CYG_WORD16 minflr; /* minimum frame length reg */ + CYG_WORD16 maxd1; /* max DMA1 length register. */ + CYG_WORD16 maxd2; /* max DMA2 length register. */ + CYG_WORD16 maxd; /* Rx max DMA. */ + CYG_WORD16 dma_cnt; /* Rx DMA counter. */ + CYG_WORD16 max_b; /* max buffer descriptor byte count. */ + CYG_WORD16 gaddr1; /* group address filter */ + CYG_WORD16 gaddr2; /* group address filter */ + CYG_WORD16 gaddr3; /* group address filter */ + CYG_WORD16 gaddr4; /* group address filter */ + CYG_WORD tbuf0_data0; /* Saved area 0, current frame. */ + CYG_WORD tbuf0_data1; /* Saved area 1, current frame. */ + CYG_WORD tbuf0_rba0; + CYG_WORD tbuf0_crc; + CYG_WORD16 tbuf0_bcnt; + CYG_WORD16 paddr1_h; /* physical address (MSB) */ + CYG_WORD16 paddr1_m; /* physical address */ + CYG_WORD16 paddr1_l; /* physical address (LSB) */ + CYG_WORD16 p_per; /* persistence */ + CYG_WORD16 rfbd_ptr; /* Rx first BD pointer. */ + CYG_WORD16 tfbd_ptr; /* Tx first BD pointer. */ + CYG_WORD16 tlbd_ptr; /* Tx last BD pointer. */ + CYG_WORD tbuf1_data0; /* Saved area 0, next frame. */ + CYG_WORD tbuf1_data1; /* Saved area 1, next frame. */ + CYG_WORD tbuf1_rba0; + CYG_WORD tbuf1_crc; + CYG_WORD16 tbuf1_bcnt; + CYG_WORD16 tx_len; /* tx frame length counter */ + CYG_WORD16 iaddr1; /* individual address filter. */ + CYG_WORD16 iaddr2; /* individual address filter. */ + CYG_WORD16 iaddr3; /* individual address filter. */ + CYG_WORD16 iaddr4; /* individual address filter. */ + CYG_WORD16 boff_cnt; /* back-off counter */ + CYG_WORD16 taddr_h; /* temp address (MSB) */ + CYG_WORD16 taddr_m; /* temp address */ + CYG_WORD16 taddr_l; /* temp address (LSB) */ +} _PackedType t_EnetScc_Pram; + +/*----------*/ +/* SCC UART */ +/*----------*/ + +typedef _Packed struct +{ + CYG_BYTE reserved1[8]; /* Reserved area */ + CYG_WORD16 max_idl; /* maximum idle characters */ + CYG_WORD16 idlc; /* rx idle counter (internal) */ + CYG_WORD16 brkcr; /* break count register */ + CYG_WORD16 parec; /* Rx parity error counter */ + CYG_WORD16 frmec; /* Rx framing error counter */ + CYG_WORD16 nosec; /* Rx noise counter */ + CYG_WORD16 brkec; /* Rx break character counter */ + CYG_WORD16 brkln; /* Receive break length */ + CYG_WORD16 uaddr1; /* address character 1 */ + CYG_WORD16 uaddr2; /* address character 2 */ + CYG_WORD16 rtemp; /* temp storage */ + CYG_WORD16 toseq; /* Tx out of sequence char */ + CYG_WORD16 cc[8]; /* Rx control characters */ + CYG_WORD16 rccm; /* Rx control char mask */ + CYG_WORD16 rccr; /* Rx control char register */ + CYG_WORD16 rlbc; /* Receive last break char */ +} _PackedType t_UartScc_Pram; + + +/*-----------------*/ +/* SCC Transparent */ +/*-----------------*/ + +typedef _Packed struct +{ + CYG_WORD c_mask; /* CRC constant */ + CYG_WORD c_pres; /* CRC preset */ +} _PackedType t_TransScc_Pram; + + +/*------------*/ +/* SCC Bisync */ +/*------------*/ + +typedef _Packed struct +{ + CYG_BYTE reserved1[4]; /* Reserved area */ + CYG_WORD crcc; /* CRC Constant Temp Value */ + CYG_WORD16 prcrc; /* Preset Receiver CRC-16/LRC */ + CYG_WORD16 ptcrc; /* Preset Transmitter CRC-16/LRC */ + CYG_WORD16 parec; /* Receive Parity Error Counter */ + CYG_WORD16 bsync; /* BISYNC SYNC Character */ + CYG_WORD16 bdle; /* BISYNC DLE Character */ + CYG_WORD16 cc[8]; /* Rx control characters */ + CYG_WORD16 rccm; /* Receive Control Character Mask */ +} _PackedType t_BisyncScc_Pram; + + +/*-----------------*/ +/* SCC Common PRAM */ +/*-----------------*/ + +typedef _Packed struct +{ + CYG_WORD16 rbase; /* RX BD base address */ + CYG_WORD16 tbase; /* TX BD base address */ + CYG_BYTE rfcr; /* Rx function code */ + CYG_BYTE tfcr; /* Tx function code */ + CYG_WORD16 mrblr; /* Rx buffer length */ + CYG_WORD rstate; /* Rx internal state */ + CYG_WORD rptr; /* Rx internal data pointer */ + CYG_WORD16 rbptr; /* rb BD Pointer */ + CYG_WORD16 rcount; /* Rx internal byte count */ + CYG_WORD rtemp; /* Rx temp */ + CYG_WORD tstate; /* Tx internal state */ + CYG_WORD tptr; /* Tx internal data pointer */ + CYG_WORD16 tbptr; /* Tx BD pointer */ + CYG_WORD16 tcount; /* Tx byte count */ + CYG_WORD ttemp; /* Tx temp */ + CYG_WORD rcrc; /* temp receive CRC */ + CYG_WORD tcrc; /* temp transmit CRC */ + union + { + t_HdlcScc_Pram h; + t_EnetScc_Pram e; + t_UartScc_Pram u; + t_TransScc_Pram t; + t_BisyncScc_Pram b; + } SpecificProtocol; + volatile CYG_BYTE COMPLETE_SIZE_OF_DPRAM_PAGE[0x5c]; +} _PackedType t_Scc_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* FAST COMMUNICATION CONTROLLER (FCC) */ +/*---------------------------------------------------------------------------*/ + +/*----------*/ +/* FCC HDLC */ +/*----------*/ + +typedef _Packed struct +{ + CYG_BYTE reserved1[8]; /* Reserved area */ + CYG_WORD c_mask; /* CRC constant */ + CYG_WORD c_pres; /* CRC preset */ + CYG_WORD16 disfc; /* discarded frame counter */ + CYG_WORD16 crcec; /* CRC error counter */ + CYG_WORD16 abtsc; /* abort sequence counter */ + CYG_WORD16 nmarc; /* nonmatching address rx cnt */ + CYG_WORD max_cnt; /* maximum length counter */ + CYG_WORD16 mflr; /* maximum frame length reg */ + CYG_WORD16 rfthr; /* received frames threshold */ + CYG_WORD16 rfcnt; /* received frames count */ + CYG_WORD16 hmask; /* user defined frm addr mask */ + CYG_WORD16 haddr1; /* user defined frm address 1 */ + CYG_WORD16 haddr2; /* user defined frm address 2 */ + CYG_WORD16 haddr3; /* user defined frm address 3 */ + CYG_WORD16 haddr4; /* user defined frm address 4 */ + CYG_WORD16 tmp; /* temp */ + CYG_WORD16 tmp_mb; /* temp */ +} _PackedType t_HdlcFcc_Pram; + + +/*--------------*/ +/* FCC Ethernet */ +/*--------------*/ + +typedef _Packed struct +{ + CYG_WORD stat_bus; /* Internal use buffer. */ + CYG_WORD cam_ptr; /* CAM address. */ + CYG_WORD c_mask; /* CRC constant mask*/ + CYG_WORD c_pres; /* CRC preset */ + CYG_WORD crcec; /* CRC error counter */ + CYG_WORD alec; /* alignment error counter */ + CYG_WORD disfc; /* discarded frame counter */ + CYG_WORD16 ret_lim; /* Retry limit threshold. */ + CYG_WORD16 ret_cnt; /* Retry limit counter. */ + CYG_WORD16 p_per; /* persistence */ + CYG_WORD16 boff_cnt; /* back-off counter */ + CYG_WORD gaddr_h; /* group address filter, high */ + CYG_WORD gaddr_l; /* group address filter, low */ + CYG_WORD16 tfcstat; /* out of sequece Tx BD staus. */ + CYG_WORD16 tfclen; /* out of sequece Tx BD length. */ + CYG_WORD tfcptr; /* out of sequece Tx BD data pointer. */ + CYG_WORD16 mflr; /* maximum frame length reg */ + CYG_WORD16 paddr1_h; /* physical address (MSB) */ + CYG_WORD16 paddr1_m; /* physical address */ + CYG_WORD16 paddr1_l; /* physical address (LSB) */ + CYG_WORD16 ibd_cnt; /* internal BD counter. */ + CYG_WORD16 ibd_start; /* internal BD start pointer. */ + CYG_WORD16 ibd_end; /* internal BD end pointer. */ + CYG_WORD16 tx_len; /* tx frame length counter */ + CYG_BYTE ibd_base[0x20]; /* internal micro code usage. */ + CYG_WORD iaddr_h; /* individual address filter, high */ + CYG_WORD iaddr_l; /* individual address filter, low */ + CYG_WORD16 minflr; /* minimum frame length reg */ + CYG_WORD16 taddr_h; /* temp address (MSB) */ + CYG_WORD16 taddr_m; /* temp address */ + CYG_WORD16 taddr_l; /* temp address (LSB) */ + CYG_WORD16 pad_ptr; /* pad_ptr. */ + CYG_WORD16 cf_type; /* flow control frame type coding. */ + CYG_WORD16 cf_range; /* flow control frame range. */ + CYG_WORD16 max_b; /* max buffer descriptor byte count. */ + CYG_WORD16 maxd1; /* max DMA1 length register. */ + CYG_WORD16 maxd2; /* max DMA2 length register. */ + CYG_WORD16 maxd; /* Rx max DMA. */ + CYG_WORD16 dma_cnt; /* Rx DMA counter. */ + + /* counter: */ + CYG_WORD octc; /* received octets counter. */ + CYG_WORD colc; /* estimated number of collisions */ + CYG_WORD broc; /* received good packets of broadcast address */ + CYG_WORD mulc; /* received good packets of multicast address */ + CYG_WORD uspc; /* received packets shorter then 64 octets. */ + CYG_WORD frgc; /* as uspc + bad packets */ + CYG_WORD ospc; /* received packets longer then 1518 octets. */ + CYG_WORD jbrc; /* as ospc + bad packets */ + CYG_WORD p64c; /* received packets of 64 octets.. */ + CYG_WORD p65c; /* received packets of 65-128 octets.. */ + CYG_WORD p128c; /* received packets of 128-255 octets.. */ + CYG_WORD p256c; /* received packets of 256-511 octets.. */ + CYG_WORD p512c; /* received packets of 512-1023 octets.. */ + CYG_WORD p1024c; /* received packets of 1024-1518 octets.. */ + CYG_WORD cam_buf; /* cam respond internal buffer. */ + CYG_WORD16 rfthr; /* received frames threshold */ + CYG_WORD16 rfcnt; /* received frames count */ +} _PackedType t_EnetFcc_Pram; + + +/*-----------------*/ +/* FCC Common PRAM */ +/*-----------------*/ + +typedef _Packed struct +{ + CYG_WORD16 riptr; /* Rx internal temporary data pointer. */ + CYG_WORD16 tiptr; /* Tx internal temporary data pointer. */ + CYG_WORD16 reserved0; /* Reserved */ + CYG_WORD16 mrblr; /* Rx buffer length */ + CYG_WORD rstate; /* Rx internal state */ + CYG_WORD rbase; /* RX BD base address */ + CYG_WORD16 rbdstat; /* Rx BD status and control */ + CYG_WORD16 rbdlen; /* Rx BD data length */ + CYG_WORD rdptr; /* rx BD data pointer */ + CYG_WORD tstate; /* Tx internal state */ + CYG_WORD tbase; /* TX BD base address */ + CYG_WORD16 tbdstat; /* Tx BD status and control */ + CYG_WORD16 tbdlen; /* Tx BD data length */ + CYG_WORD tdptr; /* Tx data pointer */ + CYG_WORD rbptr; /* rx BD pointer */ + CYG_WORD tbptr; /* Tx BD pointer */ + CYG_WORD rcrc; /* Temp receive CRC */ + CYG_WORD reserved_1[0x1]; + CYG_WORD tcrc; /* Temp transmit CRC */ + union /* Protocol-Specific parameter ram */ + { + t_HdlcFcc_Pram h; + t_EnetFcc_Pram e; + } SpecificProtocol; +} _PackedType t_Fcc_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* MULTICHANNEL COMMUNICATION CONTROLLER (MCC) */ +/*---------------------------------------------------------------------------*/ + +/****************************************************************************** +* Note that each MCC uses multiple logical channels. We first define the * +* PRAM for a logical channel (which can be used in either HDLC or Transparent * +* mode; wherever there are differences, it is specified), followed by the * +* PRAM for an MCC itself. * +******************************************************************************/ + +/*---------------------*/ +/* MCC Logical Channel */ +/*---------------------*/ + +typedef _Packed struct +{ + CYG_WORD tstate; /* Tx internal state. */ + CYG_WORD zistate; /* Zero insertion machine state. */ + CYG_WORD zidata0; /* Zero insertion high CYG_WORD16. */ + CYG_WORD zidata1; /* Zero insertion low CYG_WORD16. */ + CYG_WORD16 tbdflags; /* Tx internal BD flags. */ + CYG_WORD16 tbdcnt; /* Tx internal byte count . */ + CYG_WORD tbdptr; /* Tx internal data pointer. */ + CYG_WORD16 intmask; /* Interrupt mask flags. */ + CYG_WORD16 chamr; /* channel mode register. */ + CYG_WORD tcrc; /* Transparent: reserved. */ + /* Hdlc: Temp receive CRC.*/ + CYG_WORD rstate; /* Rx internal state. */ + CYG_WORD zdstate; /* Zero deletion machine state. */ + CYG_WORD zddata0; /* Zero deletion high CYG_WORD16. */ + CYG_WORD zddata1; /* Zero deletion low CYG_WORD16. */ + CYG_WORD16 rbdflags; /* Rx internal BD flags. */ + CYG_WORD16 rbdcnt; /* Rx internal byte count . */ + CYG_WORD rbdptr; /* Rx internal data pointer. */ + CYG_WORD16 maxrlen; /* Transparent: Max receive buffer length. */ + /* Hdlc: Max receive frame length. */ + CYG_WORD16 sync_maxcnt;/* Transparent: Receive synchronization pattern*/ + /* Hdlc: Max length counter. */ + CYG_WORD rcrc; /* Transparent: reserved. */ + /* Hdlc: Temp receive CRC.*/ +} _PackedType t_Mch_Pram; + + +/*----------*/ +/* MCC PRAM */ +/*----------*/ + +typedef _Packed struct +{ + CYG_WORD mccbase; /* A pointer to starting address of BD rings. */ + CYG_WORD16 mccstate; /* Controller state. */ + CYG_WORD16 mrblr; /* Maximum receive buffer length. */ + CYG_WORD16 grfthr; /* Global receive frame threshold. */ + CYG_WORD16 grfcnt; /* Global receive frame counter. */ + CYG_WORD rinttmp; /* Temp location for receive interrupt table entry. */ + CYG_WORD data0; /* Temporary location for holding data. */ + CYG_WORD data1; /* Temporary location for holding data. */ + CYG_WORD tintbase; /* Transmit interrupt table base address. */ + CYG_WORD tintptr; /* Transmit interrupt table pointer. */ + CYG_WORD tinttmp; /* Temp location for receive interrupt table entry. */ + CYG_WORD16 sctpbase; /* A pointer to the super channel transmit table*/ + CYG_BYTE res0[0x2]; /* Reserved area */ + CYG_WORD c_mask32; /* CRC constant. */ + CYG_WORD16 xtrabase; /* A pointer to the beginning of extra parameters */ + CYG_WORD16 c_mask16; /* CRC constant. */ + CYG_WORD rinttmp0; /* Temp location for receive interrupt table entry. */ + CYG_WORD rinttmp1; /* Temp location for receive interrupt table entry. */ + CYG_WORD rinttmp2; /* Temp location for receive interrupt table entry. */ + CYG_WORD rinttmp3; /* Temp location for receive interrupt table entry. */ + CYG_WORD rintbase0; /* Receive interrupt table base address. */ + CYG_WORD rintptr0; /* Receive interrupt table pointer. */ + CYG_WORD rintbase1; /* Receive interrupt table base address. */ + CYG_WORD rintptr1; /* Receive interrupt table pointer. */ + CYG_WORD rintbase2; /* Receive interrupt table base address. */ + CYG_WORD rintptr2; /* Receive interrupt table pointer. */ + CYG_WORD rintbase3; /* Receive interrupt table base address. */ + CYG_WORD rintptr3; /* Receive interrupt table pointer. */ + CYG_BYTE pad[0xa0]; +} _PackedType t_Mcc_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* ATM PARAMETER RAM */ +/*---------------------------------------------------------------------------*/ + + +/*--------------------------------------*/ +/* Address Compression parameters table */ +/*--------------------------------------*/ + +_Packed struct AddressCompressionPram +{ + volatile CYG_WORD VptBase; /* VP-level addressing table base address */ + volatile CYG_WORD VctBase; /* VC-level addressing table base address */ + volatile CYG_WORD Vpt1Base; /* VP1-level addressing table base address */ + volatile CYG_WORD Vct1Base; /* VC1-level addressing table base address */ + volatile CYG_WORD16 VpMask; /* VP mask for address compression look-up */ +} _PackedType; + + +/*-------------------------------*/ +/* External CAM parameters table */ +/*-------------------------------*/ + +_Packed struct ExtCamPram +{ + volatile CYG_WORD ExtCamBase; /* Base address of the external CAM */ + volatile CYG_BYTE reserved00[4]; /* Reserved */ + volatile CYG_WORD ExtCam1Base; /* Base address of the external CAM1 */ + volatile CYG_BYTE reserved01[6]; /* Reserved */ +} _PackedType; + + +/*---------------------------*/ +/* ATM mode parameters table */ +/*---------------------------*/ + +typedef _Packed struct AtmPram +{ + volatile CYG_BYTE reserved0[64]; /* Reserved */ + volatile CYG_WORD16 RxCellTmpBase; /* Rx cell temporary base address */ + volatile CYG_WORD16 TxCellTmpBase; /* Tx cell temporary base address */ + volatile CYG_WORD16 UdcTmpBase; /* UDC temp base address (in UDC mode only) */ + volatile CYG_WORD16 IntRctBase; /* Internal RTC base address */ + volatile CYG_WORD16 IntTctBase; /* Internal TCT base address */ + volatile CYG_WORD16 IntTcteBase; /* Internal ACT base address */ + volatile CYG_BYTE reserved1[4]; /* reserved four bytes */ + volatile CYG_WORD ExtRctBase; /* Extrnal RTC base address */ + volatile CYG_WORD ExtTctBase; /* Extrnal TCT base address */ + volatile CYG_WORD ExtTcteBase; /* Extrnal ACT base address */ + volatile CYG_WORD16 UeadOffset; /* The offset in half-wordunits of the UEAD + entry in the UDC extra header. Should be + even address. If little-endian format is + used, the UeadOffset is of the little-endian + format. */ + volatile CYG_BYTE reserved2[2]; /* Reserved */ + volatile CYG_WORD16 PmtBase; /* Performance monitoring table base address */ + volatile CYG_WORD16 ApcParamBase; /* APC Parameters table base address */ + volatile CYG_WORD16 FbpParamBase; /* Free buffer pool parameters base address */ + volatile CYG_WORD16 IntQParamBase; /* Interrupt queue parameters table base */ + volatile CYG_BYTE reserved3[2]; + volatile CYG_WORD16 UniStatTableBase; /* UNI statistics table base */ + volatile CYG_WORD BdBaseExt; /* BD ring base address extension */ + union + { + struct AddressCompressionPram AddrCompression; + struct ExtCamPram ExtCam; + } AddrMapping; /* Address look-up mechanism */ + volatile CYG_WORD16 VciFiltering; /* VCI filtering enable bits. If bit i is set, + the cell with VCI=i will be sent to the + raw cell queue. The bits 0-2 and 5 should + be zero. */ + volatile CYG_WORD16 Gmode; /* Global mode */ + volatile CYG_WORD16 CommInfo1; /* The information field associated with the */ + volatile CYG_WORD CommInfo2; /* last host command */ + volatile CYG_BYTE reserved4[4]; /* Reserved */ + volatile CYG_WORD CRC32Preset; /* Preset for CRC32 */ + volatile CYG_WORD CRC32Mask; /* Constant mask for CRC32 */ + volatile CYG_WORD16 AAL1SnpTableBase; /* AAl1 SNP protection look-up table base */ + volatile CYG_WORD16 reserved5; /* Reserved */ + volatile CYG_WORD SrtsBase; /* External SRTS logic base address. For AAL1 + only. Should be 16 bytes aligned */ + volatile CYG_WORD16 IdleBase; /* Idle cell base address */ + volatile CYG_WORD16 IdleSize; /* Idle cell size: 52, 56, 60, 64 */ + volatile CYG_WORD EmptyCellPayload; /* Empty cell payload (little-indian) */ + + /* ABR specific only */ + volatile CYG_WORD Trm; /* Upper bound on time between F-RM cells for active source */ + volatile CYG_WORD16 Nrm; /* Controls the maximum data cells sent for each F-RM cell. */ + volatile CYG_WORD16 Mrm; /* Controls bandwidth between F-RM, B-RM and user data cell */ + volatile CYG_WORD16 Tcr; /* Tag cell rate */ + volatile CYG_WORD16 AbrRxTcte; /* ABR reserved area address (2-CYG_WORD16 aligned)*/ + volatile CYG_BYTE reserved7[76]; /* Reserved */ +} _PackedType t_Atm_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* SERIAL MANAGEMENT CHANNEL (SMC) */ +/*---------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + CYG_WORD16 rbase; /* Rx BD Base Address */ + CYG_WORD16 tbase; /* Tx BD Base Address */ + CYG_BYTE rfcr; /* Rx function code */ + CYG_BYTE tfcr; /* Tx function code */ + CYG_WORD16 mrblr; /* Rx buffer length */ + CYG_WORD rstate; /* Rx internal state */ + CYG_WORD rptr; /* Rx internal data pointer */ + CYG_WORD16 rbptr; /* rb BD Pointer */ + CYG_WORD16 rcount; /* Rx internal byte count */ + CYG_WORD rtemp; /* Rx temp */ + CYG_WORD tstate; /* Tx internal state */ + CYG_WORD tptr; /* Tx internal data pointer */ + CYG_WORD16 tbptr; /* Tx BD pointer */ + CYG_WORD16 tcount; /* Tx byte count */ + CYG_WORD ttemp; /* Tx temp */ + + /* SMC UART-specific PRAM */ + CYG_WORD16 max_idl; /* Maximum IDLE Characters */ + CYG_WORD16 idlc; /* Temporary IDLE Counter */ + CYG_WORD16 brkln; /* Last Rx Break Length */ + CYG_WORD16 brkec; /* Rx Break Condition Counter */ + CYG_WORD16 brkcr; /* Break Count Register (Tx) */ + CYG_WORD16 r_mask; /* Temporary bit mask */ + +} _PackedType t_Smc_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* IDMA PARAMETER RAM */ +/*---------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + CYG_WORD16 ibase; /* IDMA BD Base Address */ + CYG_WORD16 dcm; /* DMA channel mode register */ + CYG_WORD16 ibdptr; /* next bd ptr */ + CYG_WORD16 DPR_buf; /* ptr to internal 64 byte buffer */ + CYG_WORD16 BUF_inv; /* The quantity of data in DPR_buf */ + CYG_WORD16 SS_max; /* Steady State Max. transfer size */ + CYG_WORD16 DPR_in_ptr; /* write ptr for the internal buffer */ + CYG_WORD16 sts; /* Source Transfer Size */ + CYG_WORD16 DPR_out_ptr; /* read ptr for the internal buffer */ + CYG_WORD16 seob; /* Source end of burst */ + CYG_WORD16 deob; /* Destination end of burst */ + CYG_WORD16 dts; /* Destination Transfer Size */ + CYG_WORD16 RetAdd; /* return address when ERM==1 */ + CYG_WORD16 Reserved; /* reserved */ + CYG_WORD BD_cnt; /* Internal byte count */ + CYG_WORD S_ptr; /* source internal data ptr */ + CYG_WORD D_ptr; /* destination internal data ptr */ + CYG_WORD istate; /* Internal state */ + +} _PackedType t_Idma_Pram; + + + +/*-------------------------------------------------------------------*/ +/* INTER-INTEGRATED CIRCUIT (I2C) */ +/*-------------------------------------------------------------------*/ + +typedef _Packed struct +{ + CYG_WORD16 rbase; /* RX BD base address */ + CYG_WORD16 tbase; /* TX BD base address */ + CYG_BYTE rfcr; /* Rx function code */ + CYG_BYTE tfcr; /* Tx function code */ + CYG_WORD16 mrblr; /* Rx buffer length */ + CYG_WORD rstate; /* Rx internal state */ + CYG_WORD rptr; /* Rx internal data pointer */ + CYG_WORD16 rbptr; /* rb BD Pointer */ + CYG_WORD16 rcount; /* Rx internal byte count */ + CYG_WORD rtemp; /* Rx temp */ + CYG_WORD tstate; /* Tx internal state */ + CYG_WORD tptr; /* Tx internal data pointer */ + CYG_WORD16 tbptr; /* Tx BD pointer */ + CYG_WORD16 tcount; /* Tx byte count */ + CYG_WORD ttemp; /* Tx temp */ + +} _PackedType t_I2c_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* SERIAL PERIPHERAL INTERFACE (SPI) */ +/*---------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + CYG_WORD16 rbase; /* Rx BD Base Address */ + CYG_WORD16 tbase; /* Tx BD Base Address */ + CYG_BYTE rfcr; /* Rx function code */ + CYG_BYTE tfcr; /* Tx function code */ + CYG_WORD16 mrblr; /* Rx buffer length */ + CYG_WORD rstate; /* Rx internal state */ + CYG_WORD rptr; /* Rx internal data pointer */ + CYG_WORD16 rbptr; /* Rx BD Pointer */ + CYG_WORD16 rcount; /* Rx internal byte count */ + CYG_WORD rtemp; /* Rx temp */ + CYG_WORD tstate; /* Tx internal state */ + CYG_WORD tptr; /* Tx internal data pointer */ + CYG_WORD16 tbptr; /* Tx BD pointer */ + CYG_WORD16 tcount; /* Tx byte count */ + CYG_WORD ttemp; /* Tx temp */ + CYG_BYTE reserved[8]; + +} _PackedType t_Spi_Pram; + + + +/*---------------------------------------------------------------------------*/ +/* RISC TIMER PARAMETER RAM */ +/*---------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + + CYG_WORD16 tm_base; /* RISC timer table base adr */ + CYG_WORD16 tm_ptr; /* RISC timer table pointer */ + CYG_WORD16 r_tmr; /* RISC timer mode register */ + CYG_WORD16 r_tmv; /* RISC timer valid register */ + CYG_WORD tm_cmd; /* RISC timer cmd register */ + CYG_WORD tm_cnt; /* RISC timer internal cnt */ +} _PackedType t_timer_pram; + + + +/*--------------------------------------------------------------------------*/ +/* ROM MICROCODE PARAMETER RAM AREA */ +/*--------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + CYG_WORD16 rev_num; /* Ucode Revision Number */ + CYG_WORD16 d_ptr; /* MISC Dump area pointer */ +} _PackedType t_ucode_pram; + +/*--------------------------------------------------------------------------*/ +/* MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP */ +/*--------------------------------------------------------------------------*/ + +typedef _Packed struct +{ + +/* cpm_ram */ + t_Mch_Pram mch_pram[256]; /* MCC logical channels parameter ram */ + volatile CYG_BYTE reserved0[0x4000]; /* Reserved area */ + +/* DPR_BASE+0x8000*/ + union + { + + /*for access to the PRAM structs for SCCs, FCCs, and MCCs */ + struct serials + { + t_Scc_Pram scc_pram[4]; + t_Fcc_Pram fcc_pram[3]; + t_Mcc_Pram mcc_pram[2]; + volatile CYG_BYTE reserved1[0x700]; + } serials; + + /* for access to ATM PRAM structs */ + struct atm + { + volatile CYG_BYTE reserved2[0x400]; + t_Atm_Pram atm_pram[2]; + volatile CYG_BYTE reserved3[0xa00]; + } atm; + + /* for access to the memory locations holding user-defined + base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */ + struct standard + { + volatile CYG_BYTE scc1[0x100]; + volatile CYG_BYTE scc2[0x100]; + volatile CYG_BYTE scc3[0x100]; + volatile CYG_BYTE scc4[0x100]; + volatile CYG_BYTE fcc1[0x100]; + volatile CYG_BYTE fcc2[0x100]; + volatile CYG_BYTE fcc3[0x100]; + volatile CYG_BYTE mcc1[0x80]; + volatile CYG_BYTE reserved_0[0x7c]; + volatile CYG_BYTE smc1[0x2]; + volatile CYG_BYTE idma1[0x2]; + volatile CYG_BYTE mcc2[0x80]; + volatile CYG_BYTE reserved_1[0x7c]; + volatile CYG_BYTE smc2[0x2]; + volatile CYG_BYTE idma2[0x2]; + volatile CYG_BYTE reserved_2[0xfc]; + volatile CYG_BYTE spi[0x2]; + volatile CYG_BYTE idma3[0x2]; + volatile CYG_BYTE reserved_3[0xe0]; + volatile CYG_BYTE timers[0x10]; + volatile CYG_BYTE Rev_num[0x2]; + volatile CYG_BYTE D_ptr[0x2]; + volatile CYG_BYTE reserved_4[0x4]; + volatile CYG_BYTE rand[0x4]; + volatile CYG_BYTE i2c[0x2]; + volatile CYG_BYTE idma4[0x2]; + volatile CYG_BYTE reserved_5[0x500]; + } standard; + + } pram; + + volatile CYG_BYTE reserved11[0x2000]; /* Reserved area */ + volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */ + volatile CYG_BYTE reserved12[0x4000]; /* Reserved area */ + +/* siu */ + volatile CYG_WORD siu_siumcr; /* SIU Module Configuration Register */ + volatile CYG_WORD siu_sypcr; /* System Protection Control Register */ + volatile CYG_BYTE reserved13[0x6]; /* Reserved area */ + volatile CYG_WORD16 siu_swsr; /* Software Service Register */ + +/* buses */ + volatile CYG_BYTE reserved14[0x14]; /* Reserved area */ + volatile CYG_WORD bcr; /* Bus Configuration Register */ + volatile CYG_BYTE ppc_acr; /* Arbiter Configuration Register */ + volatile CYG_BYTE reserved15[0x3]; /* Reserved area */ + volatile CYG_WORD ppc_alrh; /* Arbitration level Register (First clients)*/ + volatile CYG_WORD ppc_alrl; /* Arbitration Level Register (Next clients) */ + volatile CYG_BYTE lcl_acr; /* LCL Arbiter Configuration Register */ + volatile CYG_BYTE reserved16[0x3]; /* Reserved area */ + volatile CYG_WORD lcl_alrh; /* LCL Arbitration level Register (First clients)*/ + volatile CYG_WORD lcl_alrl; /* LCL Arbitration Level Register (Next clients) */ + volatile CYG_WORD tescr1; /* PPC bus transfer error status control register 1 */ + volatile CYG_WORD tescr2; /* PPC bus transfer error status control register 2 */ + volatile CYG_WORD ltescr1; /* Local bus transfer error status control register 1 */ + volatile CYG_WORD ltescr2; /* Local bus transfer error status control register 2 */ + volatile CYG_WORD pdtea; /* PPC bus DMA Transfer Error Address */ + volatile CYG_BYTE pdtem; /* PPC bus DMA Transfer Error MSNUM */ + volatile CYG_BYTE reserved17[0x3]; /* Reserved area */ + volatile CYG_WORD ldtea; /* PPC bus DMA Transfer Error Address */ + volatile CYG_BYTE ldtem; /* PPC bus DMA Transfer Error MSNUM */ + volatile CYG_BYTE reserved18[0xa3]; /* Reserved area */ + +/* memc */ + struct mem_regs + { + volatile CYG_WORD memc_br; /* Base Register */ + volatile CYG_WORD memc_or; /* Option Register */ + } mem_regs[12]; + volatile CYG_BYTE reserved19[0x8]; /* Reserved area */ + volatile CYG_WORD memc_mar; /* Memory Address Register */ + volatile CYG_BYTE reserved20[0x4]; /* Reserved area */ + volatile CYG_WORD memc_mamr; /* Machine A Mode Register */ + volatile CYG_WORD memc_mbmr; /* Machine B Mode Register */ + volatile CYG_WORD memc_mcmr; /* Machine C Mode Register */ + volatile CYG_WORD memc_mdmr; /* Machine D Mode Register */ + volatile CYG_BYTE reserved21[0x4]; /* Reserved area */ + volatile CYG_WORD16 memc_mptpr; /* Memory Periodic Timer Prescaler */ + volatile CYG_BYTE reserved22[0x2]; /* Reserved area */ + volatile CYG_WORD memc_mdr; /* Memory Data Register */ + volatile CYG_BYTE reserved23[0x4]; /* Reserved area */ + volatile CYG_WORD memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */ + volatile CYG_WORD memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */ + volatile CYG_BYTE memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */ + volatile CYG_BYTE reserved24[0x3]; /* Reserved area */ + volatile CYG_BYTE memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */ + volatile CYG_BYTE reserved25[0x3]; /* Reserved area */ + volatile CYG_BYTE memc_lurt; /* Local Bus assigned UPM Refresh Timer */ + volatile CYG_BYTE reserved26[0x3]; /* Reserved area */ + volatile CYG_BYTE memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */ + volatile CYG_BYTE reserved27[0x3]; /* Reserved area */ + volatile CYG_WORD memc_immr; /* Internal Memory Map Register */ + +/* pci */ + volatile CYG_WORD pcibr0; /* Base address+valid for PCI window 1 */ + volatile CYG_WORD pcibr1; /* Base address+valid for PCI window 2 */ + volatile CYG_BYTE reserved28[0x10]; /* Reserved area */ + volatile CYG_WORD pcimsk0; /* Mask for PCI window 1 */ + volatile CYG_WORD pcimsk1; /* Mask for PCI window 2 */ + volatile CYG_BYTE reserved29[0x54]; /* Reserved area */ + +/* si_timers */ + volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */ + volatile CYG_BYTE reserved30[0x2]; /* Reserved area */ + volatile CYG_WORD si_timers_tmcnt; /* Time Counter Register */ + volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/ + volatile CYG_WORD si_timers_tmcntal; /* Time Counter Alarm Register */ + volatile CYG_BYTE reserved31[0x10]; /* Reserved area */ + volatile CYG_WORD16 si_timers_piscr; /* Periodic Interrupt Status and Control Reg. */ + volatile CYG_BYTE reserved32[0x2]; /* Reserved area */ + volatile CYG_WORD si_timers_pitc; /* Periodic Interrupt Count Register */ + volatile CYG_WORD si_timers_pitr; /* Periodic Interrupt Timer Register */ + volatile CYG_BYTE reserved33[0x54]; /* Reserved area */ + +/* test module registers */ + volatile CYG_WORD tstmhr; + volatile CYG_WORD tstmlr; + volatile CYG_WORD16 tster; + volatile CYG_BYTE reserved34[0x156]; /* Reserved area */ + +/* pci, part 2 */ + volatile CYG_WORD pci_pci; /* PCI Configuration space */ + volatile CYG_BYTE reserved35[0x7fc]; /* Reserved area */ + +/* ic */ + volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register */ + volatile CYG_BYTE reserved36[0x2]; /* Reserved area */ + volatile CYG_WORD ic_sivec; /* CP Interrupt Vector Register */ + volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */ + volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */ + volatile CYG_WORD ic_siprr; /* SIU Interrupt Priority Register */ + volatile CYG_WORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */ + volatile CYG_WORD ic_scprr_l; /* Interrupt Priority Register (LOW) */ + volatile CYG_WORD ic_simr_h; /* Interrupt Mask Register (HIGH) */ + volatile CYG_WORD ic_simr_l; /* Interrupt Mask Register (LOW) */ + volatile CYG_WORD ic_siexr; /* External Interrupt Control Register */ + volatile CYG_BYTE reserved37[0x58]; /* Reserved area */ + +/* clocks */ + volatile CYG_WORD clocks_sccr; /* System Clock Control Register */ + volatile CYG_BYTE reserved38[0x4]; /* Reserved area */ + volatile CYG_WORD clocks_scmr; /* System Clock Mode Register */ + volatile CYG_BYTE reserved39[0x4]; /* Reserved area */ + volatile CYG_WORD clocks_rsr; /* Reset Status Register */ + volatile CYG_WORD clocks_rmr; /* Reset Moode Register */ + volatile CYG_BYTE reserved40[0x68]; /* Reserved area */ + +/* io_ports */ + struct io_regs + { + volatile CYG_WORD pdir; /* Port A-D Data Direction Register */ + volatile CYG_WORD ppar; /* Port A-D Pin Assignment Register */ + volatile CYG_WORD psor; /* Port A-D Special Operation Register */ + volatile CYG_WORD podr; /* Port A-D Open Drain Register */ + volatile CYG_WORD pdat; /* Port A-D Data Register */ + volatile CYG_BYTE reserved41[0xc]; /* Reserved area */ + } io_regs[4]; + +/* cpm_timers */ + volatile CYG_BYTE cpm_timers_tgcr1; /* Timer Global Configuration Register */ + volatile CYG_BYTE reserved42[0x3]; /* Reserved area */ + volatile CYG_BYTE cpm_timers_tgcr2; /* Timer Global Configuration Register */ + volatile CYG_BYTE reserved43[0xb]; /* Reserved area */ + volatile CYG_WORD16 cpm_timers_tmr1; /* Timer Mode Register */ + volatile CYG_WORD16 cpm_timers_tmr2; /* Timer Mode Register */ + volatile CYG_WORD16 cpm_timers_trr1; /* Timer Reference Register */ + volatile CYG_WORD16 cpm_timers_trr2; /* Timer Reference Register */ + volatile CYG_WORD16 cpm_timers_tcr1; /* Timer Capture Register */ + volatile CYG_WORD16 cpm_timers_tcr2; /* Timer Capture Register */ + volatile CYG_WORD16 cpm_timers_tcn1; /* Timer Counter */ + volatile CYG_WORD16 cpm_timers_tcn2; /* Timer Counter */ + volatile CYG_WORD16 cpm_timers_tmr3; /* Timer Mode Register */ + volatile CYG_WORD16 cpm_timers_tmr4; /* Timer Mode Register */ + volatile CYG_WORD16 cpm_timers_trr3; /* Timer Reference Register */ + volatile CYG_WORD16 cpm_timers_trr4; /* Timer Reference Register */ + volatile CYG_WORD16 cpm_timers_tcr3; /* Timer Capture Register */ + volatile CYG_WORD16 cpm_timers_tcr4; /* Timer Capture Register */ + volatile CYG_WORD16 cpm_timers_tcn3; /* Timer Counter */ + volatile CYG_WORD16 cpm_timers_tcn4; /* Timer Counter */ + volatile CYG_WORD16 cpm_timers_ter[4]; /* Timer Event Register */ + volatile CYG_BYTE reserved44[0x260]; /* Reserved area */ + +/* sdma general */ + volatile CYG_BYTE sdma_sdsr; /* SDMA Status Register */ + volatile CYG_BYTE reserved45[0x3]; /* Reserved area */ + volatile CYG_BYTE sdma_sdmr; /* SDMA Mask Register */ + volatile CYG_BYTE reserved46[0x3]; /* Reserved area */ + +/* idma */ + volatile CYG_BYTE idma_idsr1; /* IDMA Status Register */ + volatile CYG_BYTE reserved47[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idmr1; /* IDMA Mask Register */ + volatile CYG_BYTE reserved48[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idsr2; /* IDMA Status Register */ + volatile CYG_BYTE reserved49[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idmr2; /* IDMA Mask Register */ + volatile CYG_BYTE reserved50[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idsr3; /* IDMA Status Register */ + volatile CYG_BYTE reserved51[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idmr3; /* IDMA Mask Register */ + volatile CYG_BYTE reserved52[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idsr4; /* IDMA Status Register */ + volatile CYG_BYTE reserved53[0x3]; /* Reserved area */ + volatile CYG_BYTE idma_idmr4; /* IDMA Mask Register */ + volatile CYG_BYTE reserved54[0x2c3]; /* Reserved area */ + +/* fcc */ + struct fcc_regs + { + volatile CYG_WORD fcc_gfmr; /* FCC General Mode Register */ + volatile CYG_WORD fcc_psmr; /* FCC Protocol Specific Mode Register */ + volatile CYG_WORD16 fcc_todr; /* FCC Transmit On Demand Register */ + volatile CYG_BYTE reserved55[0x2]; /* Reserved area */ + volatile CYG_WORD16 fcc_dsr; /* FCC Data Sync. Register */ + volatile CYG_BYTE reserved56[0x2]; /* Reserved area */ + volatile CYG_WORD fcc_fcce; /* FCC Event Register */ + volatile CYG_WORD fcc_fccm; /* FCC Mask Register */ + volatile CYG_BYTE fcc_fccs; /* FCC Status Register */ + volatile CYG_BYTE reserved57[0x3]; /* Reserved area */ + volatile CYG_WORD fcc_ftprr; /* FCC Transmit Partial Rate Register */ + } fcc_regs[3]; + volatile CYG_BYTE reserved58[0x290]; /* Reserved area */ + +/* brgs 5 through 8 */ + volatile CYG_WORD brgs_brgc5; /* Baud Rate Generator 5 Config Register */ + volatile CYG_WORD brgs_brgc6; /* Baud Rate Generator 6 Config Register */ + volatile CYG_WORD brgs_brgc7; /* Baud Rate Generator 7 Config Register */ + volatile CYG_WORD brgs_brgc8; /* Baud Rate Generator 8 Config Register */ + volatile CYG_BYTE reserved59[0x260]; /* Reserved area */ + +/* i2c */ + volatile CYG_BYTE i2c_i2mod; /* IC Mode Register */ + volatile CYG_BYTE reserved60[0x3]; /* Reserved area */ + volatile CYG_BYTE i2c_i2add; /* IC Address Register */ + volatile CYG_BYTE reserved61[0x3]; /* Reserved area */ + volatile CYG_BYTE i2c_i2brg; /* IC BRG Register */ + volatile CYG_BYTE reserved62[0x3]; /* Reserved area */ + volatile CYG_BYTE i2c_i2com; /* IC Command Register */ + volatile CYG_BYTE reserved63[0x3]; /* Reserved area */ + volatile CYG_BYTE i2c_i2cer; /* IC Event Register */ + volatile CYG_BYTE reserved64[0x3]; /* Reserved area */ + volatile CYG_BYTE i2c_i2cmr; /* IC Mask Register */ + volatile CYG_BYTE reserved65[0x14b]; /* Reserved area */ + +/* cpm */ + volatile CYG_WORD cpm_cpcr; /* Communication Processor Command Register */ + volatile CYG_WORD cpm_rccr; /* RISC Configuration Register */ + volatile CYG_WORD cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */ + volatile CYG_WORD16 cpm_rctr1; /* RISC Controller Trap Register */ + volatile CYG_WORD16 cpm_rctr2; /* RISC Controller Trap Register */ + volatile CYG_WORD16 cpm_rctr3; /* RISC Controller Trap Register */ + volatile CYG_WORD16 cpm_rctr4; /* RISC Controller Trap Register */ + volatile CYG_BYTE reserved66[0x2]; /* Reserved area */ + volatile CYG_WORD16 cpm_rter; /* RISC Timers Event Register */ + volatile CYG_BYTE reserved67[0x2]; /* Reserved area */ + volatile CYG_WORD16 cpm_rtmr; /* RISC Timers Mask Register */ + volatile CYG_WORD16 cpm_rtscr; /* RISC Time-Stamp Timer Control Register */ + volatile CYG_WORD16 cpm_rmds; /* RISC Development Support Status Register */ + volatile CYG_WORD cpm_rtsr; /* RISC Time-Stamp Register */ + volatile CYG_BYTE reserved68[0xc]; /* Reserved area */ + +/* brgs 1 through 4 */ + volatile CYG_WORD brgs_brgc1; /* Baud Rate Generator 5 Config Register */ + volatile CYG_WORD brgs_brgc2; /* Baud Rate Generator 2 Config Register */ + volatile CYG_WORD brgs_brgc3; /* Baud Rate Generator 3 Config Register */ + volatile CYG_WORD brgs_brgc4; /* Baud Rate Generator 4 Config Register */ + +/* scc */ + struct scc_regs_8260 + { + volatile CYG_WORD gsmr_l; /* SCC General Mode Register */ + volatile CYG_WORD gsmr_h; /* SCC General Mode Register */ + volatile CYG_WORD16 psmr; /* SCC Protocol Specific Mode Register */ + volatile CYG_BYTE reserved69[0x2]; /* Reserved area */ + volatile CYG_WORD16 todr; /* SCC Transmit-On-Demand Register */ + volatile CYG_WORD16 dsr; /* SCC Data Synchronization Register */ + volatile CYG_WORD16 scce; /* SCC Event Register */ + volatile CYG_BYTE reserved70[0x2]; /* Reserved area */ + volatile CYG_WORD16 sccm; /* SCC Mask Register */ + volatile CYG_BYTE reserved71; /* Reserved area */ + volatile CYG_BYTE sccs; /* SCC Status Register */ + volatile CYG_BYTE reserved72[0x8]; /* Reserved area */ + } scc_regs[4]; + +/* smc */ + struct smc_regs_8260 + { + volatile CYG_BYTE reserved73[0x2]; /* Reserved area */ + volatile CYG_WORD16 smc_smcmr; /* SMC Mode Register */ + volatile CYG_BYTE reserved74[0x2]; /* Reserved area */ + volatile CYG_BYTE smc_smce; /* SMC Event Register */ + volatile CYG_BYTE reserved75[0x3]; /* Reserved area */ + volatile CYG_BYTE smc_smcm; /* SMC Mask Register */ + volatile CYG_BYTE reserved76[0x5]; /* Reserved area */ + } smc_regs[2]; + +/* spi */ + volatile CYG_WORD16 spi_spmode; /* SPI Mode Register */ + volatile CYG_BYTE reserved77[0x4]; /* Reserved area */ + volatile CYG_BYTE spi_spie; /* SPI Event Register */ + volatile CYG_BYTE reserved78[0x3]; /* Reserved area */ + volatile CYG_BYTE spi_spim; /* SPI Mask Register */ + volatile CYG_BYTE reserved79[0x2]; /* Reserved area */ + volatile CYG_BYTE spi_spcom; /* SPI Command Register */ + volatile CYG_BYTE reserved80[0x52]; /* Reserved area */ + +/* cpm_mux */ + + volatile CYG_BYTE cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */ + volatile CYG_BYTE reserved81; /* Reserved area */ + volatile CYG_BYTE cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */ + volatile CYG_BYTE reserved82; /* Reserved area */ + volatile CYG_WORD cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */ + volatile CYG_WORD cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */ + volatile CYG_BYTE cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */ + volatile CYG_BYTE reserved83; /* Reserved area */ + volatile CYG_WORD16 cpm_mux_cmxuar; /* CPM MUX UTOPIA Address Register */ + volatile CYG_BYTE reserved84[0x10]; /* Reserved area */ + +/* si */ + struct si_regs + { + volatile CYG_WORD16 si_si1mr[4]; /* SI TDM Mode Registers */ + volatile CYG_BYTE si_si1gmr; /* SI Global Mode Register */ + volatile CYG_BYTE reserved85; /* Reserved area */ + volatile CYG_BYTE si_si1cmdr; /* SI Command Register */ + volatile CYG_BYTE reserved86; /* Reserved area */ + volatile CYG_BYTE si_si1str; /* SI Status Register */ + volatile CYG_BYTE reserved87; /* Reserved area */ + volatile CYG_WORD16 si_si1rsr; /* SI RAM Shadow Address Register */ + volatile CYG_WORD16 mcc_mcce; /* MCC Event Register */ + volatile CYG_BYTE reserved88[0x2]; /* Reserved area */ + volatile CYG_WORD16 mcc_mccm; /* MCC Mask Register */ + volatile CYG_BYTE reserved89[0x2]; /* Reserved area */ + volatile CYG_BYTE mcc_mccf; /* MCC Configuration Register */ + volatile CYG_BYTE reserved90[0x7]; /* Reserved area */ + } si_regs[2]; + volatile CYG_BYTE reserved91[0x4a0]; /* Reserved area */ + +/* si_ram */ + struct si_ram + { + CYG_WORD16 si1_ram_si1_tx_ram[0x100]; /* SI Transmit Routing RAM */ + volatile CYG_BYTE reserved92[0x200]; /* Reserved area */ + CYG_WORD16 si1_ram_si1_rx_ram[0x100]; /* SI Receive Routing RAM */ + volatile CYG_BYTE reserved93[0x200]; /* Reserved area */ + } si_ram[2]; + volatile CYG_BYTE reserved94[0x1000]; /* Reserved area */ + +} _PackedType t_PQ2IMM; + + + + + +/***************************************************************************/ +/* General Global Definitions */ +/***************************************************************************/ + +#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */ +#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */ +#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */ +#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */ + +#define SCC1 0 /* SCC1 Index into SCC Regs Array */ +#define SCC2 1 /* SCC2 Index into SCC Regs Array */ +#define SCC3 2 /* SCC3 Index into SCC Regs Array */ +#define SCC4 3 /* SCC4 Index into SCC Regs Array */ + +#define SMC1 0 /* SMC1 Index into SMC Regs Array */ +#define SMC2 1 /* SMC2 Index into SMC Regs Array */ + +#define PORT_A 0 /* Parallel port A registers */ +#define PORT_B 1 /* Parallel port B registers */ +#define PORT_C 2 /* Parallel port C registers */ +#define PORT_D 3 /* Parallel port D registers */ + +/*--------------------------------*/ +/* KEEP ALIVE POWER REGISTERS KEY */ +/*--------------------------------*/ + +#define KEEP_ALIVE_KEY 0x55ccaa33 + +/*------------------------------------------* +* CPM Command Register (CPCR) * +*-------------------------------------------* +* NOTE: This register is cleared by reset. * +* See MPC8260 User's Manual. * +*-------------------------------------------*/ + +#define CPCR_RST 0x80000000 /* Software Reset Command */ +#define CPCR_FLG 0x00010000 /* Command Semaphore Flag */ + +/*-----------------------------------------------*/ +/* Definitions for SCC CPCR Subblock/Page codes. */ +/*-----------------------------------------------*/ + +#define SCC1_PAGE_SUBBLOCK 0x00800000 /* page 0, code = 4 */ +#define SCC2_PAGE_SUBBLOCK 0x04A00000 /* page 1, code = 5 */ +#define SCC3_PAGE_SUBBLOCK 0x08C00000 /* page 2, code = 6 */ +#define SCC4_PAGE_SUBBLOCK 0x0CE00000 /* page 3, code = 7 */ + +/*-----------------------------------------------*/ +/* Definitions for SMC CPCR Subblock/Page codes. */ +/*-----------------------------------------------*/ + +#define SMC1_PAGE_SUBBLOCK 0x1D000000 /* page 7, code = 8 */ +#define SMC2_PAGE_SUBBLOCK 0x21200000 /* page 8, code = 9 */ + +/*-----------------------------*/ +/* Opcode definitions for SCCs, opcodes for SMC's are the same + * except not all codes are valid for SMC */ +/*-----------------------------*/ + +#define CPCR_INIT_TX_RX_PARAMS 0x00000000 /* Opcode 0 */ +#define CPCR_INIT_RX_PARAMS 0x00000001 /* Opcode 1 */ +#define CPCR_INIT_TX_PARAMS 0x00000002 /* Opcode 2 */ +#define CPCR_ENTER_HUNT_MODE 0x00000003 /* Opcode 3 */ +#define CPCR_STOP_TX 0x00000004 /* Opcode 4 */ +#define CPCR_GRACEFUL_STOP_TX 0x00000005 /* Opcode 5 */ +#define CPCR_RESTART_TX 0x00000006 /* Opcode 6 */ +#define CPCR_CLOSE_RX_BD 0x00000007 /* Opcode 7 */ +#define CPCR_SET_GRP_ADDR 0x00000008 /* Opcode 8 */ +#define CPCR_RESET_BCS 0x0000000A /* Opcode 10 */ + +/*-----------------------------------------------------*/ +/* General Definitions for SCC CPCR Command Operations */ +/*-----------------------------------------------------*/ + +#define READY_TO_RX_CMD 0x00000000 + +/*-------------------------*/ +/* General SCC Definitions */ +/*-------------------------*/ + +#define DISABLE_TX_RX 0xFFFFFFCF /* Clear the ENT/ENR bits in the GSMR + Disables the transmit & Receive + port */ + +#define GSMR_L1_ENT 0x00000010 /* ENT bit for the GSMR low register */ +#define GSMR_L1_ENR 0x00000020 /* ENR bit for the GSMR low register */ + + +#define ALL_ONES 0xFFFF + + +#endif // ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/include/var_cache.h @@ -0,0 +1,385 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:nickg, jskov +// Date: 2001-12-12 +// Purpose: Variant cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations on the MPC8260 variant CPU. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/var_regs.h> + +#include <cyg/hal/plf_cache.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 16384 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line +#define HAL_DCACHE_WAYS 4 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line +#define HAL_ICACHE_WAYS 4 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ( \ + "mfspr %1, %2;" \ + "li %0, 0x4000;" \ + "rlwimi %1,%0,0,17,17;" \ + "sync;" \ + "mtspr %2,%1;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \ + CYG_MACRO_END + +// Disable the data cache +#define HAL_DCACHE_DISABLE() \ + CYG_MACRO_START \ + register cyg_uint32 tmp1; \ + register cyg_uint32 tmp2; \ + for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \ + tmp2 = *((cyg_uint32 *) tmp1); \ + asm volatile ( \ + "mfspr %1, %2;" \ + "li %0, 0x0;" \ + "rlwimi %1,%0,0,17,17;" \ + "sync;" \ + "mtspr %2,%1;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \ + CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ("sync;" \ + "mfspr %0, %2;" \ + "ori %0, %0, 0x0400;" \ + "mtspr %2, %0;" \ + "li %1, 0;" \ + "rlwimi %0,%1,0,21,21;" \ + "mtspr %2, %0;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\ + CYG_MACRO_END + + +// Synchronize the contents of the cache with memory. +// Use a brute force method until something better appears in my head +// By loading memory from 0x0 to HAL_DCACHE_SIZE, incremented by +// HAL_DCACHE_LINE_SIZE, it will ensure that the contents of the data +// cache is known. Then, I will traverse the loop again, this time +// flushing the address, not loading it. +#if 1 +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + volatile cyg_uint32 tmp1,tmp2; \ + for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \ + tmp2 = *((cyg_uint32 *) tmp1); \ + HAL_DCACHE_FLUSH(0x0, HAL_DCACHE_SIZE); \ + CYG_MACRO_END +#else +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + cyg_uint32 __base = 0x0, _tmp; \ + cyg_int32 __size = HAL_DCACHE_SIZE; \ + while (__size > 0) { \ + asm volatile ( \ + "lwz %0,0(%1);" \ + :"=r" (_tmp) : "r" (__base) \ + ); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + HAL_DCACHE_FLUSH( 0x0 , HAL_DCACHE_SIZE ); \ + CYG_MACRO_END +#endif + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) \ + asm volatile ("mfspr %0, %1;" \ + "rlwinm %0,%0,18,31,31;" \ + : "=r" (_state_) : "I" (CYGARC_REG_HID0)) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL() \ + asm volatile ("isync;" \ + "mfspr %0, %2;" \ + "oris %1, 0,0xFFFF;" \ + "ori %1,%1,0xEFFF;" \ + "and %0,%0,%1;" \ + "mtspr %2,%0;" \ + "isync;" \ + "sync;" \ + : /* No output */ \ + : "I" (5) /* %0 ==> r5 */, \ + "I" (6) /* %1 ==> r6 */, \ + "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + + +// Invalidate cache lines in the given range without writing to memory. +// NOTE: The errata for the 603e processor indicates use of the dcbf +// command as the dcbi command will only invalidate modified blocks. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ + CYG_MACRO_START \ + cyg_uint32 __base = (cyg_uint32) (_base_); \ + cyg_int32 __size = (cyg_int32) (_size_); \ + while (__size > 0) { \ + asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ + __base += HAL_DCACHE_LINE_SIZE; \ + __size -= HAL_DCACHE_LINE_SIZE; \ + } \ + CYG_MACRO_END + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ( \ + "mfspr %1, %2;" \ + "li %0, 0x4000;" \ + "rlwimi %1,%0,1,16,16;" \ + "sync;" \ + "isync;" \ + "mtspr %2,%1;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \ + CYG_MACRO_END + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ( \ + "mfspr %1, %2;" \ + "li %0, 0x0;" \ + "rlwimi %1,%0,0,16,16;" \ + "sync;" \ + "isync;" \ + "mtspr %2,%1;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \ + CYG_MACRO_END + +// Invalidate the entire cache +#if 1 +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ("sync;" \ + "mfspr %0, %2;" \ + "ori %1, %0, 0x8000;" \ + "isync;" \ + "mtspr %2, %1;" \ + "ori %1, %0, 0x0800;" \ + "mtspr %2, %1;" \ + "mtspr %2, %0;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\ + CYG_MACRO_END +#else +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + cyg_uint32 tmp1, tmp2; \ + asm volatile ("sync;" \ + "mfspr %0, %2;" \ + "ori %0, %0, 0x0800;" \ + "isync;" \ + "mtspr %2, %0;" \ + "li %1, 0;" \ + "rlwimi %0,%1,0,20,20;" \ + "isync;" \ + "mtspr %2, %0;" \ + "isync;" \ + "sync;" \ + : "=r" (tmp1), "=r" (tmp2) \ + : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\ + CYG_MACRO_END +#endif +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() \ + HAL_ICACHE_INVALIDATE_ALL() + + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) \ + asm volatile ("mfspr %0, %1;" \ + "rlwinm %0,%0,17,31,31;" \ + : "=r" (_state_) : "I" (CYGARC_REG_HID0)) + + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL() \ + asm volatile ("isync;" \ + "mfspr %0, %2;" \ + "oris %1, 0,0xFFFF;" \ + "ori %1,%1,0xDFFF;" \ + "and %0,%0,%1;" \ + "isync;" \ + "mtspr %2,%0;" \ + "isync;" \ + "sync;" \ + : /* No output */ \ + : "I" (5) /* %0 ==> r5 */, \ + "I" (6) /* %1 ==> r6 */, \ + "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/include/var_intr.h @@ -0,0 +1,361 @@ +#ifndef CYGONCE_VAR_INTR_H +#define CYGONCE_VAR_INTR_H +//============================================================================= +// +// var_intr.h +// +// Variant HAL interrupt and clock support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): mtek, pfine +// Contributors:nickg, jskov, jlarmour, hmt +// Date: 2001-12-12 +// Purpose: Variant interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock on the MPC8260 PowerQUICCII CPU. +// Usage: Is included via the architecture interrupt header: +// #include <cyg/hal/hal_intr.h> +// ... +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include <pkgconf/hal.h> +#include <cyg/hal/plf_intr.h> +#include <cyg/hal/mpc8260.h> // Memory map +#include <cyg/infra/cyg_type.h> // types +#include <cyg/hal/hal_io.h> // io macros +#include <cyg/infra/cyg_ass.h> // CYG_FAIL + +#define CYGARC_IMM_BASE 0x04700000 + +// Interrupts + +// The first level of external interrupts +#define CYGNUM_HAL_INTERRUPT_I2C 1 +#define CYGNUM_HAL_INTERRUPT_SPI 2 +#define CYGNUM_HAL_INTERRUPT_RISC_TIMERS 3 +#define CYGNUM_HAL_INTERRUPT_SMC1 4 +#define CYGNUM_HAL_INTERRUPT_SMC2 5 +#define CYGNUM_HAL_INTERRUPT_IDMA1 6 +#define CYGNUM_HAL_INTERRUPT_IDMA2 7 +#define CYGNUM_HAL_INTERRUPT_IDMA3 8 +#define CYGNUM_HAL_INTERRUPT_IDMA4 9 +#define CYGNUM_HAL_INTERRUPT_SDMA 10 + +#define CYGNUM_HAL_INTERRUPT_TIMER1 12 +#define CYGNUM_HAL_INTERRUPT_TIMER2 13 +#define CYGNUM_HAL_INTERRUPT_TIMER3 14 +#define CYGNUM_HAL_INTERRUPT_TIMER4 15 +#define CYGNUM_HAL_INTERRUPT_TMCNT 16 +#define CYGNUM_HAL_INTERRUPT_PIT 17 + +#define CYGNUM_HAL_INTERRUPT_IRQ1 19 +#define CYGNUM_HAL_INTERRUPT_IRQ2 20 +#define CYGNUM_HAL_INTERRUPT_IRQ3 21 +#define CYGNUM_HAL_INTERRUPT_IRQ4 22 +#define CYGNUM_HAL_INTERRUPT_IRQ5 23 +#define CYGNUM_HAL_INTERRUPT_IRQ6 24 +#define CYGNUM_HAL_INTERRUPT_IRQ7 25 + +#define CYGNUM_HAL_INTERRUPT_FCC1 32 +#define CYGNUM_HAL_INTERRUPT_FCC2 33 +#define CYGNUM_HAL_INTERRUPT_FCC3 34 + +#define CYGNUM_HAL_INTERRUPT_MCC1 36 +#define CYGNUM_HAL_INTERRUPT_MCC2 37 + +#define CYGNUM_HAL_INTERRUPT_SCC1 40 +#define CYGNUM_HAL_INTERRUPT_SCC2 41 +#define CYGNUM_HAL_INTERRUPT_SCC3 42 +#define CYGNUM_HAL_INTERRUPT_SCC4 43 + +#define CYGNUM_HAL_INTERRUPT_PC15 48 +#define CYGNUM_HAL_INTERRUPT_PC14 49 +#define CYGNUM_HAL_INTERRUPT_PC13 50 +#define CYGNUM_HAL_INTERRUPT_PC12 51 +#define CYGNUM_HAL_INTERRUPT_PC11 52 +#define CYGNUM_HAL_INTERRUPT_PC10 53 +#define CYGNUM_HAL_INTERRUPT_PC9 54 +#define CYGNUM_HAL_INTERRUPT_PC8 55 +#define CYGNUM_HAL_INTERRUPT_PC7 56 +#define CYGNUM_HAL_INTERRUPT_PC6 57 +#define CYGNUM_HAL_INTERRUPT_PC5 58 +#define CYGNUM_HAL_INTERRUPT_PC4 59 +#define CYGNUM_HAL_INTERRUPT_PC3 60 +#define CYGNUM_HAL_INTERRUPT_PC2 61 +#define CYGNUM_HAL_INTERRUPT_PC1 62 +#define CYGNUM_HAL_INTERRUPT_PC0 63 + +#define CYGNUM_HAL_INTERRUPT_ERROR 0 + +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_PC0 + +//-------------------------------------------------------------------------- +// Interrupt controller access + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED +#ifdef CYGPKG_HAL_POWERPC_MPC8260 + + + +static __inline__ void +cyg_hal_interrupt_mask ( cyg_uint32 vector ) +{ + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE; + cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h); + cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l); + + switch (vector) { + + case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0: + *reg_simr_h &= ~( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) ); + break; + + case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7: + *reg_simr_h &= ~( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) ); + break; + + case CYGNUM_HAL_INTERRUPT_TMCNT: + *reg_simr_h &= ~(0x00000004); + break; + + case CYGNUM_HAL_INTERRUPT_PIT: + *reg_simr_h &= ~(0x00000002); + break; + + case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3: + *reg_simr_l &= ~( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) ); + break; + + case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2: + *reg_simr_l &= ~( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4: + *reg_simr_l &= ~( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA: + *reg_simr_l &= ~( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) ); + break; + + case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4: + *reg_simr_l &= ~( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) ); + break; + + default: + CYG_FAIL("Unknown Interrupt in mask !!!"); + break; + } + +} + +static __inline__ void +cyg_hal_interrupt_unmask ( cyg_uint32 vector ) +{ + + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE; + cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h); + cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l); + + switch (vector) { + + case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0: + *reg_simr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) ); + break; + + case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7: + *reg_simr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) ); + break; + + case CYGNUM_HAL_INTERRUPT_TMCNT: + *reg_simr_h |= (0x00000004); + break; + + case CYGNUM_HAL_INTERRUPT_PIT: + *reg_simr_h |= (0x00000002); + break; + + case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3: + *reg_simr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) ); + break; + + case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2: + *reg_simr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4: + *reg_simr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA: + *reg_simr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) ); + break; + + case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4: + *reg_simr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) ); + break; + + default: + CYG_FAIL("Unknown Interrupt in unmask !!!"); + break; + } + +} + +static __inline__ void +cyg_hal_interrupt_acknowledge ( cyg_uint32 vector ) +{ + + volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE; + cyg_uint32 *reg_sipnr_h = (cyg_uint32 *) &(IMM->ic_sipnr_h); + cyg_uint32 *reg_sipnr_l = (cyg_uint32 *) &(IMM->ic_sipnr_l); + + switch (vector) { + + case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0: + *reg_sipnr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) ); + break; + + case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7: + *reg_sipnr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) ); + break; + + case CYGNUM_HAL_INTERRUPT_TMCNT: + *reg_sipnr_h |= (0x00000004); + break; + + case CYGNUM_HAL_INTERRUPT_PIT: + *reg_sipnr_h |= (0x00000002); + break; + + case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3: + *reg_sipnr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) ); + break; + + case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2: + *reg_sipnr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4: + *reg_sipnr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) ); + break; + + case CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA: + *reg_sipnr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) ); + break; + + case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4: + *reg_sipnr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) ); + break; + + default: + CYG_FAIL("Unknown Interrupt in unmask !!!"); + break; + } + +} + +static __inline__ void +cyg_hal_interrupt_configure ( cyg_uint32 vector, + cyg_bool level, + cyg_bool up ) +{ + // NOT IMPLEMENTED ... +} + + +static __inline__ void +cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level ) +{ + + // NOT IMPLEMENTED .... + // FACT : USER should not program the same interrupt to more than + // one priority position. + // FACT : Every interrupt has an assigned default priority. + + // PROBLEM : One has to find the previous priority of the given vector + // and swap(?) it with the requested priority owner (Not nice because + // it changes another interrupt's priority inadvertently) + +} + +// The decrementer interrupt cannnot be masked, configured or acknowledged. + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_mask ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_unmask ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_acknowledge ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ + CYG_MACRO_START \ + if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \ + cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \ + CYG_MACRO_END + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#endif +#endif + + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_INTR_H +// End of var_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/include/var_regs.h @@ -0,0 +1,252 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H + +//========================================================================== +// +// var_regs.h +// +// PowerPC MPC8260 CPU definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors: jskov +// Date: 2001-12-12 +// Purpose: Provide MPC8260 register definitions +// Description: Provide MPC8260 register definitions +// The short definitions (sans CYGARC_REG_) are exported only +// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined. +// Usage: Included via the acrhitecture register header: +// #include <cyg/hal/ppc_regs.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +//-------------------------------------------------------------------------- +#define CYGARC_REG_LR 8 // Link Register +#define CYGARC_REG_CTR 9 // Counter Register + +#define CYGARC_REG_DSISR 18 +#define CYGARC_REG_DAR 19 +#define CYGARC_REG_DEC 22 +#define CYGARC_REG_SDR1 25 + +#define CYGARC_REG_TBL 268 +#define CYGARC_REG_TBU 269 + +#define CYGARC_REG_SPRG0 272 +#define CYGARC_REG_SPRG1 273 +#define CYGARC_REG_SPRG2 274 +#define CYGARC_REG_SPRG3 275 +#define CYGARC_REG_EAR 282 +#define CYGARC_REG_PVR 287 + +#define CYGARC_REG_IBAT0U 528 +#define CYGARC_REG_IBAT0L 529 +#define CYGARC_REG_IBAT1U 530 +#define CYGARC_REG_IBAT1L 531 +#define CYGARC_REG_IBAT2U 532 +#define CYGARC_REG_IBAT2L 533 +#define CYGARC_REG_IBAT3U 534 +#define CYGARC_REG_IBAT3L 535 + +#define CYGARC_REG_DBAT0U 536 +#define CYGARC_REG_DBAT0L 537 +#define CYGARC_REG_DBAT1U 538 +#define CYGARC_REG_DBAT1L 539 +#define CYGARC_REG_DBAT2U 540 +#define CYGARC_REG_DBAT2L 541 +#define CYGARC_REG_DBAT3U 542 +#define CYGARC_REG_DBAT3L 543 + +#define CYGARC_REG_DMISS 976 +#define CYGARC_REG_DCMP 977 +#define CYGARC_REG_HASH1 978 +#define CYGARC_REG_HASH2 979 +#define CYGARC_REG_IMISS 980 +#define CYGARC_REG_ICMP 981 +#define CYGARC_REG_RPA 982 + + +// Hardware Implementation Defined Special Purpose Registers +#define CYGARC_REG_HID0 1008 +#define CYGARC_REG_HID1 1009 +#define CYGARC_REG_IABR 1010 +#define CYGARC_REG_HID2 1011 +#define CYGARC_REG_DABR 1013 + +// MPC8260 Internal Memory Mapped Registers +// These values are the offsets from the base memory address, which +// is stored in the IMMR register (0x101A8). +#define CYGARC_REG_IMM_SIUMCR 0x0000 // SIU Module Configuration Register +#define CYGARC_REG_IMM_SYPCR 0x0004 // System Protection Control Register +#define CYGARC_REG_IMM_SWSR 0x000E // Software Service Register +#define CYGARC_REG_IMM_BCR 0x0024 // Bus Configuration Register +#define CYGARC_REG_IMM_PPC_ACR 0x0028 // .60x Bus Arbiter Config Register +#define CYGARC_REG_IMM_PPC_ALRH 0x002C // .60x Bus Arb-Level[High] Register +#define CYGARC_REG_IMM_PPC_ALRL 0x0030 // .60x Bus Arb-Level[Low] Register +#define CYGARC_REG_IMM_LCL_ACR 0x0034 // Local Arbiter Config Register +#define CYGARC_REG_IMM_LCL_ACRH 0x0038 // Local Arb-Level[High] Register +#define CYGARC_REG_IMM_LCL_ACRL 0x003C // Local Arb-Level[Low] Register +#define CYGARC_REG_IMM_TESCR1 0x0040 // .60x Bus Transfer Error Status and + // Control Register 1 +#define CYGARC_REG_IMM_TESCR2 0x0044 // .60x Bus Transfer Error Status and + // Control Register 2 + +#define CYGARC_REG_IMM_LTESCR1 0x0048 // Local Bus Transfer Error Status + // and Control Register 1 +#define CYGARC_REG_IMM_LTESCR2 0x004C // Local Bus Transfer Error Status and + // //Control Register 2 + +#define CYGARC_REG_IMM_PDTEA 0x0050 // .60x Bus DMA Transfer + // Error Address +#define CYGARC_REG_IMM_PDTEM 0x0054 // .60x Bus DMA Transfer Error MSNUM +#define CYGARC_REG_IMM_LDTEA 0x0058 // Local Bus DMA Xfer Error Address +#define CYGARC_REG_IMM_LDTEM 0x005C // Local Bus DMA Transfer Error MSNUM + +#define CYGARC_REG_IMM_SCCR 0x0C80 // System Clock Control Register +#define CYGARC_REG_IMM_BR0 0x0100 // Base Register Bank 0 +#define CYGARC_REG_IMM_OR0 0x0104 // Option Register Bank 0 +#define CYGARC_REG_IMM_BR1 0x0108 // Base Register Bank 1 +#define CYGARC_REG_IMM_OR1 0x010C // Option Register Bank 1 +#define CYGARC_REG_IMM_BR2 0x0110 // Base Register Bank 2 +#define CYGARC_REG_IMM_OR2 0x0114 // Option Regiser Bank 2 +#define CYGARC_REG_IMM_BR3 0x0118 // Base Register Bank 3 +#define CYGARC_REG_IMM_OR3 0x011C // Option Register Bank 3 +#define CYGARC_REG_IMM_BR4 0x0120 // Base Register Bank 4 +#define CYGARC_REG_IMM_OR4 0x0124 // Option Register Bank 4 +#define CYGARC_REG_IMM_BR5 0x0128 // Base Register Bank 5 +#define CYGARC_REG_IMM_OR5 0x012C // Option Register Bank 5 +#define CYGARC_REG_IMM_BR6 0x0130 // Base Register Bank 6 +#define CYGARC_REG_IMM_OR6 0x0134 // Option Register Bank 6 +#define CYGARC_REG_IMM_BR7 0x0138 // Base Register Bank 7 +#define CYGARC_REG_IMM_OR7 0x013C // Option Register Bank 7 +#define CYGARC_REG_IMM_BR8 0x0140 // Base Register Bank 8 +#define CYGARC_REG_IMM_OR8 0x0144 // Option Regiser Bank 8 +#define CYGARC_REG_IMM_BR9 0x0148 // Base Register Bank 9 +#define CYGARC_REG_IMM_OR9 0x014C // Option Register Bank 9 +#define CYGARC_REG_IMM_BR10 0x0150 // Base Register Bank 10 +#define CYGARC_REG_IMM_OR10 0x0154 // Option Register Bank 10 +#define CYGARC_REG_IMM_BR11 0x0158 // Base Register Bank 11 +#define CYGARC_REG_IMM_OR11 0x015C // Option Register Bank 11 + +#define CYGARC_REG_IMM_MAR 0x0168 // Memory Address Register +#define CYGARC_REG_IMM_MAMR 0x0170 // Machine A mode Register +#define CYGARC_REG_IMM_MBMR 0x0174 // Machine B mode Register +#define CYGARC_REG_IMM_MCMR 0x0178 // Machine C mode Register + +#define CYGARC_REG_IMM_MPTPR 0x0184 // Memory Periodic Timer + // Prescaler Register +#define CYGARC_REG_IMM_MDR 0x0188 // Memory Data Register +#define CYGARC_REG_IMM_PSDMR 0x0190 // PowerPC Bus SDRAM Machine + // Mode Register +#define CYGARC_REG_IMM_LSDMR 0x0194 // Local Bus SDRAM Machine + // Mode Register +#define CYGARC_REG_IMM_PURT 0x0198 // .60x Bus-assigned UPM Refresh timer +#define CYGARC_REG_IMM_PSRT 0x019C // .60x Bus Assigned SDRAM + // Refresh Timer +#define CYGARC_REG_IMM_LURT 0x01A0 // Local Bus-assigned UPM + // Refresh timer +#define CYGARC_REG_IMM_LSRT 0x01A4 // Local Bus Assigned SDRAM + // Refresh Timer +#define CYGARC_REG_IMM_IMMR 0x01A8 // Internal I/O base register offset + +// Interrupt Controller +#define CYGARC_REG_IMM_SICR 0x0C00 // SIU Interrupt Config Register +#define CYGARC_REG_IMM_SIVEC 0x0C04 // SIU Interrupt Vector Register +#define CYGARC_REG_IMM_SIPNR_H 0x0C08 // SIU Interrupt Pending Reg. High +#define CYGARC_REG_IMM_SIPNR_L 0x0C0C // SIU Interrupt Pending Reg. Low +#define CYGARC_REG_IMM_SIPRR 0x0C10 // SIU Interrupt Priority Register +#define CYGARC_REG_IMM_SCPRR_H 0x0C14 // CPM Interrupt Priority Reg. High +#define CYGARC_REG_IMM_SCPRR_L 0x0C18 // CPM Interrupt Priority Reg. Low +#define CYGARC_REG_IMM_SIMR_H 0x0C1C // SIU Interrupt Mask Register High +#define CYGARC_REG_IMM_SIMR_L 0x0C20 // SIU Interrupt Mask Register High +#define CYGARC_REG_IMM_SIEXR 0x0C24 // SIU External Interrupt Ctrl Reg. + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#define HID0 CYGARC_REG_HID0 +#define HID1 CYGARC_REG_HID1 +#define HID2 CYGARC_REG_HID2 +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//-------------------------------------------------------------------------- +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +// BATs +#define IBAT0U 528 +#define IBAT0L 529 +#define IBAT1U 530 +#define IBAT1L 531 +#define IBAT2U 532 +#define IBAT2L 533 +#define IBAT3U 534 +#define IBAT3L 535 + +#define DBAT0U 536 +#define DBAT0L 537 +#define DBAT1U 538 +#define DBAT1L 539 +#define DBAT2U 540 +#define DBAT2L 541 +#define DBAT3U 542 +#define DBAT3L 543 + +#define UBAT_BEPIMASK 0xfffe0000 // effective address mask +#define UBAT_BLMASK 0x00001ffc // block length mask +#define UBAT_VS 0x00000002 // supervisor mode valid bit +#define UBAT_VP 0x00000001 // problem mode valid bit + +#define LBAT_BRPNMASK 0xfffe0000 // real address mask +#define LBAT_W 0x00000040 // write-through +#define LBAT_I 0x00000020 // caching-inhibited +#define LBAT_M 0x00000010 // memory coherence +#define LBAT_G 0x00000008 // guarded + +#define LBAT_PP_NA 0x00000000 // no access +#define LBAT_PP_RO 0x00000001 // read-only +#define LBAT_PP_RW 0x00000002 // read/write + + +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +//----------------------------------------------------------------------------- +#endif // ifdef CYGONCE_HAL_VAR_REGS_H +// End of var_regs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/include/variant.inc @@ -0,0 +1,338 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## MPC8260 family assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): pfine +## Contributors:jskov +## Date: 2001-12-12 +## Purpose: MPC8260 family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the MPC8260 CPU family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/arch.inc> + +##----------------------------------------------------------------------------- +#ifndef SPRG0 +#define SPRG0 272 # Counter Register +#endif +#ifndef SPRG1 +#define SPRG1 273 # Counter Register +#endif +#ifndef SPRG2 +#define SPRG2 274 # Counter Register +#endif +#ifndef SPRG3 +#define SPRG3 275 # Counter Register +#endif + +##----------------------------------------------------------------------------- +## MPC8260 defined vectors + .macro mpc8260_vector name + .p2align 8 + .globl __exception_\name +__exception_\name: + #-------------------------------------------# + # save off registers used in vector routine # + #-------------------------------------------# + + mtspr SPRG3,r3 # save r3 + mfspr r3,8 + mtspr SPRG2,r3 # save LR + + #----------------------------------------------------------------------- + # Load the vector offset value in SPRG0 for handler shifted down 8 bits. + #----------------------------------------------------------------------- + + #addi r3,r0,0x0010 + addi r3,r0,__exception_\name@l #load low 16 bits of exception vector + srawi r3,r3,8 #shift right by 8 + mtspr SPRG0,r3 + + #--------------------------------------------------------- + # load link register in order to jump to physical address + #--------------------------------------------------------- + + addis r3,0,handler@h + ori r3,r3,handler@l + mtspr 8,r3 + bclr 20,0 # jump unconditionally to address in Link + # Register (LR) + .endm + + .macro infinite_loop_vector name + .p2align 8 + .globl __exception_\name +__exception_\name: + mflr r0 + lwi r1,0x04700010 + lwi r2,0x12345678 + stw r0,0(r1) + lwi r3,__exception_\name + stw r3,4(r1) + stw r2,8(r1) +1: + nop + nop + nop + b 1b + .endm + + .macro hal_reserved_vector_00000 + infinite_loop_vector reserved + .endm +#define CYG_HAL_RESERVED_VECTOR_00000 + + .macro hal_extra_vectors + infinite_loop_vector itbl_miss + infinite_loop_vector dltlb_miss + infinite_loop_vector dstlb_miss + infinite_loop_vector iaddr_brkpt + infinite_loop_vector sys_mngmnt_intrpt +#if 0 + exception_vector reserved_01500 + exception_vector reserved_01600 + exception_vector reserved_01700 + exception_vector reserved_01800 + exception_vector reserved_01900 + exception_vector reserved_01a00 + exception_vector reserved_01b00 + exception_vector reserved_01c00 + exception_vector reserved_01d00 + exception_vector reserved_01e00 + exception_vector reserved_01f00 + exception_vector reserved_02000 + exception_vector reserved_02100 + exception_vector reserved_02200 + exception_vector reserved_02300 + exception_vector reserved_02400 + exception_vector reserved_02500 + exception_vector reserved_02600 + exception_vector reserved_02700 + exception_vector reserved_02800 + exception_vector reserved_02900 + exception_vector reserved_02a00 + exception_vector reserved_02b00 + exception_vector reserved_02c00 + exception_vector reserved_02d00 + exception_vector reserved_02e00 + exception_vector reserved_02f00 +#endif + .endm + +#if 0 +## MPC8260 defined vectors +# infinite_loop_vector macro + + .macro infinite_loop_vector name + .p2align 8 + .globl __exception_\name +__exception_\name: + nop + nop + nop + b __exception_\name + .endm + + .macro hal_extra_vectors + # MPC8260 vectors + mpc8260_vector instruction_tlb_miss + mpc8260_vector data_load_tlb_miss + mpc8260_vector data_store_tlb_miss + mpc8260_vector instruction_addr_brkpt + mpc8260_vector system_mngmnt_intrpt + .endm +#endif + +##----------------------------------------------------------------------------- +## MPC8260 CPU initialization +## +## Initialize CPU to a post-reset state, ensuring the ground doesn''t +## shift under us while we try to set things up. + + .macro hal_cpu_init + # Set up MSR (disable MMU for now) + lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR)) + sync + mtmsr r3 + sync + .endm + +##----------------------------------------------------------------------------- +## MPC8260 monitor initialization + +#ifndef CYGPKG_HAL_PPC_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + .macro hal_mon_init +#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS + # If we are starting up from ROM and want vectors in RAM + # or we are starting in RAM and NOT using a ROM monitor, + # copy exception handler code to 0. + lwi r3,rom_vectors # r3 = rom start + lwi r4,0 # r4 = ram start + lwi r5,rom_vectors_end # r5 = rom end + cmplw r3,r5 # skip if no vectors + beq 2f + + subi r3,r3,4 + subi r4,r4,4 + subi r5,r5,4 +1: + lwzu r0,4(r3) # get word from ROM + stwu r0,4(r4) # store in RAM + cmplw r3,r5 # compare + blt 1b # loop if not yet done +2: + + # Next initialize the VSR table. This happens whether the + # vectors were copied to RAM or not. + + # First fill with exception handlers + lwi r3,cyg_hal_default_exception_vsr + lwi r4,hal_vsr_table + subi r4,r4,4 + li r5,CYGNUM_HAL_VSR_COUNT +1: stwu r3,4(r4) + subi r5,r5,1 + cmpwi r5,0 + bne 1b +#endif + + # Then fill in the special vectors + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vectors, + # the rest are left to the ROM for now... + + .macro hal_mon_init + lwi r3,cyg_hal_default_interrupt_vsr + lwi r4,hal_vsr_table + stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4) + stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4) + .endm + + +#else + + .macro hal_mon_init + + .endm + +#endif + + +#define CYGPKG_HAL_PPC_MON_DEFINED + +#endif // CYGPKG_HAL_PPC_MON_DEFINED + +##----------------------------------------------------------------------------- +## MPC8260 exception state handling + .macro hal_variant_save regs + .endm + + .macro hal_variant_load regs + .endm + +##----------------------------------------------------------------------------- +## Indicate that the ISR tables are defined in variant.S + +#define CYG_HAL_PPC_ISR_TABLES_DEFINED + +##----------------------------------------------------------------------------- +## MPC8260 interrupt handling. + +#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED + +## First level decoding of MPC8xx SIU interrupt controller. + + # decode the interrupt + .macro hal_intc_decode dreg,state +#if 0 + lis r24,0x0471 # load register base + lbz r24,CYGARC_REG_IMM_SIVEC(r24) # if + //lwi \dreg,0x00ffff1c + //stw r24,0(\dreg) + stw r24,0(0) +#endif + lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number, + rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21 + //stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame. + //slwi \dreg,\dreg,2 # convert to byte offset. +#if 1 + beq 0f # done if decrementer (vec 0) + lis \dreg,0x0471 # load register base + lbz \dreg,CYGARC_REG_IMM_SIVEC(\dreg) # if external, get SIU vector + srwi \dreg,\dreg,2 # shift SIVEC value by 2 + //addi \dreg,\dreg,1 # Skip decrementer vector +0: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame. + slwi \dreg,\dreg,2 # convert to byte offset. +#endif + .endm + + +#define CYGPKG_HAL_POWERPC_INTC_DEFINED +#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/src/quicc2_diag.c @@ -0,0 +1,1129 @@ +//============================================================================= +// +// quicc2_diag.c +// +// HAL diagnostic I/O support routines for MPC8260/QUICC2 +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt, gthomas +// Date: 1999-06-08 +// Purpose: HAL diagnostics I/O support +// Description: +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_mem.h> // HAL memory definitions +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> // hal_if_init +#include <cyg/hal/hal_io.h> // hal_if_init +#include <cyg/hal/hal_misc.h> // cyg_hal_is_break + +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +// Added by WPD +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/var_intr.h> +#include <cyg/hal/mpc8260.h> // Needed for IMMR structure + +// For Baud Rate Calculation, see MPC8260 PowerQUICC II User's Manual +// 16.3 UART Baud Rate Examples, page 16-5. +// BRGCx[DIV16] = 0 ==> value of 1 (Prescale divider) +// BRGCx[EXTC] = 16.667 MHz (Baud Rate generator input clock) +// GSMRx_L[xDCR] = 16 (Sampling Rate) +// UART_CLK_DIV + 1 = +// BRGCx[EXTC] / (BRGCx[DIV16] * UART_BAUD_RATE * GSMRx_L[xDCR]) +// UART_CLK_DIV = ((66.667 MHz / 4) / (UART_BAUD_RATE * 16)) - 1 +// UART_CLK_DIV = ((66.667 MHz ) / (UART_BAUD_RATE * 64)) - 1 +// UART_CLK_DIV = ((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000 ) +// / (UART_BAUD_RATE * 64)) (Calculation will truncate, so +// lose the -1 ) +#define UART_BIT_RATE(n) \ + (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64)) +#define UART_BAUD_RATE CYGNUM_HAL_DIAG_BAUD + + +/***********************/ +/* Global Declarations */ +/***********************/ +//#define USE_SMC1 + +volatile t_PQ2IMM *IMM; /* IMM base pointer */ +volatile BDRINGS *RxTxBD; /* buffer descriptors base pointer */ +volatile LB *SCC1Buffers; /* SCC1 base pointers */ + +#define SMC1_PRAM 0x04703800 +#define BD_RX_ERROR 0xBF /* Mask for set of Receive Buffer Errors, + including: DE, LG, NO, AB, CR, OV, CD */ + +/*---------------------*/ +/* Function Prototypes */ +/*---------------------*/ + +static void InitSCC1Uart(void); +static void ConfigSCC1Clock(void); +static void InitParallelPorts(void); +static cyg_uint8 SCC1Poll(void); +static void InitBDs(void); + +static cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data); + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch); + +static cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch); + +static void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len); +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len); + +static void +cyg_hal_plf_serial_init_channel(void); + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data); + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...); + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + t_PQ2IMM *immr = (t_PQ2IMM*) __ch_data; + struct cp_bufdesc *bd; + char ch; + int res = 0; + cyg_uint32 regval; + + CYGARC_HAL_SAVE_GP(); + //GREEN_LED_ON; +/* + dbg_values[3]++; + dbg_values[10+dbg_values[3]] = + RxTxBD->RxBD.bd_cstatus + | (immr->scc_regs[SCC1].scce<<16); +*/ + *__ctrlc = 0; + if (immr->scc_regs[SCC1].scce & 0x0001) { + + // Clear the event by writing a "1" to the prpoper bit. + immr->scc_regs[SCC1].scce = 0x0001; + + if((RxTxBD->RxBD.bd_cstatus & 0x8000) == 0){ + ch = *(RxTxBD->RxBD.bd_addr); + /*----------------------*/ + /* Set Buffer Empty bit */ + /*----------------------*/ + //dbg_values[10+dbg_values[3]] = __vector | 0xffff0000; + //dbg_values[10+dbg_values[3]] |= ch << 8; + + RxTxBD->RxBD.bd_cstatus |= 0x8000; + + if( cyg_hal_is_break( &ch , 1 ) ){ + //GREEN_LED_ON; + *__ctrlc = 1; + //dbg_values[7] = immr->ic_sivec; + } + } + // Interrupt handled. Acknowledge it. + //eppc->cpmi_cisr = 0x10; + // Clear interrupt in SIPNR_L by writing a one to bit 8 (0x800000) + HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIPNR_L, + regval); + regval |= 0x00800000; + HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIPNR_L, + regval); + + res = CYG_ISR_HANDLED; + } + + //GREEN_LED_OFF; + CYGARC_HAL_RESTORE_GP(); + return res; +} + +/* Early initialization of comm channels. Must not rely + * on interrupts, yet. Interrupt operation can be enabled + * in _bsp_board_init(). + */ +void +cyg_hal_plf_serial_init(void) +{ +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + static int init = 0; // It's wrong to do this more than once + if (init) return; + init++; + + // init_channel sets the global *IMM == 0x04700000, the base of the + // Internal Memory map for the MPC8260 + cyg_hal_plf_serial_init_channel(); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0);// Should be configurable! + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, IMM); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + +#else // No CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + static int init = 0; // It's wrong to do this more than once + if (init) return; + init++; + + cyg_hal_plf_serial_init_channel(); +#endif +} + +static void +cyg_hal_plf_serial_init_channel(void) +{ + /* We will assume here that the IMMR has been programmed such that + * the internal Memory Map starts at 0x04700000. Initialization + * should have done that setup. + */ + + IMM = (t_PQ2IMM *)0x04700000; /* MPC8260 internal register map */ + + /*----------------------------------------------------------------------*/ + /* Get a pointer to the BD area on DP RAM. The buffer descriptors (BDs) */ + /* and the Rx/Tx data buffers will be located right after SCC1's para- */ + /* meter RAM area because only 2 BDs and 2 data buffers are being used */ + /* for this port and SCC1 only uses 64 bytes of it's allotted 256 for */ + /* it's parameter ram. One BD and one data buffer each for transmit and */ + /* receive will be used. This buffer descriptor area will take up 16 */ + /* bytes. */ + /*----------------------------------------------------------------------*/ + + + RxTxBD = (BDRINGS *) 0x04708070; + // (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 72); + + //RxTxBD = (BDRINGS *) + // (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 72); + + /*-------------------------------------------------------------------*/ + /* Establish the buffer pool in Dual Port RAM. We do this because the*/ + /* pool size is only 2 bytes (1 for Rx and 1 for Tx) and to avoid */ + /* disabling data cache for the memory region where BufferPool would */ + /* reside. The CPM does not recognize data in buffer pools once it */ + /* been cached. It's acesses are direct through DMA to external */ + /* memory. */ + /*-------------------------------------------------------------------*/ + + //SCC1Buffers = (LB *) + // (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 96); + + SCC1Buffers = (LB *) 0x04708090; + // (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + // + 72 + 14); + + /*----------------------------------------*/ + /* Initialize SCC1 and buffer descriptors */ + /*----------------------------------------*/ +/* while(1); */ + + InitSCC1Uart(); + +} + +/*--------------------------------------------------------------------------- +* +* FUNCTION NAME: InitBDs +* +* +* DESCRIPTION: +* +* Initializes BD rings to point RX BDs to first half of buffer pool and TX +* BDs to second half of buffer pool. This function also initializes the +* buffer descriptors control and data length fields. It also ensures that +* transmit and recieve functions are disabled before buffer descriptors are +* initialized. +* +* EXTERNAL EFFECTS: Disable Tx/Rx functions. Changes BDs in dual port ram. +* +* PARAMETERS: None +* +* RETURNS: None +* +*---------------------------------------------------------------------------*/ + +void InitBDs() + +{ + + /*--------------------------------------------------------------------*/ + /* First let's ensure the SCC1 functions are off while we program the */ + /* buffer descriptors and the parameter ram. Clear the ENT/ENR bits */ + /* in the GSMR -- disable Transmit/Receive */ + /*--------------------------------------------------------------------*/ + + IMM->scc_regs[SCC1].gsmr_l &= DISABLE_TX_RX; + + /*--------------------------------------*/ + /* Issue Init Stop TX Command for SCC1. */ + /*--------------------------------------*/ + + while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); + + IMM->cpm_cpcr = SCC1_PAGE_SUBBLOCK | + CPCR_STOP_TX | + CPCR_FLG; /* ISSUE COMMAND */ + + while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); + + + /*-----------------------------------*/ + /* Setup Receiver Buffer Descriptors */ + /*-----------------------------------*/ + +#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + /* Set receive Buffer to generate an interrupt when buffer full */ + RxTxBD->RxBD.bd_cstatus = 0xB000; /* 0xB000; */ +#else + RxTxBD->RxBD.bd_cstatus = 0xA000; /* Empty, Wrap Bit */ +#endif + //dbg_values[3] = RxTxBD->RxBD.bd_cstatus; + RxTxBD->RxBD.bd_length = 1; + RxTxBD->RxBD.bd_addr = &(SCC1Buffers->RxBuffer); + + /*--------------------------------------*/ + /* Setup Transmitter Buffer Descriptors */ + /*--------------------------------------*/ + + RxTxBD->TxBD.bd_cstatus = 0x2800; /* Buffer not yet ready; Wrap Bit + Clear-to-send_report */ + + RxTxBD->TxBD.bd_length = 1; + RxTxBD->TxBD.bd_addr = &(SCC1Buffers->TxBuffer); + +} /* end InitBDs */ + + +/*--------------------------------------------------------------------------- +* +* FUNCTION NAME: InitSCC1Uart +* +* +* DESCRIPTION: +* +* SCC1 Uart Mode Initialization Routine. +* +* EXTERNAL EFFECT: +* +* Initializes SCC1 to operate in Uart mode at 9600 Baud, No Parity, 8 data +* bits, and 1 stop bit. +* +* PARAMETERS: None +* +* RETURNS: None +* +*--------------------------------------------------------------------------*/ + +void InitSCC1Uart() + +{ + cyg_uint32 regval; + /*----------------------------------------------------------------------*/ + /* Configure the parallel ports so that TXD and RXD are connected to */ + /* the appropriate port pins and are configured according to their */ + /* functions. */ + /*----------------------------------------------------------------------*/ + + InitParallelPorts(); + + /*------------------------------------------*/ + /* Configure Clock Source and Clock Routing */ + /*------------------------------------------*/ + + ConfigSCC1Clock(); + + /*-----------------------------------*/ + /* Initialize the Buffer Descriptors */ + /*-----------------------------------*/ + + InitBDs(); + + /*----------------------------------------------------------------------*/ + /* Program Rx and Tx Function Codes (RFCRx/TFCRx). */ + /* */ + /* - Bits 0-1 reserved. Set to zero. */ + /* */ + /* - GBL (Global) = 0 = Snooping Disabled. */ + /* */ + /* - BO (Byte Ordering) = 11 = Big-endian or true little-endian. */ + /* */ + /* - TC[2] (Transfer Code) = 0 = Transfer code is 0 */ + /* */ + /* - DTB (Data Bus Indicator) = 1 = */ + /* */ + /* Use the Local Bus for SDMA operation. In this example it doesn't */ + /* matter because the buffer were located in parameter ram. Normally */ + /* this bit would be set because data buffers normally will reside */ + /* in Local memory. */ + /*----------------------------------------------------------------------*/ + + IMM->pram.serials.scc_pram[SCC1].rfcr = 0x18; + + IMM->pram.serials.scc_pram[SCC1].tfcr = 0x18; + + IMM->scc_regs[SCC1].psmr = 0xB000; + + /*------------------------------------------------------------*/ + /* Set RBASE, TBASE -- Rx,Tx Buffer Descriptor Base Addresses */ + /*------------------------------------------------------------*/ + + IMM->pram.serials.scc_pram[SCC1].rbase = (CYG_WORD16)&RxTxBD->RxBD; + + IMM->pram.serials.scc_pram[SCC1].tbase = (CYG_WORD16)&RxTxBD->TxBD; + + /*-----------------------------------------*/ + /* Set MRBLR -- Max. Receive Buffer Length */ + /*-----------------------------------------*/ + + IMM->pram.serials.scc_pram[SCC1].mrblr = 1; + + /*----------------------------------------------------------------------*/ + /* Program the General SCC Mode Register High (GSMR_H) */ + /* */ + /* - Bits 0-14 Reserved. Set to 0. */ + /* */ + /* - GDE (Glitch Detect Enable) = 0 = No Glitch Detect. BRG supplies */ + /* the clock so there's no need to */ + /* detect glitches. */ + /* */ + /* - TCRC (Transparent CRC) = 00 = This field is ignored for Uart mode. */ + /* */ + /* - REVD (Reverse Data) = 0 = This field is ignored for Uart mode. */ + /* */ + /* - TRX,TTX (Transparent Receiver/Transmitter) = 00 = Normal operation */ + /* */ + /* - CDP,CTSP (CD/ & CTS/ sampling) = 00 = Normal Operation (envelope */ + /* mode. */ + /* */ + /* - CDS,CTSS (CD/ & CTSS Sampling) = 00 = */ + /* */ + /* CD/ or CTS/ is assumed to be asynchronous with data. It is */ + /* internally synchronized by the SCC, then data is received (CD/) */ + /* or sent (CTS/) after several clock delays. */ + /* */ + /* - TFL (Transmit FIFO length) = 0 = */ + /* */ + /* Normal Operation. The SCC transmit FIFO is 32 bytes. */ + /* */ + /* - RFW (Rx FIFO Width) = 1 = */ + /* */ + /* Low-latency operation.The receive FIFO is 8 bits wide, reducing */ + /* the Rx FIFO to a quarter of it's normal size. This allows data to */ + /* be written to the buffer as soon as a character is received, */ + /* instead of waiting to receive 32 bits. This configuration must be */ + /* chosen for character-oriented protocols, such as UART. It can */ + /* also be used for low-performance, low-latency, transparent */ + /* operation. */ + /* */ + /* - TXSY (Trasnmitter Synchronized) = 0 = */ + /* */ + /* No synchronization between receiver and transmitter. */ + /* */ + /* - SYNL (Sync Length) = 0 = An external sync (CD/) is used instead of */ + /* the sync pattern in the DSR. */ + /* */ + /* - RTSM (RTS/ Mode) = 0 = Send idles between frames as defined by the */ + /* protocol and the TEND bit. TRS/ is negated */ + /* between frames. */ + /* */ + /* - RSYN (Receive Synchronization Timing) = 0 = This field is ignored */ + /* for Uart mode. */ + /* */ + /*----------------------------------------------------------------------*/ + + IMM->scc_regs[SCC1].gsmr_h = 0x00000060; + + + /*----------------------------------------------------------------------*/ + /* Program the General SCC Mode Register High (GSMR_L) */ + /* */ + /* - Bit 0 Reserved. Set to 0. */ + /* */ + /* - EDGE (Clock Edge) = 00 = Ignored in Uart Mode. */ + /* */ + /* - TCI (Transmit Clock Invert) = 0 = Normal Operation */ + /* */ + /* - TSNC (Transmit Sense) = 00 = Infinite. Carrier sense is always */ + /* active. */ + /* */ + /* - RINV (DPLL Rx Input Invert) = 0 = Do not invert. */ + /* */ + /* - TINV (DPLL Tx Input Invert) = 0 = Do not invert. */ + /* */ + /* - TPL (Tx Preamble Length) = 000 = No Preamble. */ + /* */ + /* - TPP (Tx Preamble Pattern) = 00 = All zeros. This field is ignored */ + /* for Uart mode. */ + /* */ + /* - TEND (Transmitter Frame Ending) = 0 = */ + /* */ + /* Default operation. TxD is encoded only when data is sent, */ + /* including the preamble and opening and closing flags/syncs. When */ + /* no data is available to send, the signal is driven high. */ + /* */ + /* - TDCR (Transmitter DPLL Clock Rate) = 10 = */ + /* */ + /* 16x clock mode. This value is normally chosen for Uart mode. */ + /* */ + /* - RDCR (Receiver DPLL Clock Rate) = 10 = */ + /* */ + /* 16x clock mode. This value is normally chosen for Uart mode. */ + /* */ + /* - RENC (Receiver Decoding Method) = 000 = */ + /* */ + /* NRZ. Required for Uart Mode (asynchronous or synchronous). */ + /* */ + /* - TENC (Transmitter Encoding Method) = 000 = */ + /* */ + /* NRZ. Required for Uart Mode (asynchronous or synchronous). */ + /* */ + /* - DIAG (Diagnostic Mode) = 01 = Loopback */ + /* */ + /* - ENR (Enable Receiver) = 0 = Disabled for now. Will enabled later in*/ + /* this function. */ + /* */ + /* - ENT (Enable Transmitter) = 0 = Disabled for now. Will enable later */ + /* in this function. */ + /* */ + /* - MODE (Channel Protocol Mode) = 0100 = Uart mode. */ + /* */ + /*----------------------------------------------------------------------*/ + + + IMM->scc_regs[SCC1].gsmr_l = 0x00028004; + + /*-----------------------------------------*/ + /* Clear SCCE Register by writing all 1's. */ + /*-----------------------------------------*/ + + IMM->scc_regs[SCC1].scce = ALL_ONES; + + /*----------------------------------------------------------------------*/ + /* Issue Init RX & TX Parameters Command for SCC1. This command to the */ + /* CP lets it know to reinitialize SCC1 with the new parameter RAM */ + /* values. When the ENT/ENR bits are set below Hunt Mode will begin */ + /* automatically. */ + /*----------------------------------------------------------------------*/ + + while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); + + IMM->cpm_cpcr = SCC1_PAGE_SUBBLOCK | + CPCR_INIT_TX_RX_PARAMS | + CPCR_FLG; /* ISSUE COMMAND */ + + while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); + + /*-------------------------------------------------------------*/ + /* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */ + /*-------------------------------------------------------------*/ + + IMM->scc_regs[SCC1].gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR; +#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) +#define PFADDED +#ifdef PFADDED + // Fill out the control Character Table. Make the first entry + // an end of table line. + // cc[0] = 0x4003 ==> reject if char = 0x3, write to RCCR + IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.cc[0] = 0x4003; + { + int i; + for (i = 0; i < 8; i++){ + IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.cc[i] = 0x8000; + } + } + + IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.rccm = 0xc000; +#endif + /*-----------------------------------------*/ + /* Write to the SCCM mask register to enable an CCR interrupt*/ + /*-----------------------------------------*/ + IMM->scc_regs[SCC1].sccm = 0x1; + + /* Unmask the CPM SCC1 interrupt */ + HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + regval |= 0x00800000; + HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + +#endif +} /* end SCC1HInit() */ + + +/*-------------------------------------------------------------------------- +* +* FUNCTION NAME: ConfigSCC1Clock +* +* DESCRIPTION: +* +* This function will configure SCC1 to utilize Baud Rate Generator #1. It +* will program the the baud rate generator and configure the SMXSCR +* register in the CPM Mux block to route the clock to SCC1. SCC2, SCC3, and +* SCC4 are also programmed to assume Baud Rate Generator #1, #2, and #3 +* respectively to be routed to them. There was no special reason for doing +* this; The bit values needed to be programmed to something. +* +* +* EXTERNAL EFFECTS: BRGC1 and CMXSCR +* +* PARAMETERS: +* +* RETURNS: Nothing +* +*--------------------------------------------------------------------------*/ + +void ConfigSCC1Clock() + +{ + /* FIXME --- This picture is not accurate */ + /*----------------------------------------------------------------------*/ + /* Initialize Baud Rate Generator #1 to generate a 9600 clock. The */ + /* source of the clock starts with the input clock that is generated */ + /* external to the MPC8260 by a clock generator. This clock is then */ + /* fed to the CPM PLL where it is multiplied up and the output freq- */ + /* uency is determined by the MODCLK_HI bits in the Hard Reset Config- */ + /* uration Word and MODCK pins on the MPC8260. This output is fed to a */ + /* general purpose Baud Rate Generator Divider that services all 8 baud */ + /* rate generators. From the output of this divider the the clock goes */ + /* to the baud rate generator circuitry where, in this case, BRGCLK is */ + /* selected to be BRGO1 (the output clock). This frequency is deter- */ + /* mined by a Divide by 1 or 16 divider and then a 12 bit Prescaler */ + /* divider. the clock then goes to the CPM Mux where BRG1 is selected */ + /* to be TCLK and RCLK to SCC1. This is accomplished by programming the */ + /* CMXSCR register. TCLK and RCLK are then routed to the SCC1 DPLL */ + /* circuitry at 9600 baud where the DPLL will be programmed to multiply */ + /* the frequency by X16 for UART over-sampling. Here a diagram and the */ + /* programming: */ + /* */ + /* ---------- --------- --------------------- */ + /* |External| |MPC8260| 132 Mhz |General Purpose | 16.5 Mhz */ + /* |Clk Gen |----|CPM PLL|---------|Baud Rate Generator|--------->| */ + /* |66 Mhz | |Block | |Divider [/8] (SCCR)| | */ + /* ---------- --------- --------------------- | */ + /* | */ + /* |<-------------------------------------------------------------| */ + /* | */ + /* | ------------------------ ------------------- */ + /* |-->|Divide by 1 or 16 in | 1.03125 Mhz |12 Bit Prescaler | BRG01 */ + /* |Baud Rate Generator |------------->|in Baud Rate Gen. |--| */ + /* |Block [/16 selected] | |Block [107(0x6B) | | */ + /* |(BRGC1 Programmed) | |(BRGC1 Programmed)| | */ + /* ------------------------ -------------------- | */ + /* | */ + /* |<--------------------------------------------------------------| */ + /* | */ + /* | -------------- TCLK ---------- */ + /* | 9.638 Khz | CPM Mux |------>| SCC1 |----> TCLK*16 }*16 for */ + /* |----------->| (CMXSCR) | RCLK | DPLL | }over- */ + /* |(Programmed)|------>| *16 |----> RCLK*16 }sampling */ + /* -------------- |(GSMR_L)| */ + /* ---------- */ + /* */ + /* SCCR was programmed in init8260.s. BRGC1,CMXSCR will be programmed */ + /* in this function. GSMR_L will be programmed in InitSCC1Uart(). */ + /* */ + /*----------------------------------------------------------------------*/ + + /*----------------------------------------------------------------------*/ + /* Program Baud Rate Generator Configuration #1 Register (BRGC1). */ + /* */ + /* - Bits 0-13 are reserved. Set to 0. */ + /* */ + /* - RST (Reset BRG) = 0 = Enable the BRG */ + /* */ + /* - EN (Enable BRG Count) = 1 = Enable clocks to the BRG */ + /* */ + /* - EXTC (External Clock Source) = 00 = */ + /* */ + /* The BRG input clock comes from the BRGCLK */ + /* */ + /* - ATB (AutoBaud) = 0 = Normal operation of the BRG. */ + /* */ + /* - CD (Clock Divider) = 0x6C = 108 decimal = */ + /* */ + /* The input frequency is 1.03125 Mhz Dividing it by 107 will give */ + /* 9.638 Khz. However 1 must be added to the count value because it */ + /* counts down to 0. So the programmed value is 108. */ + /* */ + /* PF edit - changed CD = 0x1A = 26 ==> baud rate of 4 * 9600 = 38400 */ + /* - DIV16 (Divide-by-16) = 0 = divide by 1. */ + /*----------------------------------------------------------------------*/ + + // IMM->brgs_brgc1 = 0x000100D6; + //IMM->brgs_brgc1 = 0x00010034; /* Attempt to get 38400 baud */ + // IMM->brgs_brgc1 = 0x00010022; /* Attempt to get 57600 baud */ + //IMM->brgs_brgc1 = 0x00010010; /* Attempt to get 115200 baud */ + IMM->brgs_brgc1 = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1); + + /*----------------------------------------------------------------------*/ + /* Program the CMX SCC Route Register (CMXSCR). */ + /* */ + /* - GR1 (Grant support of SCC1) = 0 = */ + /* */ + /* SCC1 transmitter does not support the grant mechanism. The grant */ + /* is always asserted internally. */ + /* */ + /* - SC1 (SCC1 connection) = 0 */ + /* */ + /* SCC1 is not connected to the TSA of the SIs but is connected */ + /* directly to the NMSIx pins. */ + /* */ + /* - RS1CS (Receive SCC1 or clock source) = 000 = */ + /* */ + /* SCC1 receive clock is BRG1. */ + /* */ + /* - TS1CS (Transmit SCC1 clock source) = 000 = */ + /* */ + /* SCC1 transmit clock is BRG1. */ + /* */ + /* - GR2 (Grant support of SCC2) = 0 = */ + /* */ + /* SCC1 transmitter does not support the grant mechanism. The grant */ + /* is always asserted internally. */ + /* */ + /* - SC2 (SCC2 connection) = 0 */ + /* */ + /* SCC2 is not connected to the TSA of the SIs but is connected */ + /* directly to the NMSIx pins. */ + /* */ + /* - RS2CS (Receive SCC2 or clock source) = 001 = */ + /* */ + /* SCC1 receive clock is BRG2. */ + /* */ + /* - TS2CS (Transmit SCC2 clock source) = 001 = */ + /* */ + /* SCC2 transmit clock is BRG2. */ + /* */ + /* - GR3 (Grant support of SCC3) = 0 = */ + /* */ + /* SCC3 transmitter does not support the grant mechanism. The grant */ + /* is always asserted internally. */ + /* */ + /* - SC3 (SCC3 connection) = 0 */ + /* */ + /* SCC3 is not connected to the TSA of the SIs but is connected */ + /* directly to the NMSIx pins. */ + /* */ + /* - RS3CS (Receive SCC3 or clock source) = 010 = */ + /* */ + /* SCC3 receive clock is BRG3. */ + /* */ + /* - TS3CS (Transmit SCC3 clock source) = 010 = */ + /* */ + /* SCC3 transmit clock is BRG3. */ + /* */ + /* - GR4 (Grant support of SCC4) = 0 = */ + /* */ + /* SCC4 transmitter does not support the grant mechanism. The grant */ + /* is always asserted internally. */ + /* */ + /* - SC4 (SCC4 connection) = 0 */ + /* */ + /* SCC4 is not connected to the TSA of the SIs but is connected */ + /* directly to the NMSIx pins. */ + /* */ + /* - RS4CS (Receive SCC4 or clock source) = 011 = */ + /* */ + /* SCC4 receive clock is BRG4. */ + /* */ + /* - TS4CS (Transmit SCC4 clock source) = 011 = */ + /* */ + /* SCC4 transmit clock is BRG4. */ + /* */ + /*----------------------------------------------------------------------*/ + + IMM->cpm_mux_cmxscr = 0x0009121B; + +} /* end of ConfigSCC1Clock() */ + + + +/*-------------------------------------------------------------------------- +* +* FUNCTION NAME: InitParallelPorts +* +* DESCRIPTION: +* +* This function programs the parallel port configuration registers to +* utilize the pins required for proper SCC1 operation. The pins programmed +* here are TxD and RxD for SCC1 and CD1 for SCC1. +* +* EXTERNAL EFFECTS: Parallel Port C and D Configuration Registers +* +* PARAMETERS: +* +* RETURNS: Nothing +* +*--------------------------------------------------------------------------*/ + +void InitParallelPorts() + +{ + /*--------------------------------------------*/ + /* Program the Port Special Options Registers */ + /*--------------------------------------------*/ + + IMM->io_regs[PORT_C].psor &= 0xFFFDFFFF; /* CD/ pin 14 */ + IMM->io_regs[PORT_D].psor &= 0xFFFFFFFC; /* clear first */ + IMM->io_regs[PORT_D].psor |= 0x00000002; /* TXD pin 30| RXD pin 31 */ + + /*-------------------------------------------*/ + /* Program the Port Pin Assignment Registers */ + /*-------------------------------------------*/ + + IMM->io_regs[PORT_C].ppar |= 0x00020000; /* CD/ pin 14 */ + IMM->io_regs[PORT_D].ppar |= 0x00000003; /* TXD pin 30| RXD pin 31 */ + + /*-------------------------------------------*/ + /* Program the Port Data Direction Registers */ + /*-------------------------------------------*/ + + IMM->io_regs[PORT_C].pdir &= 0xFFFDFFFF; /* CD/ pin 14 */ + IMM->io_regs[PORT_D].pdir &= 0xFFFFFFFC; /* clear first */ + IMM->io_regs[PORT_D].pdir |= 0x00000002; /* TXD pin 30| RXD pin 31 */ + + /*---------------------------------------*/ + /* Program the Port Open-Drain Registers */ + /*---------------------------------------*/ + + IMM->io_regs[PORT_C].podr &= 0xFFFDFFFF; /* CD/ pin 14 */ + IMM->io_regs[PORT_D].podr &= 0xFFFFFFFC; /* TXD pin 30| RXD pin 31 */ + +} + +/*--------------------------------------------------------------------------- +* +* FUNCTION NAME: BDRxError +* +* DESCRIPTION: +* +* Return TRUE if Buffer Descriptor Status bd_cstatus indicates Receive +* Error; Return FALSE otherwise note Receive Errors are as follows: +* +* 0x80: DPLL Error (DE) +* 0x20: Length Violation (LG) +* 0x10: Non-Octet Aligned (NO) +* 0x8: Rx Abort Sequence (AB) +* 0x4: Rx CRC Error (CR) +* 0x2: Overrun (OV) +* 0x1: Carrier Detect Lost (CD) +* +* EXTERNAL EFFECTS: None +* +* PARAMETERS: +* +* bd_cstatus +* +* RETURNS: TRUE if there was an error and FALSE if there wasn't +* +*---------------------------------------------------------------------------*/ + +CYG_WORD16 BDRxError(CYG_WORD16 bd_cstatus) + +{ + + if (bd_cstatus & BD_RX_ERROR) + + return true; + + else + + return false; + +} /* end BDRxError */ + +/*--------------------------------------------------------------------------- +* +* FUNCTION NAME: SCC1Poll +* +* DESCRIPTION: Poll SCC1 RxBD and check to see if a character was received +* +* EXTERNAL EFFECT: NONE +* +* PARAMETERS: NONE +* +* RETURNS: A one if there is a character available in the receive buffer, +* else zero. +* +*--------------------------------------------------------------------------*/ + +cyg_uint8 SCC1Poll(void) + +{ + + if(RxTxBD->RxBD.bd_cstatus & 0x8000) + + { + return 0; /* character NOT available */ + } + + else + + { + return 1; /* character IS available */ + } + +} /* END SCC1Poll */ + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +void +cyg_hal_plf_serial_putc(cyg_uint8 ch) +#else +static void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch) +#endif +{ + /*-----------------------------------*/ + /* Loop until transmission completed */ + /*-----------------------------------*/ +#if 1 + volatile CYG_WORD16 stat = 1; + while (stat){ + stat = RxTxBD->TxBD.bd_cstatus & 0x8000; + } +#else + while (RxTxBD->TxBD.bd_cstatus & 0x8000); +#endif + /*------------*/ + /* Store data */ + /*------------*/ + + *(RxTxBD->TxBD.bd_addr) = ch; + RxTxBD->TxBD.bd_length = 1; + + /*---------------*/ + /* Set Ready bit */ + /*---------------*/ + + RxTxBD->TxBD.bd_cstatus |= 0x8000; + +} + + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_bool retval; + + if ( (retval = SCC1Poll() ) ){ /* Check BD status for Rx characters */ + *ch = cyg_hal_plf_serial_getc(__ch_data); + } + + return retval; +} + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +cyg_uint8 +cyg_hal_plf_serial_getc(void) +#else +static cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +#endif +{ + cyg_uint8 ch; + /*--------------------*/ + /* Loop if RxBD empty */ + /*--------------------*/ +#if 1 + volatile short stat = 1; + while (stat){ + stat = RxTxBD->RxBD.bd_cstatus & 0x8000; + } +#else + while (RxTxBD->RxBD.bd_cstatus & 0x8000); +#endif + /*--------------*/ + /* Receive data */ + /*--------------*/ + + ch = *(RxTxBD->RxBD.bd_addr); + + /*----------------------*/ + /* Set Buffer Empty bit */ + /*----------------------*/ + + RxTxBD->RxBD.bd_cstatus |= 0x8000; + + return ch; +} + + + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + //CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + cyg_hal_plf_serial_putc(*__buf++); +#else + cyg_hal_plf_serial_putc(__ch_data, *__buf++); +#endif + + //CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + *__buf++ = cyg_hal_plf_serial_getc(); +#else + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); +#endif + CYGARC_HAL_RESTORE_GP(); +} + +cyg_int32 msec_timeout = 1000; + +static cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count = msec_timeout * 10; // delay in .1 ms steps + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + int ret = 0; + cyg_uint32 regval; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + //HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_CPM_SMC1); + // For now, don't bother calling a macro, just do it here + // Bit 8 in the SIMR_L corresponds to SCC1 + HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + regval |= 0x00800000; + + HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + asm volatile ("ori %0, 0, 0x1234;" \ + : /* No output */ \ + : "I" (22)); /* %0 ==> r2 */ + + //RxTxBD->RxBD.bd_cstatus = 0xB000; + irq_state = 1; + //RED_LED_ON; + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + //HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_CPM_SMC1); + HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + regval &= 0xFF7FFFFF; + + HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval); + //RED_LED_OFF; + //RxTxBD->RxBD.bd_cstatus = 0xA000; + break; + case __COMMCTL_DBG_ISR_VECTOR: + //ret = CYGNUM_HAL_INTERRUPT_CPM_SMC1; + ret = CYGNUM_HAL_INTERRUPT_SCC1; + + //ret = 0x01; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = msec_timeout; + msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +// EOF hal_aux.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/src/var_intr.c @@ -0,0 +1,65 @@ +//========================================================================== +// +// var_intr.c +// +// PowerPC variant interrupt handlers +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors: jskov +// Date: 2001-12-11 +// Purpose: PowerPC variant interrupt handlers +// Description: This file contains code to handle interrupt related issues +// on the PowerPC variant. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +externC void +hal_variant_IRQ_init(void) +{ + // No special init required for 60x series. +} + +// ------------------------------------------------------------------------- +// EOF var_intr.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/src/var_misc.c @@ -0,0 +1,179 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors: jskov +// Date: 2001-12-12 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/ppc_regs.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_mem.h> + +//-------------------------------------------------------------------------- +void hal_variant_init(void) +{ +} + + +//-------------------------------------------------------------------------- +// Variant specific idle thread action. +bool +hal_variant_idle_thread_action( cyg_uint32 count ) +{ + // Let architecture idle thread action run + return true; +} + +//--------------------------------------------------------------------------- +// Use MMU resources to map memory regions. +// Takes and returns an int used to ID the MMU resource to use. This ID +// is increased as resources are used and should be used for subsequent +// invocations. +int +cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, + cyg_int32 size, cyg_uint8 flags) +{ + // Use BATs to map the memory. + cyg_uint32 ubat, lbat; + + ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; + lbat = (phys & LBAT_BRPNMASK); + if (flags & CYGARC_MEMDESC_CI) + lbat |= LBAT_I; + if (flags & CYGARC_MEMDESC_GUARDED) + lbat |= LBAT_G; +#define IWASPATRICK +#ifdef IWASPATRICK + lbat |= LBAT_PP_RW; // Always enable for Read-Write +#else + if (flags & CYGARC_MEMDESC_RO) // Memory is Read Only + lbat |= LBAT_PP_RO; + if (flags & CYGARC_MEMDESC_RW) // Memory is RW + lbat |= LBAT_PP_RW; +#endif + // There are 4 BATs, size is programmable. + while (id < 4 && size > 0) { + cyg_uint32 blk_size = 128*1024; + cyg_uint32 bl = 0; + while (blk_size < 256*1024*1024 && blk_size < size) { + blk_size *= 2; + bl = (bl << 1) | 1; + } + ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); + + switch (id) { + case 0: + CYGARC_MTSPR (IBAT0U, ubat); + CYGARC_MTSPR (IBAT0L, lbat); + CYGARC_MTSPR (DBAT0U, ubat); + CYGARC_MTSPR (DBAT0L, lbat); + break; + case 1: + CYGARC_MTSPR (IBAT1U, ubat); + CYGARC_MTSPR (IBAT1L, lbat); + CYGARC_MTSPR (DBAT1U, ubat); + CYGARC_MTSPR (DBAT1L, lbat); + break; + case 2: + CYGARC_MTSPR (IBAT2U, ubat); + CYGARC_MTSPR (IBAT2L, lbat); + CYGARC_MTSPR (DBAT2U, ubat); + CYGARC_MTSPR (DBAT2L, lbat); + break; + case 3: + CYGARC_MTSPR (IBAT3U, ubat); + CYGARC_MTSPR (IBAT3L, lbat); + CYGARC_MTSPR (DBAT3U, ubat); + CYGARC_MTSPR (DBAT3L, lbat); + break; + } + + size -= blk_size; + id++; + } + + return id; +} + + +// Initialize MMU to a sane (NOP) state. +void +cyg_hal_clear_MMU (void) +{ + cyg_uint32 ubat, lbat; + + // Initialize BATs with 0 -- VS&VP are unset, making all matches fail + ubat = 0; + lbat = 0; + + CYGARC_MTSPR (IBAT0U, ubat); + CYGARC_MTSPR (IBAT0L, lbat); + CYGARC_MTSPR (DBAT0U, ubat); + CYGARC_MTSPR (DBAT0L, lbat); + CYGARC_MTSPR (IBAT1U, ubat); + CYGARC_MTSPR (IBAT1L, lbat); + CYGARC_MTSPR (DBAT1U, ubat); + CYGARC_MTSPR (DBAT1L, lbat); + CYGARC_MTSPR (IBAT2U, ubat); + CYGARC_MTSPR (IBAT2L, lbat); + CYGARC_MTSPR (DBAT2U, ubat); + CYGARC_MTSPR (DBAT2L, lbat); + CYGARC_MTSPR (IBAT3U, ubat); + CYGARC_MTSPR (IBAT3L, lbat); + CYGARC_MTSPR (DBAT3U, ubat); + CYGARC_MTSPR (DBAT3L, lbat); +} + +//-------------------------------------------------------------------------- +// End of var_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mpc8260/current/src/variant.S @@ -0,0 +1,87 @@ +##============================================================================= +## +## variant.S +## +## PowerPC MPC8260 variant code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): pfine +## Contributors:jskov +## Date: 2001-12-12 +## Purpose: PowerPC MPC8260 variant code +## Description: Variant specific code for PowerPC MPC8260 CPUs. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/variant.inc> + +#--------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + + .data + + .extern hal_default_decrementer_isr + .extern hal_default_isr + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_decrementer_isr + .rept CYGNUM_HAL_ISR_COUNT-1 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept CYGNUM_HAL_ISR_COUNT + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of variant.S +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/ChangeLog @@ -0,0 +1,61 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/ts6.S: + * src/hal_diag.c: + * src/hal_aux.c: + * misc/redboot_ROMRAM.ecm: + * misc/redboot_ROM.ecm: + * misc/redboot_RAM.ecm: + * include/pkgconf/mlt_powerpc_ts6_romram.ldi: + * include/pkgconf/mlt_powerpc_ts6_romram.h: + * include/pkgconf/mlt_powerpc_ts6_romlow.ldi: + * include/pkgconf/mlt_powerpc_ts6_romlow.h: + * include/pkgconf/mlt_powerpc_ts6_romhigh.ldi: + * include/pkgconf/mlt_powerpc_ts6_romhigh.h: + * include/pkgconf/mlt_powerpc_ts6_rom.mlt: + * include/pkgconf/mlt_powerpc_ts6_ram.mlt: + * include/pkgconf/mlt_powerpc_ts6_ram.ldi: + * include/pkgconf/mlt_powerpc_ts6_ram.h: + * include/plf_stub.h: + * include/plf_intr.h: + * include/plf_cache.h: + * include/hal_diag.h: + * cdl/hal_powerpc_ts6.cdl: New package - support for Delphi + Communications TS6 board. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/cdl/hal_powerpc_ts6.cdl @@ -0,0 +1,377 @@ +# ==================================================================== +# +# hal_powerpc_ts6.cdl +# +# Delphi Communications TS6 board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): wpd, pfine +# Original data: hmt +# Contributors: +# Date: 2002-02-27 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_POWERPC_TS6 { + display "MPC8260 TS6 board" + parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_MPC8260 + define_header hal_powerpc_ts6.h + include_dir cyg/hal + description " + The TS6 HAL package provides the support needed to run + eCos on the MPC8260 micro controller portion of the + Delphi Communication Systems TS6 board." + + compile hal_diag.c hal_aux.c ts6.S + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + requires { CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP == 0 } + requires { CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP == 0 } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8260.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts6.h>" + + puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC MPC8260\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"TS6\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + This option is used to control where the application program will + run, either from RAM or ROM (flash) memory. ROM based applications + must be self contained, while RAM applications will typically assume + the existence of a debug environment, such as GDB stubs." + + cdl_option DCSPRI_HAL_TS6_ROM_MLT { + display "Memory Layout for ROM Startup" + flavor data + legal_values {"LOW" "HIGH" "RAM"} + default_value {"HIGH"} + description " + + This option selects which memory layout file should be + used when configuring the TS6 board for ROM startup. + The LOW option selects the memory layout for an image + stored at the beginning of the FLASH. It should be + used when the (hard reset) IP and boot memory space + are both mapped to address 0. + + NOTE: support for the LOW option has not been implemented. + + The HIGH option selects the memory layout for an image + stored in the last Megabyte of FLASH. It should be + used when the (hard reset) IP maps the interrupt + vector base address to 0xFFF00000 and the boot memory + space to the last 32 Megabytes of FLASH. + + The RAM option is a hack used to place the ROM image + in RAM in order to simplify the development of a ROM + monitor by using the existing ROM monitor to load it + into RAM, but pretend like it is in ROM." + } + + } + + cdl_option CYGHWR_HAL_POWERPC_DISABLE_MMU { + display "DISABLE MMU" + flavor bool + default_value 0 + # calculated 0 + description " + This option will disable the MMU enabled." + } + + cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED { + display "Development board clock speed (MHz)" + flavor data + legal_values 45 60 66 + default_value 60 + description " + The Delphi MPC8260 TigerSHARC-6 board has a 60 MHz crystal." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + description " + Period is busclock/4/CYGNUM_HAL_RTC_DENOMINATOR. VERIFY THIS!!!" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + description " + This option selects the number of system clock 'ticks' + per second. This rate is sometimes known as the heartbeat rate." + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated { (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/4)/CYGNUM_HAL_RTC_DENOMINATOR) } + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "powerpc-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=603e -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=603e -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the platform CDL takes care of creating + an S-Record data file. -- This needs more work" + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec --srec-forceS3 $< $(@:.bin=.s19) + $(OBJCOPY) -O binary $< $@ +# } +# Changed the .srec extentsion to .txt for ease of downloading with hyperterm +# Changed the .txt extentsion to .s19 for ease of downloading with OCD + } + } + + cdl_component CYGPKG_HAL_POWERPC_TS6_OPTIONS { + display "MPC8260 TS6 build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_POWERPC_TS6_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the TS6 HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_POWERPC_TS6_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the TS6 HAL. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_ts6_ram" : \ + "powerpc_ts6_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_ts6_ram.ldi>" : \ + DCSPRI_HAL_TS6_ROM_MLT == "LOW" ? "<pkgconf/mlt_powerpc_ts6_romlow.ldi>" : \ + DCSPRI_HAL_TS6_ROM_MLT == "HIGH" ? "<pkgconf/mlt_powerpc_ts6_romhigh.ldi>" : \ + "<pkgconf/mlt_powerpc_ts6_romram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_ts6_ram.h>" : \ + DCSPRI_HAL_TS6_ROM_MLT == "LOW" ? "<pkgconf/mlt_powerpc_ts6_romlow.h>" : \ + DCSPRI_HAL_TS6_ROM_MLT == "HIGH" ? "<pkgconf/mlt_powerpc_ts6_romhigh.h>" : \ + "<pkgconf/mlt_powerpc_ts6_romram.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor bool + default_value { (CYG_HAL_STARTUP == "RAM" && + !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS && + !CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED && + !CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + requires ! CYGSEM_HAL_POWERPC_COPY_VECTORS + requires ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED + description " + Allow coexistence with ROM monitor (CygMon or GDB stubs) by + only initializing interrupt vectors on startup, thus leaving + exception handling to the ROM monitor." + } + + + # FIXME: the option above should be adjusted to select between monitor + # variants + cdl_option CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs { + parent CYGPKG_HAL_ROM_MONITOR + display "Bad CDL workaround" + calculated 1 + active_if CYGSEM_HAL_USE_ROM_MONITOR + } + + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + +# compile -library=libextras.a redboot_cmds.c + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming. + This needs more work." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O srec --change-address=0x02040000 $< $(@:.bin=.ppcbug) + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/hal_diag.h @@ -0,0 +1,110 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 1998-03-02 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +// These should not need to be prototyped here, but where???? +cyg_uint8 +cyg_hal_plf_serial_getc(void); + +#if 1 +void +cyg_hal_plf_serial_putc(cyg_uint8 ch); +#else +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); +#endif + +void +cyg_hal_plf_serial_init(void); +#endif //#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_ram.h @@ -0,0 +1,37 @@ +// eCos memory layout - Fri Oct 20 10:35:23 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_for_rom) []; +#endif +#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom)) +#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x1cd00) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x04000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_ram.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:35:23 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00020000, LENGTH = 0x04000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x1cd00; + SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_ram.mlt @@ -0,0 +1,17 @@ +version 0 +region ram 0 2000000 0 ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table ! +section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom ! +section reserved_for_rom 1cd00 10 0 0 0 1 0 1 vectors vectors ! +section vectors 0 10 0 1 0 1 0 1 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_rom.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 2000000 0 ! +section vectors 0 1 0 1 1 0 1 0 0 0 ! +section reserved_vsr_table 200 1 0 0 1 1 1 1 3000 3000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romhigh.h @@ -0,0 +1,30 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xff800000) +#define CYGMEM_REGION_rom_SIZE (0x00800000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) + +#if 0 +#define CYGMEM_SECTION_heap1_SIZE (0x100000 - (size_t) CYG_LABEL_NAME (__heap1)) +#else // Attempt to make more RAM usable in RedBoot ROM version +#define CYGMEM_SECTION_heap1_SIZE (0x04000000 - (size_t) CYG_LABEL_NAME (__heap1)) +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romhigh.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x04000000 + rom : ORIGIN = 0xff800000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xfff00000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romlow.h @@ -0,0 +1,25 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xff800000) +#define CYGMEM_REGION_rom_SIZE (0x00800000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x04000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romlow.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x04000000 + rom : ORIGIN = 0xff800000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xff800000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romram.h @@ -0,0 +1,25 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x03000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x03f00000) +#define CYGMEM_REGION_rom_SIZE (0x00100000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x03000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/pkgconf/mlt_powerpc_ts6_romram.ldi @@ -0,0 +1,32 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x03000000 + rom : ORIGIN = 0x03F00000, LENGTH = 0x00100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0x03f00000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + CYG_LABEL_DEFN(__reserved_for_flash) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_for_flash) + 0xcd00; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/plf_cache.h @@ -0,0 +1,69 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform HAL cache details +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:jskov +// Date: 2002-02-27 +// Purpose: Platform cache control API +// Description: The macros defined here provide the platform specific +// cache control operations / behavior. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//--------------------------------------------------------------------------- +// Initial cache enabling +#ifdef CYGSEM_HAL_ROM_MONITOR +# define CYGPRI_INIT_CACHES +# define CYGPRI_ENABLE_CACHES +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/plf_intr.h @@ -0,0 +1,104 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// MPC8260 platform specific interrupt definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors: jskov +// Date: 2002-02-27 +// Purpose: Define platform specific interrupt support +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + + +//---------------------------------------------------------------------------- +// Reset. +/* This reset sequence will generate a checkstop reset + * It should probably live in mpc8260 variant directory, or be copied + * to the VADS directory. + */ +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + cyg_uint32 tmp0, tmp1; \ + cyg_uint32 *tmp2 = (cyg_uint32 *) 0x04710c94; \ + *tmp2 = 0x1; /* set RMR[CSRE] bit */ \ + asm volatile("lis %0, 0xB001;" /* tmp0 = 0xB0010000 */\ + "mtspr %2, %0;" /* HID0 = 0xB0010000, set HID0[EMCP] */\ + "isync;" /* paranoia */\ + "li %1, 0x0;" /* tmp0 = 0x0 */\ + "mfmsr %0;" /* tmp0 = MSR */\ + "rlwimi %0,%1,0,19,19;" /* */\ + "rlwimi %0,%1,0,26,27;" /* */\ + "mtmsr %0;" /* clear MSR[EE][IR][DR] */\ + "isync;" /* probably required here */\ + "lis %1, 0xF000;" /* tmp1 = 0xF0000000 */\ + "eieio;" /* paranoia */\ + "lwz %0,0(%1);" /* Attempt to access illegal memory. */\ + : "=r" (tmp0), "=r" (tmp1)\ + : "I" (CYGARC_REG_HID0));\ + CYG_MACRO_END + +// FIXME - What about the LOWROM configuarion ? +#ifdef DCSPRI_HAL_TS6_ROM_MLT_RAM +#define HAL_PLATFORM_RESET_ENTRY 0x00000100 +#else +#define HAL_PLATFORM_RESET_ENTRY 0xFFF00100 +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/include/plf_stub.h @@ -0,0 +1,87 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:jskov +// Date: 2001-11-29 +// Purpose: Platform HAL stub support for TS6 board +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_powerpc_ts6.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/ppc_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +externC int wpd_stub_get_char(void); +externC void wpd_stub_put_char(int); +#define HAL_STUB_PLATFORM_GET_CHAR cyg_hal_plf_serial_getc +#define HAL_STUB_PLATFORM_PUT_CHAR cyg_hal_plf_serial_putc + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/misc/redboot_RAM.ecm @@ -0,0 +1,98 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ts6 ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_TS6 current ; + package -hardware CYGPKG_DEVS_ETH_POWERPC_QUICC2 current ; + package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_TS6 current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED { + user_value 60 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "DCS Version 1.16" +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00040000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0x700000 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 { + user_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/misc/redboot_ROM.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ts6 ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_TS6 current ; + package -hardware CYGPKG_DEVS_ETH_POWERPC_QUICC2 current ; + package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_TS6 current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "DCS Version 1.16" +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00040000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0x700000 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x40000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 { + user_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/misc/redboot_ROMRAM.ecm @@ -0,0 +1,105 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ts6 ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_TS6 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_TS6 current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_DEVS_ETH_POWERPC_QUICC2 current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option DCSPRI_HAL_TS6_ROM_MLT { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00040000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0x00700000 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 { + user_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/src/hal_aux.c @@ -0,0 +1,178 @@ +//============================================================================= +// +// hal_aux.c +// +// HAL auxiliary objects and code; per platform +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:hmt +// Date: 2002-02-27 +// Purpose: HAL aux objects: startup tables. +// Description: Tables for per-platform initialization +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_mem.h> // HAL memory definitions +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> // hal_if_init +#include <cyg/hal/hal_io.h> // hal_if_init +#include <cyg/hal/hal_misc.h> // cyg_hal_is_break + +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/mpc8260.h> // Needed for IMMR structure + +// The memory map is weakly defined, allowing the application to redefine +// it if necessary. The regions defined below are the minimum requirements. +CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = { + // Mapping for the Motorola MPC8260 development board + CYGARC_MEMDESC_CACHE( 0x00000000, 0x04000000 ), // Main memory 60x SDRAM + // Mapping for the FPGA and the MPC8260 Internal memory + CYGARC_MEMDESC_NOCACHE( 0x04500000, 0x00400000 ), + // Mapping for the Cluster Bus + CYGARC_MEMDESC_NOCACHE( 0xE0000000, 0x10000000 ), + // Mapping for the FLASH + CYGARC_MEMDESC_NOCACHE( 0xff800000, 0x00800000 ), // ROM region + + CYGARC_MEMDESC_TABLE_END +}; + + +/***********************/ +/* Global Declarations */ +/***********************/ +//#define USE_SMC1 + +volatile t_PQ2IMM *IMM; /* IMM base pointer */ + +// Define some space in high SDRAM that I can use for debugging +#define nPFDEBUG +#ifdef PFDEBUG +cyg_uint32 *dbg_values = (cyg_uint32 *) 0x00FFFF00; +#endif + +//-------------------------------------------------------------------------- +// Platform init code. +void +hal_platform_init(void) +{ + +// Ports and Pins assigned for General Purpose I/O +// PORT PIN(s) DIR (I/O) Name Init Value Comment +//------------------------------------------------------------------- +// A 30-31 TBD TBD Wires to RF Board +// A 29 O TS_RESET_L 0 Tiger Sharc Reset +// A 28 O LP_ENB_L 1 Link Port Buffer Enable +// A 26-27 TBD TBD Wires to RF Board +// A 18-23 TBD TBD Wires to each Tiger Sharc +// A 12-17 O xxxxxxxxxx 0 Tiger Sharc Interrupt +// B 4-7 O xxxxxxxxxx TBD User controlled LEDs +// C 8 I xxxxxxxxxx xxx RF Board Interrupt +// C 6 I xxxxxxxxxx xxx FPGA Interrupt +// C 0-5 I xxxxxxxxxx xxx TSn Interrupt +// D 20 ? PPC_WAIT TBD Open Drain == High Z +// D 7-9 O CIMP 0-2 110 TS Impedance ctrl +// D 4-6 O DS 0-2 100 TS Drive Strength + + +// Ports and Pins assigned for Dedicated Pin Assignment +// PORT PIN(s) DIR (I/O) Name Init Value Comment +//------------------------------------------------------------------- +// D 16-19 x TBD SPI to RF Board +// D 14-15 x TBD I2C + + + +#define TS6_PPARA_INIT_MASK 0xFFF00000 +#define TS6_PDIRA_INIT_MASK 0x3003F000 +#define TS6_PDATA_INIT_MASK 0x1003F000 + IMM = (t_PQ2IMM *)0x04700000; /* MPC8260 internal register map */ + + /*-------------------------------------------*/ + /* Program the Port Pin Registers */ + /*-------------------------------------------*/ + + IMM->io_regs[PORT_A].ppar &= 0xFFF00000; /* Clear bits for GPIO */ + IMM->io_regs[PORT_A].pdir |= 0x000FC00C; /* Set bits on outputs */ + IMM->io_regs[PORT_A].pdat |= 0x00000008; /* Set high outputs bits */ + IMM->io_regs[PORT_A].pdat &= 0xFFF03FFB; /* Clear low output bits */ + +// Initialize Port B Pins 4,5,6,7 general purpose IO +// Pin == 0 ==> LED on +// Pin 4 LED 18, Red +// Pin 5 LED 18, Green +// Pin 6 LED 17, Red +// Pin 7 LED 17, Green + IMM->io_regs[PORT_B].ppar &= 0xF0FFFFFF; /* Clear 4-7 */ + IMM->io_regs[PORT_B].pdir |= 0x0F000000; /* Set 4-7 as outputs */ + IMM->io_regs[PORT_B].pdat |= 0x0F000000; /* Clear LED's */ + IMM->io_regs[PORT_B].pdat &= 0xFDFFFFFF; /* Set LED's 17 to green */ + + IMM->io_regs[PORT_C].ppar &= 0x007FFFFF; /* Clear 0 -8 */ + IMM->io_regs[PORT_C].pdir &= 0x007FFFFF; /* Configure as inputs */ + //IMM->io_regs[PORT_C].podr &= 0xFF800000; /* Configure as inputs */ + + IMM->io_regs[PORT_D].ppar &= 0xF03FF7FF; + IMM->io_regs[PORT_D].pdir |= 0x0FC00000; + IMM->io_regs[PORT_D].podr |= 0x00000800; + IMM->io_regs[PORT_D].pdat |= 0x09800000; + + // Dedicated Pin assignments for SPI + IMM->io_regs[PORT_D].ppar |= 0x0000F000; + IMM->io_regs[PORT_D].podr &= 0xFFFF0FFF; + IMM->io_regs[PORT_D].pdir |= 0x0000F000; + + +#ifdef PFDEBUG + int i; + for(i = 0; i < 20;i++) + dbg_values[i] = 0; +#endif +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif + +} +// EOF hal_aux.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/src/hal_diag.c @@ -0,0 +1,292 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:hmt, jskov +// Date: 2002-02-27 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt macros + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/mpc8260.h> + +// This prototype probably needs to be in an include file +void +cyg_hal_plf_serial_init(void); + + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + +/* This is where I will put the SCC1 initialization code */ + cyg_hal_plf_serial_init(); +} + + +#ifdef LATER +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +//----------------------------------------------------------------------------- +// Select default diag channel to use + +//#define CYG_KERNEL_DIAG_ROMART +//#define CYG_KERNEL_DIAG_SERIAL + +#if !defined(CYG_KERNEL_DIAG_SERIAL) +#define CYG_KERNEL_DIAG_SERIAL +#endif + +#ifdef CYGDBG_DIAG_BUF +// Keep diag messages in a buffer for later [re]display + +int enable_diag_uart = 1; +int enable_diag_buf = 1; +static char diag_buf[40960*4]; +static int diag_buf_ptr = 0; + +static void +diag_putc(char c) +{ + if (enable_diag_buf) { + diag_buf[diag_buf_ptr++] = c; + if (diag_buf_ptr == sizeof(diag_buf)) diag_buf_ptr--; + } +} + +void +dump_diag_buf(int start, int len) +{ + int i; + enable_diag_uart = 1; + enable_diag_buf = 0; + if (len == 0) len = diag_buf_ptr; + diag_printf("\nDiag buf\n"); + for (i = start; i < len; i++) { + hal_diag_write_char(diag_buf[i]); + } +} +#endif // CYGDBG_DIAG_BUF + + +//----------------------------------------------------------------------------- +// MBX board specific serial output; using GDB protocol by default: + + +#if defined(CYG_KERNEL_DIAG_SERIAL) + +t_PQ2IMM *IMM; + +void hal_diag_init(void) +{ + static int init = 0; + if (init) return; + init++; + + // hardwired base + //eppc = eppc_base(); + IMM = (t_PQ2IMM *) 0x04700000; + + // init the actual serial port + cyg_hal_plf_serial_init_channel(); +#ifdef CYGSEM_HAL_DIAG_MANGLER_GDB +#ifndef CYG_HAL_STARTUP_ROM + // We are talking to GDB; ack the "go" packet! + cyg_hal_plf_serial_putc('+'); +#endif +#endif +} + +void hal_diag_write_char_serial( char c ) +{ + unsigned long __state; + HAL_DISABLE_INTERRUPTS(__state); + cyg_hal_plf_serial_putc(c); + HAL_RESTORE_INTERRUPTS(__state); +} + +#if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN) +void hal_diag_write_char(char c) +{ +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + hal_diag_write_char_serial(c); +} + +#else // RAM start so encode for GDB + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + +#ifndef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + // only gobble characters if no interrupt handler to grab ^Cs + // is installed (which is exclusive with device driver use) + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + c = cyg_hal_plf_serial_getc(eppc); + + if( c == '+' ) + break; // a good acknowledge +#if 0 + if( c1 == 3 ) { + // Ctrl-C: breakpoint. + breakpoint(); + break; + } +#endif + // otherwise, loop round again +#else + break; +#endif + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + + } +} +#endif // NOT def CYG_HAL_STARTUP_ROM + +#if 0 +// These should not need to be prototyped here, but where???? +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data); + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); +#endif + +void hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(); +} + +#endif // CYG_KERNEL_DIAG_SERIAL + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG +#endif + +// EOF hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/ts6/current/src/ts6.S @@ -0,0 +1,1598 @@ +#============================================================================== +## +## ts6.S +## +## MPC8260 TS6 board hardware setup +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): pfine, wpd +## Contributors: nickg +## Date: 2002-02-27 +## Purpose: TigerSHARC-6 board hardware setup +## Description: This file contains any code needed to initialize the +## hardware on the Delphi TigerSHARC-6 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/arch.inc> +#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */ +#------------------------------------------------------------------------------ + + .globl hal_hardware_init +hal_hardware_init: +// It is possible that the board may experience a soft reset, which +// will cause this hal_hardware_init routine to be called. As a +// result of the soft reset, the IMMR, memory controller, system +// protection logic, interrupt controller and parallel I/O pins are +// NOT reset (MPC8260 User Manual p 5-2), and therefor we do not want to +// run the setup in this routine. Luckily, a hard reset will clear +// the NHR bit (bit 15) of the HID0 register. We will check for this bit +// to be 0 (implying a hard reset). If it is 0, we will run the +// initialization. If non-zero, we will skip the initialization. +// +// If we do the initialization, then we must set the NHR bit so that +// next time we hit this point in the routine, we can determine the type +// of reset. + + mfspr r22,CYGARC_REG_HID0 # Get contents of HID0 + rlwinm r23,r22,0,15,15 #shift HID0 by 0, mask with 0x10000, store in r23 + cmpwi r23,0 # Compare r23 with 0 + bne hardware_init_done + + mfspr r31,CYGARC_REG_LR + + + #---------------------------------------------- + # Load the IMMR register with the base address + #---------------------------------------------- + + addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We add + # 0x10000 because using relative addressing + # in load and store instructions only allow a + # offset from the base of +/-32767. + addis r5,0,0x0470 + + addis r3,0,0x0F01 + +# The default IMMR base address was 0x0F0000000 as +# originally programmed into the Hard Reset +# Configuration Word. + stw r5,CYGARC_REG_IMM_IMMR(r3) + + + + mfspr r21,CYGARC_REG_HID0 # get HID0 in R21 + oris r21,r21,0x1 # Set bit 15 of HID0 (NHR) + + mtspr CYGARC_REG_HID0,r21 # load HID0 with NHR set + + + #******************************************* + # Main System Clock Configuration Registers + #******************************************* + + #------------------------------------------------------------------------- + # We only need to program the System Clock Control Register (SCCR). The + # System Clock Mode Register (SCMR) doesn t need to be programmed here + # because the MODCLK_HI bits in the Hard Reset Configuration Word and the + # MODCK pins dictate the values in the SCCR during power-on reset. + #------------------------------------------------------------------------- + + #------------------------------------------------------------------------- + # Program the System Clock Control Register (SCCR). + # + # - Bits 0 - 28 Reserved. Clear to 0. + # + # - CLPD (CPM Low Power Disable) = 0 = + # + # CPM does not enter low power mode when the core enters low power + # mode. + # + # - DFBRG (Division Factor of BRGCLK) = 01 - Divide by 8. + # + #------------------------------------------------------------------------- + + + addis r3,0,0x0000 + ori r3,r3,0x0001 # SCCR = 0x00000001 + stw r3,CYGARC_REG_IMM_SCCR(r4) + + #~~~~~~~~~~~~~~~~~~~~ + # Initialize the SIU + #~~~~~~~~~~~~~~~~~~~~ + + bl init_siu + + #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + # Initialize the memory controller and SDRAM + #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + bl init_memc + + mtspr CYGARC_REG_LR,r31 # restore original Link Register value + +hardware_init_done: + +#define nFLASH_LEDS_FOREVER +#ifdef FLASH_LEDS_FOREVER + bl init_user_leds + b flash_leds_forever +#endif +#if 0 + b memory_test +#endif + + + bclr 20,0 + + +######################################################################### +# Function: init_siu +# +# Description: Initializes the System Interface Unit +# +# History: +# +# +######################################################################### + +init_siu: + + #----------------------------------------------------------------------- + # Program the System Protection Control Register with the following + # values: + # + # - SWTC (Software Watchdog Timer Count) = 0xFFFF = programmed to max + # count value. + # + # - BMT (Bus Monitor Timing) = 0xFF = Set to max timeout period. + # + # - PBME (60x Bus Monitor Enable) = 1 = enabled. + # + # - LBME (Local Bus Monitor Enable) = 1 = enabled. + # + # - Bits 26-28 Reserved. Set to 0. + # + # - SWE (Software Watchdog Enabled) = 0 = disabled for now. User will + # have to enable this in a non-debug application. + # + # - SWRI (Software Watchdog Reset/Interrupt Select) = 1 = Software + # watchdog timeout or bus monitor time-out causes a soft reset. + # + # - SWP (Software Watchdog Prescale) = 1 = clock is prescaled. + #----------------------------------------------------------------------- + + addis r3,0,0xFFFF + ori r3,r3,0xFFC3 # SYPCR = 0xFFFFFFC3 + stw r3,CYGARC_REG_IMM_SYPCR(r4) + + + #------------------------------------------------------------------------- + # Program the Bus Configuration Register. The details are as follows: + # + # - EBM (External Bus Mode) = 0 = Single MPC8260 bus mode is assumed. + # + # - APD (Address Phase delay) = 001 = + # + # One address tenure wait states for address operations initiated by + # a 60x bus master. + # + # - L2C (Secondary Cache Controller) = 0 = No secondary cache controller + # is assumed. + # + # - L2D (L2 cache hit Delay) = 000 = This is a don t care because we re + # not using the L2 cache. + # + # - PLDP (PipeLine maximum Depth) = 0 = The pipeline max depth is one. + # + # - Bits 9-11 = Reserved. Set to 0. + # + # - ETM (Compatibility Mode enable) = 1 = Extended transfer mode is + # enabled. + # + # - LETM (Local Bus Compatibility Mode Enable) = 1 = + # + # Extended transfer mode is enabled on the local bus. + # + # - EPAR (Even Parity) = 0 = This is a do not care. + # + # - LEPAR (Local Bus Even Parity) = 0 = This is a do not care. + # + # - Bits 16-20 = Reserved. Set to 0. + # + # - EXDD (External Master Delay Disable) = 0 = + # + # The memroy controller inserts one wait state between the assertion + # of TS and the assertion of CS when an external master accesses an + # address space controlled by the memory controller. + # + # - Bits 22-26 = Reserved. Set to 0. + # + # - ISPS (Internal Space Port Size) = 0 = + # + # MPC8260 acts as a 64-bit slave to external master accesses to its + # internal space. + # + # - Bits 28-31 = Reserved. Set to 0. + # + #------------------------------------------------------------------------- + + addis r3,0,0x100c + stw r3,CYGARC_REG_IMM_BCR(r4) + + #------------------------------------------------------------------------- + # Program the 60x Bus Arbiter Configuration Register. The details are as + # follows: + # + # - Bits 0-1 = Reserved. Set to 0. + # + # - DBGD (Data Bus Grant Delay) = Minimum of zero wait states for PowerPC + # master-initiated data operations. This + # is the minimum delay between TS/ and + # DBG/. + # + # - Bits 3 = Reserved. Set to 0. + # + # - PRKM (Parking Master) = 0010 = CPM is at a low request level for the + # parked master. + # + #------------------------------------------------------------------------- + + addi r3,0,0x0002 + stb r3,CYGARC_REG_IMM_PPC_ACR(r4) + + + #------------------------------------------------------------------------- + # Program the 60x Bus Arbitration-Level[High] Register. The priority for + # potential bus masters are defined by locating the value associated with + # a particular master from the PRKM field in the PPC_ACR register and + # inserting its value in the priority field. Priority field 0 is the + # highest priority and the lowest is Priority field 15 in the PPC_ALRH + # register. + # + # - Priority Field 0 = 0000 = CPM high request level + # + # - Priority Field 1 = 0001 = CPM middle request level + # + # - Priority Field 2 = 0010 = CPM low request level + # + # - Priority Field 3 = 0110 = Internal Core + # + # - Priority Field 4 = 0111 = External Master 1 + # + # - Priority Field 5 = 1000 = External Master 2 + # + # - Priority Field 6 = 1001 = External Master 3 + # + # - Priority Field 7 = 0011 = Reserved + # + #------------------------------------------------------------------------- + + addis r3,0,0x0126 + ori r3,r3,0x7893 + stw r3,CYGARC_REG_IMM_PPC_ALRH(r4) + + + #------------------------------------------------------------------------ + # + # First program the SIUMCR. The details are as follows: + # + # - BBD (Bus Busy Disable) = 0 = [ABB/]/[IRQ2] pin is ABB/ and [DBB/]/IRQ2 + # pin is DBB/. + # + # - ESE (External Snoop Enable = 0 = [GPL/]/[IRQ1/] pin is IRQ1/ + # + # - PBSE (Parity Byte Select Enable) = 0 = Parity byte select is disabled. + # + # - CDIS (Core DISable) = 0 = The PowerQUICCII CPU core is enabled. + # + # - DPPC (Data Parity Pins Configuration) = 10 = + # + # Gives the following pin meanings: DP(0)|RSRV/|EXT_BR2/ = RSRV/ + # DP(1)|IRQ1/|EXT_BG2/ = IRQ1/ + # DP(2)|TLBISYNC/|IRQ2/ = TLBISYNC/ + # DP(3)|IRQ3/ = IRQ3/ + # DP(4)|IRQ4/ = IRQ4/ + # DP(5)|TBEN/|IRQ5 = TBEN/ + # DP(6)|CSE(0)|IRQ6/ = CSE(0) + # DP(7)|CSE(1)|IRQ7/ = CSE(1) + # + # - L2CPC (L2 Cache Pins Configuration) = 00 = + # + # Gives the following pin meanings: CI/|BADDR(29)|IRQ2/ = CI/ + # WT/|BADDR(30)|IRQ3/ = WT/ + # L2_HIT/|IRQ4 = L2_HIT/ + # + # CPU_BG/|BADDR(31) + # |IRQ5/ = CPU_BG/ + # + # - LBPC (Local Bus Pins Configuration) = 00 = + # + # Local Bus pins function as local bus. + # + # - APPC (Address Parity Pins Configuration) = 11 = + # + # Gives the following pin meanings: MODCK1|AP(1)|TC(0) = - + # MODCK2|AP(2)|TC(1) = - + # MODCK3|AP(3)|TC(2) = - + # IRQ7/|APE/|INT_OUT/ = IRQ7/+INT_OUT/ + # CS11/|AP(0) = - + # + # - CS10PC (Chip Select 10-pin Configuration) = 00 = + # + # CS10/|BCTL1/|DBG_DIS/ = CS10/ + # + # - BCTLC (Buffer Control Configuration) = 00 = + # + # BCTL0 pin is used as W|R/ control. BCTL1 is used as OE/ control if + # BCTL1 was connected to its alternate pin. + # + # - MMR (Mask Masters Requests) = 00 = No masking on bus request lines. + # + # - LPBSE (Local Bus Parity Byte Select Enable) = 0 + # + # Parity byte select is disabled. + # + # Bits 19-31 are reserved and set to 0. + # + #------------------------------------------------------------------------ + + #-------------------------------------------------------------------------- + # Program the 60x Bus Transfer Error Status and Control Register 1. The + # details are as follows: + # + # - DMD (Data Errors Disable) = 1 = + # + # Disable all data errors on the 60x bus. Also parity single and double + # ECC error. + # + # - All other bits are either status or reserved bits. All reserved bits + # should be set to 0. + #-------------------------------------------------------------------------- + + addis r3,0,0x0000 + ori r3,r3,0x4000 + stw r3,CYGARC_REG_IMM_TESCR1(r4) + + #-------------------------------------------------------------------------- + # Program the Local Bus Transfer Error Status and Control Register 1. The + # details are as follows: + # + # - DMD (Data Errors Disable) = 1 = + # + # Disable parity errors on the Local bus. + # + # - All other bits are either status or reserved bits. All reserved bits + # should be set to 0. + #-------------------------------------------------------------------------- + + addis r3,0,0x0E30 + ori r3,r3,0x0000 + stw r3,CYGARC_REG_IMM_SIUMCR(r4) + + # FIXME - What is this programming from?????? + addis r3,0,0x0000 + ori r3,r3,0x4000 + stw r3,CYGARC_REG_IMM_LTESCR1(r4) + + + #------------------------------------------------------------------------- + # First, program the Memory Periodic Timer Prescaler Register (MPTPR). + # Finding the value to this ties in with the desired SDRAM Refresh + # Timer (PSRT) value and the required Refresh Command interval for + # refreshing each row. The Refresh Command interval is found by + # determining the number of rows on the SDRAM device. In this case + # its 4096 (12 bits to address rows). The "Refresh Period" value in the + # AC characteristic section of the data sheet is 64 msec. This value + # is divided by the number of rows to give the number of Refresh + # commands that needs to be sent in a 64 msec interval. This value + # is 64 msec/4096 = 15.625 usec. + # Due to probable contention from time to time with other memory + # controller bus requests, lets make the refresh command interval to be + # around 15.5 usec. + # + # Using the calculation found in the MPC8260 User Manual errata, the + # timer period is + # + # Timer Period = (PSRT + 1) * (MPTPR[PTP] + 1) + # ---------------------------- + # Bus Frequency + # + # - Set PSRT = 16 + # - Set MPTPR[PTP] = 40 + # - Use 45 MHz as Bus Frequency + # + # + # - Timer Period = 15.489 usec + # + # + # The clock distribution block diagram looks like this: + # + # ---------- ------------- ----------- ------------- + # | Clock | | MPT | | SDRAM | | Refresh | + # | Gen. |-----| Prescaler |---------| Refresh |----| Command | + # | 45 Mhz | ------------- | Timer | | Logic in | + # | on Ts6 | ----------- | Mem.Cont. | + # | Board | ------------- + # ----------- + # + #------------------------------------------------------------------------- + +# addi r5,0,0x4000 # load 0x40 or 64 into the PTP field of MPTPR + addi r5,0,0x2800 # load 0x28 or 40 into the PTP field of MPTPR + sth r5,CYGARC_REG_IMM_MPTPR(r4) # store half word - bits[16-31] + + + + #----------------------- + # return from init_siu + #----------------------- + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_memc +# +# Description: +# +# The following registers directly control the memory controllers +# operation: +# +# BR0-BR11 - Base Register Banks 0-11 +# OR0-OR11 - Option Register Banks 0-11 +# PSDMR - 60x bus SDRAM machine mode register +# LSDMR - Local bus SDRAM machine mode register +# MAMR - UPMA mode register +# MBMR - UPMB mode register +# MCMR - UPMC mode register +# MDR - Memory data register +# MAR - Memory address register +# MPTPR - Memory periodic timer pre-scaler register +# PURT - 60x bus assigned UPM refresh timer +# PSRT - 60x bus assigned SDRAM refresh timer +# LURT - Local Bus assigned UPM refresh timer +# LSRT - Local Bus assigned SDRAM refresh timer +# +# This example will program the following registers. The rest will remain at +# their default values. +# +# BR0 - Base Register for Flash Memory +# OR0 - Option Register for Flash Memory +# BR1 - Base Register for BCSR (Board Control and Status Registers) +# OR1 - Option Register for BCSR +# BR2 - Base Register for 60x SDRAM +# OR2 - Option Register for 60x SDRAM +# BR3 - Base Register for 60x Local Bus SDRAM +# OR3 - Option Register for 60x Local Bus SDRAM +# PSDMR - 60x bus SDRAM machine mode register +# LSDMR - Local bus SDRAM machine mode register +# MPTPR - Memory periodic timer pre-scaler register +# PSRT - 60x bus assigned SDRAM refresh timer +# LSRT - Local Bus assigned SDRAM refresh timer +# +# +# History: +# +######################################################################### + +init_memc: + + mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers + # value will be restored so that this function + # can return to the calling address. + + bl init_flash # 8 Mbyte of flash memory + + bl init_fpga_mem # 64 KByte memory map for FPGA access + + bl init_cluster_bus # 256 MByte Memory mapped for Tiger Sharc cluster bus + +#ifdef MORE_FLASH +#endif +#if 0 // The Delphi TS6 Digital Board does not have BCSR + bl init_bcsr # Board Control and Status Registers +#endif + + bl init_60x_sdram # Main 60x Bus SDRAM + + #----------------------- + # return from init_memc + #----------------------- + + mtspr CYGARC_REG_LR,r30 # restore original Link Register value + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + + +############################################################################ +# Function: init_flash +# +# Description: This function programs Base Register 0 and Option Register 0 +# designating bank 0 for the 8Mbyte flash SIMM on the TS6 +# board. Programming these two registers describes how the +# MPC8260 will inter-operate with this memory space and thus +# this memory device. +# +# History: +# +############################################################################ + +init_flash: + + #------------------------------------------------------------------------- + # Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + # flash that resides on the MPC8260 TS6 board. + # The particulars are defined here. + # + # BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + addis r3,0,0xFF80 # R3 holds the value temporarily + ori r3,r3,0x1801 + #------------------------------------------------------------------------- + # Option Register 0 (OR0) for GPCM use: further flash definitions + # + # AM (Address Mask) = 0xFF80+0b = We have masked the upper 9 bits which + # defines a 8 Mbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter + # of a clock early. + # + # ACS (Address To Chip-Select Setup) = 00 = CS/ is output the same time as + # the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0011 = Add a 3 clock cycle wait state + # + # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated + # internally by the memory + # controller unless GTA/ is + # asserted earlier externally. + # + # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 1 = + # + # Extended hold time is generated by the memory controller. An idle + # clock cycle is inserted between a read access from the current bank + # and any write or read access to a different bank. + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFF80 # R5 holds the value temporarily + ori r5,r5,0x0836 + + #------------------------------------------------------------------------ + # It is important to note the order in which OR0 and BR0 are programmed. + # When coming out of reset and CS0 is the global chip select, OR0 MUST be + # programmed AFTER BR0. In all other cases BRx would be programmed after + # ORx. + #------------------------------------------------------------------------ + + #------------------ + # Write the values + #------------------ + + stw r3,CYGARC_REG_IMM_BR0(r4) + stw r5,CYGARC_REG_IMM_OR0(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_bcsr +# +# Description: This function programs Base Register 1 and Option Register 1 +# designating bank 1 for BCSR0, BCSR1, and BCSR2 on the TS6 +# board. BCSR stands for Board Control and Status Register. +# This space is treated as general I/O. Programming the +# following 2 registers describes how the MPC8260 will inter- +# operate with this memory space. +# +# History: +# +# Jan 9/99 jay +# +######################################################################### + +init_bcsr: + + + #------------------------------------------------------------------------- + # Base Register 1 (BR1): Bank 1 is assigned to the Board Control and + # Status Registers (BCSRs). There are 3 + # that resides on the MPC8260 TS6 board. + # The particulars are defined here. + # + # BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0450 # R3 holds the value temporarily + ori r3,r3,0x1801 + + #------------------------------------------------------------------------- + # Option Register 1 (OR1) for GPCM use: further BCSR definitions + # + # AM (Address Mask) = 0xFFFF +1b = We have masked the upper 17 bits which + # which defines a 32 Kbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally. + # + # ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same + # time as the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state + # + # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated + # internally by the memory + # controller unless GTA/ is + # asserted earlier externally. + # + # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is + # generated by the memory + # controller + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFFFF # R5 holds the value temporarily + ori r5,r5,0x8010 + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR1(r4) + stw r3,CYGARC_REG_IMM_BR1(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_fpga_mem +# +# Description: This function programs Base Register 4 and Option Register 4 +# designating bank 4 for the FPGA control space on the TS6 +# board. +# +# History: +# +# +######################################################################### + +init_fpga_mem: + + + #------------------------------------------------------------------------- + # Base Register 4 (BR4): Bank 4 is assigned to FPGA control memory map. + # + # BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0450 # R3 holds the value temporarily + ori r3,r3,0x1801 + + #------------------------------------------------------------------------- + # Option Register 1 (OR1) for GPCM use: further BCSR definitions + # + # AM (Address Mask) = 0xFFFF +0b = We have masked the upper 16 bits which + # which defines a 64 Kbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter cycle + # early. For now, put in all delay + # possible. + # + # ACS (Address To Chip-Select Setup) = 11 = CS/ is output one half clock + # after the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0000 = The SETA bit is set, therefore + # SCY is not used. + # + # SETA (External Transfer Acknowledge) = 1 = PSDVAL/ is generated + # by external logic, is this + # case, the FPGA. + # + # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 1 = Eight idle cycle inserted + # between a read access from + # the current bank and + # next access. + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFFFF # R5 holds the value temporarily + ori r5,r5,0x0E0E + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR4(r4) + stw r3,CYGARC_REG_IMM_BR4(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + +######################################################################### +# Function: init_cluster_bus +# +# Description: This function programs Base Register 8 and Option Register 8 +# designating bank 8 for the Cluster Bus space on the TS6 +# board. +# +# History: +# +# +######################################################################### + +init_cluster_bus: + + + #------------------------------------------------------------------------- + # Base Register 8 (BR8): Bank 8 is assigned to Cluster Bus memory map. + # + # BA (Base Address) = 0xe000+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 00b = 64 bit port size (use 64 bit port size) + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0xE000 # R3 holds the value temporarily + ori r3,r3,0x0001 + + #------------------------------------------------------------------------- + # Option Register 8 (OR8) for GPCM use: further BCSR definitions + # + # AM (Address Mask) = 0xF000 +0b = We have masked the upper 4 bits which + # which defines a 256 Mbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter cycle + # early. For now, put in all delay + # possible. + # + # ACS (Address To Chip-Select Setup) = 11 = CS/ is output one half clock + # after the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0000 = The SETA bit is set, therefore + # SCY is not used. + # + # SETA (External Transfer Acknowledge) = 1 = PSDVAL/ is generated + # by external logic, is this + # case, the FPGA. + # + # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 1 = Eight idle cycle inserted + # between a read access from + # the current bank and + # next access. + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xF000 # R5 holds the value temporarily + ori r5,r5,0x0E0E + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR8(r4) + stw r3,CYGARC_REG_IMM_BR8(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + + +######################################################################### +# Function: init_60x_sdram +# +# Description: This function programs the 64 Mbyte SDRAM DIMM on the TS6 +# board. This memory functions as the RAM for the 603 core and +# is connected to the 60x bus. Base and Option Register 5 are +# used as well as the SDRAM Machine #1 and Chip Select #5. +# +# History: +# +# Apr /10/02 pfine Modified so that all 64 MBytes are addressable. +# +# Feb /27/02 pfine Modified the Motorola code to work for the TS6 +# board. +# Jan /9/99 jay Initial Release +# +######################################################################### + +init_60x_sdram: + + + # The Delphi MPC8260 TigerSHARC-6 Board is stocked with a 64 MByte + # SDRAM DIMM module (WINTEC W9Q308647PA-222H). The DIMM module consists + # of 4 Micron Technology 128 Mbit SDRAM modules, each having 12 row + # by 9 columns by 4 banks. The part number for the Micron SDRAM + # is 48LC8M16A2. The Refresh Period is 64 milliseconds for all 4096 + # rows, or 15.625 usec per row. + # + # NOTE - The spec sheet for the WINTEC DIMM claims that the device + # has 12/11/2 rows/columns/banks, but the spec sheet for the Micron + # SDRAM chips says 12/9/4. The 4 Banks seems to work. + + # The TS6 board has the 60x Bus SDRAM connected to CS5, so use BR5, OR5. + + #------------------------------------------------------------------------- + # Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT). + # See SIU initialization programming for details of why 16 is the + # value for the PSRT. + #------------------------------------------------------------------------- + + addi r5,0,0x0010 # load 0x10 or 16 + stb r5,CYGARC_REG_IMM_PSRT(r4) # store byte - bits[24-31] + + + ######################### + # Program Bank Registers + ######################### + + + #------------------------------------------------------------------------- + # Base Register 5 (BR5): Bank 5 is assigned to the 64 Mbyte 60x SDRAM DIMM + # that resides on the MPC8260 TS6 board. The + # particulars are defined here. + # + # - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This + # value represents the upper 17 bits of the base + # address. + # + # - Bits 17-18 reserved. = 00 = cleared to 0. + # + # - PS (Port Size) = 00b = 64 bit port size + # + # - DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # - WP (Write Protect) = 0 = both read and write accesses are allowed + # + # - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected + # + # - EMEMC (External Memory Controller Enable) = 0 = + # + # Accesses are handled by the memory controller according to MSEL. + # + # - ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # - DR (Delayed Read) = 0 = Normal operation. + # + # - V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0000 # R3 holds the value temporarily + ori r3,r3,0x0041 + + #------------------------------------------------------------------------- + # Option Register 5 (OR5) for SDRAM Machine use: further SDRAM definitions + # + # - SDAM (SDRAM Address Mask) = 1111 1100 0000b = 0xFC0 + # As per the errata to the MPC8260 Users Manual, the SDAM value + # is a 12 bit field (0-11). The 64 MByte block is specified. + # + # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size. + # + # - BPD (Banks Per Device) = 01b = 4 internal banks per device. + # + # + # + # -- The SDRAM is set up to operate in Page Based Interleaving Mode. + # + # - ROWST (Row Start Address Bit) = 0110b = A6 being the row start address + # bit. See the PSDMR programming + # explanation below for details + # of how A6 was determined to be + # the starting row. + # As per the errata to the MPC8260 Users Manual, the ROWST field + # bits 19-22. + # + # - NUMR (Number of Row Address Lines) = 011b = 12 row address lines. + # + # - PMSEL (Page Mode Select) = 1 + # + # - IBID (Internal bank interleaving within same device disable) = 1 + # + # As per MPC8260 Users Manual, if the SDRAM device is not connected + # to the BNKSEL pins, then this bit should be set. The BNKSEL pins + # are not connected on the TS6 platform. + # + # - Bits 28-31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFC00 # R5 holds the value temporarily + ori r5,r5,0x2CF0 + + #------------------ + # Write the values + #------------------ + stw r5,CYGARC_REG_IMM_OR5(r4) + stw r3,CYGARC_REG_IMM_BR5(r4) + + ########################################### + # Perform Initialization sequence to SDRAM + ########################################### + + #------------------------------------------------------------------------- + # Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used + # to configure operations pertaining to SDRAM. Program the PSDMR, turning + # off refresh services and changing the SDRAM operation to "Precharge all + # banks". Then do a single write to an arbitrary location. Writing 0xFF + # to address 0 will do the trick. + # + # - PBI (Page Based Interleaving) = 1 + # + # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit + # will be set later in this function as a + # last step. + # + # - OP (SDRAM Operation) = xxx Precharge all banks 101b + # CBR Refresh 001b + # Mode register write 011b + # Normal operation 000b + # + # - SDAM (Address Multiplex Size = 011 = + # + # FIXME - This explanation needs to updated. + # The 64 MByte SDRAM DIMM used on the TS6 platform has only 12 address + # pins and 2 bank select pins. The MPC8260 SDRAM memory controller + # must multiplex the 23 MPC8260 address bits (64 MBytes = 2^26, but + # the 3 lsbs are ignored due to the 64 bit depth of the SDRAM) onto + # the available SDRAM pins. + + # The following explanation will explain (hopefully) how the 23 bits + # of the effective address (as seen from the MPC8260) will be remapped + # onto the physical pins of the SDRAM device. It is expected that + # the MPC8260 Users Manual (Chapter 10) is necessary to understand + # this explanation. + # + # Page Based Interleaving is chosen as the address multiplexing method. + # The SDRAM device architecture is 12 rows, 9 columns, 4 banks. + # + # The effective address space as seen from the MPC8260 is partitioned + # as follows to map to the architecture of the SDRAM device. + # + # addresses ignored by SDRAM : A29 A30 A31 + # + # column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28 + # + # bank select addresses: A18 A19 + # + # row addresses: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 + # + # These address bits correspond to the effective address which the MPC8260 + # is attempting to access. The MPC8260 memory controller, through + # the settings of the BR5/OR5 and PSDMR registers, will remap these + # effective addresses bits onto the physical address pins of the SDRAM + # DIMM. + # + # -1) The SDRAM has a data width of 64 bits, which means that each + # read or write consists of 8 8-bit bytes aligned on an 8 byte + # boundary. Therefore, the lowest three address bits (A29 A30 A31) + # are always ignored, and not physically connected to the SDRAM. + # + # -2) The 9 column address bits select one column of 512 for + # SDRAM read or write. These bits are mapped directly to the + # physical pins on the SDRAM DIMM. + # + # -3) In Page Based Interleaving mode (PSDMR[PBI] = 1) the bank select + # lines are assigned the address lines between the column addresses + # and the row addresses. By setting OR5[BPD] = 01, the memory + # controller knows that there are 4 banks, and therefore 2 bank + # select lines (A18 A19). The TS6 platform has MPC8260 address + # lines A14 and A15 connected to the two bank select pins on the + # DIMM, and therefore PSDMR[BSMA] = 001. + # + # PSDMR[PBI] = 1 + # OR5[BPD] = 01 + # + # To clarify, selecting PSDMR[BSMA] = 001 tells the memory + # controller to put out the bits corresponding to the bank select + # address bits on the address lines named A14 and A15. + # Those bank select lines correspond to effective address bits + # A18 and A19. So the effective address bits A18 and A19 actually + # are put out onto the A14 and A15 address lines, which are, in + # turn, connected to BA1 and BA0 on the SDRAM DIMM. + # + # PSDMR[BSMA] = 001 + # + # -4) The remaining 12 address bits are the row addresses. Simple + # subtraction says that the starting row address bit + # (OR5[ROWST]) is A6 (3 bits not connected, 9 column bits, 2 + # bank select bits, 12 row bits). + # + # OR5[NUMR] = 011b ==> 12 rows + # OR5[ROWST] = 0110b ==> A6 is row start address bit + # + # -5) The memory controller must be told how to multiplex the row + # address bits onto the physical pins of the SDRAM device. This + # is accomplished through the PSDMR[SDAM] field. + # Lining up the column and row addresses so that the + # lsb of the row addresses lines up with the lsb of the column + # addresses gives the following arrangemnt: + # + # column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28 + # row addresses: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 + # + # The MPC8260 Users Manual, Table 10-20 shows that PSDMR[SDAM] = 011b + # provides the proper alignment for this multiplexing scheme. + # + # PSDMR[SDAM] = 011b + # + # -6) The final complication in the SDRAM configuration is the SDA10 + # control. SDRAM is accessed in a two stage process. In the + # first stage, the row address and bank selects are loaded to the + # SDRAM device. In the second stage, the column address is loaded. + # SDRAM devices multiplex the A10/AP pin for two purposes. In the + # first stage, A10/AP is an address pin. In the second stage, the + # pin is used to determine how precharging is done (this + # explanation will not go into this aspect). Because the A10/AP + # pin is special, the pin is connected physically to a special + # pin on the MPC8260, the PSDA10 pin. The memory controller must + # be told how which address bit is being multiplexed on PSDA10. + # + # The row address bit which is multplexed onto the pin between + # A9 and A11 physical pins on the SDRAM device is this special bit. + # Lining up the physical pins and the MPC8260 address lines (from + # sheet 15 of the TS6 platform schematics) and the line of Table 20 + # corresponding to SDAM = 011b + # + # SDRAM physical pins: A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 + # MPC8260 address lines:A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 + # row address: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 + # + # It is seen that the row address bit which will appear on the A10 + # physical pin is A7 and therefore + # + # PSDMR[SDA10] = 011b ==> Address bit A7 (for PBI = 1) + # + # - BSMA (Bank Select Multiplexed Address line) = 001 = A13-A15 + # + # - SDA10 ("A10 Control") = 011 = + # + # FIXME - The following timing values are not optimized. They are the + # same values as were used in the MPC8260 TS6 board, with + # the 16 MByte DIMM and a 66 MHz Bus Frequency. + # + # - RFRC (ReFresh ReCovery) = 101 = + # + # Once a refresh request is granted, the memory controller begins + # issuing auto-refresh commands to each device associated with the + # refresh timer in one clock intervals. After the last REFRESH + # command is issued, the memory controller waits for 7 clocks before + # the ACTIVATE command and before normal read/write operations can + # resume. + # + # - PRETOACT (PREcharge TO ACTivate interval) = 011 = + # + # Wait 3 clock cycles before an activate command. This parameter is + # determined by the requirements of the SDRAM at a particular clock + # speed. + # + # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles. + # + # - BL (Burst Length) = 0 = SDRAM burst length is 4. This is programmed + # into the SDRAM via the MRS commmand. + # + # - LDOTOPRE (Last Data Out TO PREcharge) = 01 = + # + # The delay required from the last data out to precharge state is 1 clock + # cycle. This parameter is determined by the requirements of the SDRAM at + # a particular clock speed. + # + # - WRC (Write Recovery Time) = 01 = + # + # Time needed to elapse before another operation is 1 clock cycle. This + # parameter is determined by the requirements of the SDRAM at a + # particular clock speed. + # + # - EAMUX (External Address MUltipleXing) = 0 No external address + # multiplexing. + # + # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control + # lines. + # + # - CL (CAS Latency) = 10 = + # + # CAS latency is 2. Two cycles after column address is registered, data + # is valid. This parameter is determined by the requirements of the + # SDRAM at a particular clock speed. + # + #------------------------------------------------------------------------- + + ################## + # Precharge all banks + ################## + + # Clear refresh enable bit (bit 1 = 0) + # Set OP mode to Precharge (bits 2-4 = 101b) + + addis r3,0,0x8B2E + ori r3,r3,0xB452 + + stw r3,CYGARC_REG_IMM_PSDMR(r4) + addis r0,0,0 + + addi r3,0,0x00FF # Load 0x000000FF into r3 + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + + #------------------------------------------------------------------------- + # Program the PSDMR keeping refresh services off and changing the + # SDRAM operation to "CBR Refresh". This step is responsible for issuing + # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine + # by issuing the CBR Refresh command by programming the OP field of the + # PSDMR register and writing 0xFF 8 times to an arbitrary address. + #------------------------------------------------------------------------- + + # Clear refresh enable bit (bit 1 = 0) + # Set OP mode to CBR Refresh (bits 2-4 = 001b) + + addis r3,0,0x8B2E + ori r3,r3,0xB452 + + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + #------------------------------------------ + # Loop 8 times, writing 0xFF to address 0 + #------------------------------------------ + + addi r6,0,0x0008 + mtspr CYGARC_REG_CTR,r6 # Load CTR with 8. The CTR special purpose + # is spr 9 + + addi r3,0,0x00FF # Load 0x000000FF into r3 + +write_loop: + + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + bc 16,0,write_loop # Decrement CTR, then branch if the decremented CTR + # is not equal to 0 + + #------------------------------------------------------------------------- + # Program the PSDMR again turning off refresh services and changing the + # SDRAM operation to "Mode Register Write". Then do a single write to an + # arbitrary location. The various fields that will be programmed in the + # mode register on the SDRAM were specified in fields of the PSDMR, like + # the BR (burst length) and the CL (CAS Latency) field. + #------------------------------------------------------------------------- + + # Clear refresh enable bit (bit 1 = 0) + # Set OP mode to Mode Register Write (bits 2-4 = 011b) + + addis r3,0,0x9B2E + ori r3,r3,0xB452 + + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + addi r3,0,0x00FF # Load 0x000000FF into r3 + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + #------------------------------------------------------------------------- + # Program the PSDMR one last time turning on refresh services and changing + # the SDRAM operation to "Normal Operation". + #------------------------------------------------------------------------- + + # Set refresh enable bit (bit 1 = 1) + # Set OP mode to Normal Operation (bits 2-4 = 000b) + + addis r3,0,0xC32E + ori r3,r3,0xB452 + + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + #---------------------------- + # return from init_60x_sdram + #---------------------------- + + bclr 20,0 # jump unconditionally to effective address in Link + # register + +init_user_leds: + + # Initialize Port A pins + # Pin 30-31 GPIO wires to RF board + # Pin 29 TS_RESET_L, output, Tiger Sharc Reset line, drive low on + # initialization. + # Pin 28 LB_ENB_L, output, Link Port Buffer enable, drive high on + # initialization. + # Pin 26-27 GPIO wires to RF board + # Pin 18-23 GPIO wires, one each to Tiger Sharc + # Pin 12-17 Interrupt wires to Sharc, output, drive high on + # initialization. + + # Set Port A pins 12-31 for general purpose, i.e., to 0 + # Set Port A pins 12-17, 28, 29 (add more later) for output (set to 1) + # for lines that we do not know, set to 0 (input) + # Set Port A output pins High or Low, as specified +#define TS6_PPARA_INIT_MASK 0xFFF00000 +#define TS6_PDIRA_INIT_MASK 0x3003F000 +#define TS6_PDATA_INIT_MASK 0x1003F000 + + # Initialize Port B Pins 4,5,6,7 general purpose IO + # Pin 4 LED 18, Red + # Pin 5 LED 18, Green + # Pin 6 LED 17, Red + # Pin 7 LED 17, Green + + mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers + # value will be restored so that this function + # can return to the calling address. + + addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We + # add 0x10000 because using relative addressing + # in load and store instructions only allow a + # offset from the base of +/-32767. + + addi r6,0,0 # R6 = 0 + lwz r3,0x0D24(r4) # R3 = PPARB + rlwimi r3,r6,0,4,7 +# and r3,r3,r6 # Clear bits 4,5,6,7 + stw r3,0x0D24(r4) # Store 0 to PPARB to set 4 bits to general + # purpose. + + addis r6,0,0x0F00 # R6 = 0x0F000000 + lwz r3,0x0D20(r4) # R3 = PDIRB + or r3,r3,r6 # Set bits 4,5,6,7 + stw r3,0x0D20(r4) # Store r3 to PDIRB to set 4 bits as outputs. + + #----------------------- + # return from init_user_leds + #----------------------- + mtspr CYGARC_REG_LR,r30 # restore original Link Register value + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +flash_leds_forever: + # This function assumes that the Port B registers have been properly + # initialized so the LEDs will function. See init_user_leds. + + addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We + # add 0x10000 because using relative addressing + # in load and store instructions only allow a + # offset from the base of +/-32767. + + + + addi r3,0,0x000F # R3 will hold value of LEDs, start with all off + +flash_again: + #~~~~~~~~~~~~~~~~~~~~~~~~~~ + # Load count of 0x0040000 + #~~~~~~~~~~~~~~~~~~~~~~~~~~ + + addis r5,r0,4 + + #~~~~~~~~~~~~~~~~~ + # Delay Loop here + #~~~~~~~~~~~~~~~~~ + +check_count: + + #------------------------- + # while (count != 0) + #------------------------- + + cmpi 0,0,r5,0 + bc 12,2,count_done # if zero branch to count_done + + #----------- + # count--; + #----------- + + addi r5,r5,-1 + b check_count + +count_done: + #increment r3 + addi r3,r3,1 + rlwinm r6,r3,24,4,7 # left shift r3 by 24, mask r3 so + # so bits 4 -7 are all thats left, + # and store result in r6 + stw r6,0x0D30(r4) # Store new value to PDATB Register + b flash_again + + +#ifdef CYG_HAL_STARTUP_ROM + # This routine will test the memory from address 0x0 + # thru 0x03ffffff (64MByte) by writing the address to the address + # for all addresses, and then reading each of those values. + # + # Use two loops, the outer loop goes from 0 to 0x3ff and counts + # by 1. The inner loop goes from 0 to 0xfffc and counts by 4. +memory_test: + + #Turn on Green Led + # For TS6 board, LD17 will signal running status + # LD17 == GREEN ==> writing data to memory + # LD17 == RED ==> reading data from memory and comparing + # LD17 == OFF ==> test completed + # For TS6 board, LD18 will test status + # LD18 == GREEN ==> all memory location contained expected values + # LD18 == RED ==> error reading memory location, + # r6 contains address and expected value + # r10 contains actual value read + # LD18 == OFF ==> test not completed + # + # r23 will hold the largest memory value to test + # r29 will hold the smallest memory value (0x0 <= r29 < 0x10000) + # NOTE read the code to find out exactly how the test is run. + bl init_user_leds + + addis r23, 0, 0x0400 # Initialize r23 to 64 MBytes + addis r29, 0, 0x0 # Initialize r29 to 0 + + addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We + # add 0x10000 because using relative addressing + # in load and store instructions only allow a + # offset from the base of +/-32767. + # LD18 off, LED17 Green + lwz r3,0x0D30(r4) # r3 = PDATB value + addis r5,0,0x0d00 # LD18 off, LED17 Green + rlwimi r3,r5,0,4,7 + stw r3,0x0D30(r4) + + #addis r3,0,0x0200 # r3 will hold the outer counter, start at 0x3ff0000 + #addis r9,0,0x0000 # r9 will hold the stop address + + mr r3, r23 # r23 holds the start value, set with debugger + mr r9, r29 # r29 holds the stop value, set with debugger + +memwrite_loop1: + addis r3,r3,-1 # subtract 0x10000 from r3 + addis r5,0,0x1 # r5 will hold inner counter, start at 0xfffc + + # generate the value to store in the address. It is the value in r3 + # shifted by 16 plus the vale in r5. + +memwrite_loop2: + addi r5,r5,-4 # subtract 1 from r5 + + add r6,r3,r5 + stwx r6,r5,r3 # Store the value at r6 in the memory addressed + # by the sum of r3 and r5 + cmpi 0,0,r5,0 + bne memwrite_loop2 # branch if r5 != 0 + +# Check if r3 is 0 + cmp 0,0,r3,r9 + bne memwrite_loop1 # branch if r3 != 0 + +# Writing to memory complete, start reading and validating + # LD18 off, LED17 Red + lwz r3,0x0D30(r4) # r3 = PDATB value + addis r5,0,0x0e00 # LD18 off, LED17 Red + rlwimi r3,r5,0,4,7 + stw r3,0x0D30(r4) + + #addis r3,0,0x0200 # r3 will hold the outer counter, start at 0x3ff0000 + #addis r9,0,0x0000 # r9 will hold the stop address + mr r3, r23 # r23 holds the start value, set with debugger + mr r9, r29 # r29 holds the stop value, set with debugger + + +memread_loop1: + addis r3,r3,-1 # subtract 0x10000 from r3 + addis r5,0,0x1 # r5 will hold inner counter, start at 0xfffc + + # generate the value to store in the address. It is the value in r3 + # shifted by 16 plus the vale in r5. + +memread_loop2: + addi r5,r5,-4 # subtract 1 from r5 + + add r6,r3,r5 + lwzx r10,r5,r3 # Read the value into r10 from the memory addressed + # by the sum of r3 and r5 + cmpw r6,r10 # compare values + bne mem_error + + cmpi 0,0,r5,0 + bne memread_loop2 # branch if r5 != 0 + +# Check if r3 is 0 + cmp 0,0,r3,r9 + bne memread_loop1 # branch if r3 != 0 + + + # We get here if memory test passes + # LD18 Green, LED17 Off + lwz r3,0x0D30(r4) # r3 = PDATB value + addis r5,0,0x0700 # LD18 Green, LED17 Off + rlwimi r3,r5,0,4,7 + stw r3,0x0D30(r4) + + addis r7,0,0x0E00 + stw r7,0(r8) + b branch_to_dot + +mem_error: + # We get here if a memory error was detected + # LD18 Red, LED17 Off + lwz r3,0x0D30(r4) # r3 = PDATB value + addis r5,0,0x0b00 # LD18 off, LED17 Red + rlwimi r3,r5,0,4,7 + stw r3,0x0D30(r4) +#endif +branch_to_dot: + b branch_to_dot + + +#------------------------------------------------------------------------------ +# end of ts6.S
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/ChangeLog @@ -0,0 +1,61 @@ +2002-12-12 Gary Thomas <gthomas@ecoscentric.com> +2002-12-12 Patrick Doyle <wpd@delcomsys.com> + + * src/vads.S: + * src/hal_diag.c: + * src/hal_aux.c: + * misc/redboot_ROMRAM.ecm: + * misc/redboot_ROM.ecm: + * misc/redboot_RAM.ecm: + * include/pkgconf/mlt_powerpc_vads_romram.ldi: + * include/pkgconf/mlt_powerpc_vads_romram.h: + * include/pkgconf/mlt_powerpc_vads_romlow.ldi: + * include/pkgconf/mlt_powerpc_vads_romlow.h: + * include/pkgconf/mlt_powerpc_vads_romhigh.ldi: + * include/pkgconf/mlt_powerpc_vads_romhigh.h: + * include/pkgconf/mlt_powerpc_vads_rom.mlt: + * include/pkgconf/mlt_powerpc_vads_ram.mlt: + * include/pkgconf/mlt_powerpc_vads_ram.ldi: + * include/pkgconf/mlt_powerpc_vads_ram.h: + * include/plf_stub.h: + * include/plf_intr.h: + * include/plf_cache.h: + * include/hal_diag.h: + * cdl/hal_powerpc_vads.cdl: New package - support for Motorola + Voyager (VADS) MPC8260 board. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/cdl/hal_powerpc_vads.cdl @@ -0,0 +1,383 @@ +# ==================================================================== +# +# hal_powerpc_vads.cdl +# +# Motorola MPC8260 Voyager ADS board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): wpd +# Original data: hmt +# Contributors: +# Date: YYYY-MM-DD +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_POWERPC_VADS { + display "MPC8260 VADS board" + parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_MPC8260 + define_header hal_powerpc_vads.h + include_dir cyg/hal + description " + The VADS HAL package provides the support needed to run + eCos on a Mototola MPC8260 VADS board." + + compile hal_diag.c hal_aux.c vads.S + + implements CYGINT_HAL_DEBUG_GDB_STUBS +# removed by WPD for now + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT +# added by WPD for now + +# Note: uncomment this to get old-style debug behaviour +# implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8260.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_vads.h>" + + puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC MPC8260\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Voyager ADS\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + This option is used to control where the application program will + run, either from RAM or ROM (flash) memory. ROM based applications + must be self contained, while RAM applications will typically assume + the existence of a debug environment, such as GDB stubs." + + cdl_option DCSPRI_HAL_VADS_ROM_MLT { + display "Memory Layout for ROM Startup" + flavor data + legal_values {"LOW" "HIGH" "RAM"} + default_value {"HIGH"} + description " + + This option selects which memory layout file should be + used when configuring the VADS board for ROM startup. + The LOW option selects the memory layout for an image + stored at the beginning of the FLASH. It should be + used when the (hard reset) IP and boot memory space + are both mapped to address 0. + + The HIGH option selects the memory layout for an image + stored in the last Megabyte of FLASH. It should be + used when the (hard reset) IP maps the interrupt + vector base address to 0xFFF00000 and the boot memory + space to the last 32 Megabytes of FLASH. + + The RAM option is a hack used to place the ROM image + in RAM in order to simplify the development of a ROM + monitor by using the existing ROM monitor to load it + into RAM, but pretend like it is in ROM." + } + + } + + cdl_option CYGHWR_HAL_POWERPC_DISABLE_MMU { + display "DISABLE MMU" + flavor bool + default_value 1 + # calculated 1 + description " + This option will disable the MMU enabled." + } + + cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED { + display "Development board clock speed (MHz)" + flavor data + legal_values 45 60 66 + default_value 66 + description " + The Delphi TigerSHARC-6 board will probably run at either + 45 or 60 MHz. In the short term, however, we will be using + an MPC8260ADS board running at 66 MHz. Select the clock + speed appropriate for your board so that the system can set + the serial baud rate correctly, amongst other things." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + description " + Period is busclock/4/CYGNUM_HAL_RTC_DENOMINATOR. VERIFY THIS!!!" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + description " + This option selects the number of system clock 'ticks' + per second. This rate is sometimes known as the heartbeat rate." + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated { (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/4)/CYGNUM_HAL_RTC_DENOMINATOR) } + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "powerpc-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=603e -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=603e -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +# We don't support GDB BREAK (yet) +# requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +# + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the platform CDL takes care of creating + an S-Record data file. -- This needs more work" + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec --srec-forceS3 $< $(@:.bin=.s19) + $(OBJCOPY) -O binary $< $@ +# } +# Changed the .srec extentsion to .txt for ease of downloading with hyperterm +# Changed the .txt extentsion to .s19 for ease of downloading with OCD + } + } + + cdl_component CYGPKG_HAL_POWERPC_VADS_OPTIONS { + display "MPC8260 VADS build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_POWERPC_VADS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the VADS HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_POWERPC_VADS_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the VADS HAL. These flags are removed from + the set of global flags if present." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_vads_ram" : \ + "powerpc_vads_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_vads_ram.ldi>" : \ + DCSPRI_HAL_VADS_ROM_MLT == "LOW" ? "<pkgconf/mlt_powerpc_vads_romlow.ldi>" : \ + DCSPRI_HAL_VADS_ROM_MLT == "HIGH" ? "<pkgconf/mlt_powerpc_vads_romhigh.ldi>" : \ + "<pkgconf/mlt_powerpc_vads_romram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_vads_ram.h>" : \ + DCSPRI_HAL_VADS_ROM_MLT == "LOW" ? "<pkgconf/mlt_powerpc_vads_romlow.h>" : \ + DCSPRI_HAL_VADS_ROM_MLT == "HIGH" ? "<pkgconf/mlt_powerpc_vads_romhigh.h>" : \ + "<pkgconf/mlt_powerpc_vads_romram.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor bool + default_value { (CYG_HAL_STARTUP == "RAM" && + !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS && + !CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED && + !CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + requires ! CYGSEM_HAL_POWERPC_COPY_VECTORS + requires ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED + description " + Allow coexistence with ROM monitor (CygMon or GDB stubs) by + only initializing interrupt vectors on startup, thus leaving + exception handling to the ROM monitor." + } + + + # FIXME: the option above should be adjusted to select between monitor + # variants + cdl_option CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs { + parent CYGPKG_HAL_ROM_MONITOR + display "Bad CDL workaround" + calculated 1 + active_if CYGSEM_HAL_USE_ROM_MONITOR + } + + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + +# compile -library=libextras.a redboot_cmds.c + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming. + This needs more work." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O srec --change-address=0x02040000 $< $(@:.bin=.ppcbug) + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/hal_diag.h @@ -0,0 +1,174 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 1998-03-02 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +// These should not need to be prototyped here, but where???? +cyg_uint8 +cyg_hal_plf_serial_getc(void); + +#if 1 +void +cyg_hal_plf_serial_putc(cyg_uint8 ch); +#else +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); +#endif + +#if 1 +void +cyg_hal_plf_serial_init(void); +#else +void +cyg_hal_plf_serial_init_channel(void); +#endif +#endif //#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +#define LATER +#ifdef LATER +// See the #else clause at the end +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#else +// Need to figure out what to do here at some point, for now, I just copied +// these from the simulator hal_diag.h + +//----------------------------------------------------------------------------- +// Register addresses + +#define PAL_RESET 0x00 +#define PAL_CPU_NR 0x04 +#define PAL_INT 0x08 +#define PAL_NR_CPU 0x0a + +#define PAL_READ_FIFO 0x10 +#define PAL_READ_STATUS 0x14 +#define PAL_WRITE_FIFO 0x18 +#define PAL_WRITE_STATUS 0x1a + +#define OEA_DEV 0xf0001000 + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() + +// Added by WPD +#ifndef HAL_DISABLE_INTERRUPTS +#define HAL_DISABLE_INTERRUPTS +#define HAL_RESTORE_INTERRUPTS +#endif + +#define HAL_DIAG_WRITE_CHAR(_c_) \ +CYG_MACRO_START \ + volatile unsigned char *tty_buffer = \ + (unsigned char*)(OEA_DEV + PAL_WRITE_FIFO); \ + volatile unsigned char *tty_status = \ + (unsigned char*)(OEA_DEV + PAL_WRITE_STATUS); \ + unsigned long __state; \ + \ + HAL_DISABLE_INTERRUPTS(__state); \ + if( _c_ != '\r' ) \ + { \ + while( *tty_status == 0 ) continue; \ + *tty_buffer = _c_; \ + } \ + HAL_RESTORE_INTERRUPTS(__state); \ +CYG_MACRO_END + +#define HAL_DIAG_READ_CHAR(_c_) \ +CYG_MACRO_START \ + volatile unsigned char *tty_buffer = \ + (unsigned char*)(OEA_DEV + PAL_READ_FIFO); \ + volatile unsigned char *tty_status = \ + (unsigned char*)(OEA_DEV + PAL_READ_STATUS); \ + while( *tty_status == 0 ) continue; \ + _c_ = *tty_buffer; \ +CYG_MACRO_END +#endif // LATER +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_ram.h @@ -0,0 +1,37 @@ +// eCos memory layout - Fri Oct 20 10:35:23 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x1000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_for_rom) []; +#endif +#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom)) +#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x1cd00) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_ram.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:35:23 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00020000, LENGTH = 0x1000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x1cd00; + SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_ram.mlt @@ -0,0 +1,17 @@ +version 0 +region ram 0 400000 0 ! +section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table ! +section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table ! +section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom ! +section reserved_for_rom 1cd00 10 0 0 0 1 0 1 vectors vectors ! +section vectors 0 10 0 1 0 1 0 1 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_rom.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 1000000 0 ! +section vectors 0 1 0 1 1 0 1 0 0 0 ! +section reserved_vsr_table 200 1 0 0 1 1 1 1 3000 3000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romhigh.h @@ -0,0 +1,30 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x01000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xff800000) +#define CYGMEM_REGION_rom_SIZE (0x00800000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) + +#if 1 +#define CYGMEM_SECTION_heap1_SIZE (0x100000 - (size_t) CYG_LABEL_NAME (__heap1)) +#else // Attempt to make more RAM usable in RedBoot ROM version +#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1)) +#endif
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romhigh.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + rom : ORIGIN = 0xff800000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xfff00000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romlow.h @@ -0,0 +1,25 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x01000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0xff800000) +#define CYGMEM_REGION_rom_SIZE (0x00800000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x100000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romlow.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + rom : ORIGIN = 0xff800000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xff800000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romram.h @@ -0,0 +1,25 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x01000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x00f00000) +#define CYGMEM_REGION_rom_SIZE (0x00100000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x100000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/pkgconf/mlt_powerpc_vads_romram.ldi @@ -0,0 +1,32 @@ +// eCos memory layout - Fri Oct 20 10:36:41 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + rom : ORIGIN = 0x00f00000, LENGTH = 0x00100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0x00f00000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + CYG_LABEL_DEFN(__reserved_for_flash) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_for_flash) + 0xcd00; + SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/plf_cache.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform HAL cache details +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-01-26 +// Purpose: Platform cache control API +// Description: The macros defined here provide the platform specific +// cache control operations / behavior. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//--------------------------------------------------------------------------- +// Initial cache enabling +#if 1 +#ifdef CYGSEM_HAL_ROM_MONITOR +# define CYGPRI_INIT_CACHES +# define CYGPRI_ENABLE_CACHES +#endif +#else +// Disable caches for now +# define CYGPRI_INIT_CACHES +# define CYGPRI_ENABLE_CACHES + +// Hack to enable "quicc_smc1.c" to compile +#if 0 // I don't think the MPC8260 needs this stuff +#define CYGPKG_HAL_POWERPC_MPC860 +#define HAL_DCACHE_INVALIDATE(x, y) +#define CYGNUM_HAL_INTERRUPT_CPM_SMC1 0 +#endif + +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/plf_intr.h @@ -0,0 +1,87 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// VADS platform specific interrupt definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 2000-06-13 +// Purpose: Define platform specific interrupt support +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#ifdef CYGPKG_HAL_QUICC +//-------------------------------------------------------------------------- +// Control-C support. + +// Defined by the quicc driver +#include <cyg/hal/quicc/quicc_smc1.h> +#endif + + +//---------------------------------------------------------------------------- +// Reset. + +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT +#ifdef DCSPRI_HAL_VADS_ROM_MLT_RAM +#define HAL_PLATFORM_RESET_ENTRY 0x00000100 +#else +#define HAL_PLATFORM_RESET_ENTRY 0xFFF00100 +#endif + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/include/plf_stub.h @@ -0,0 +1,97 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): pfine +// Contributors:jskov +// Date: 2001-11-29 +// Purpose: Platform HAL stub support for MPC8260 VADS board +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_powerpc_vads.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/ppc_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +externC int wpd_stub_get_char(void); +externC void wpd_stub_put_char(int); +#define HAL_STUB_PLATFORM_GET_CHAR cyg_hal_plf_serial_getc +#define HAL_STUB_PLATFORM_PUT_CHAR cyg_hal_plf_serial_putc + +//---------------------------------------------------------------------------- +// Stub initializer. +#ifdef MBX_SPECIFIC +externC void hal_mbx_set_led( int val ); +#ifdef CYG_HAL_STARTUP_ROM +# define HAL_STUB_PLATFORM_INIT() hal_mbx_set_led( 4 ) +// to distinguish eCos stub ROM ready state from either CygMon or app. +#endif +#endif + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/misc/redboot_RAM.ecm @@ -0,0 +1,83 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware vads ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_VADS current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_VADS current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00040000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0x700000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/misc/redboot_ROM.ecm @@ -0,0 +1,83 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware vads ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_VADS current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_VADS current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/misc/redboot_ROMRAM.ecm @@ -0,0 +1,87 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware vads ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC8260 current ; + package -hardware CYGPKG_HAL_POWERPC_VADS current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_DEVS_FLASH_VADS current ; + package CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option DCSPRI_HAL_VADS_ROM_MLT { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 { + inferred_value 1 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/src/hal_aux.c @@ -0,0 +1,106 @@ +//============================================================================= +// +// hal_aux.c +// +// HAL auxiliary objects and code; per platform +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1999-06-08 +// Purpose: HAL aux objects: startup tables. +// Description: Tables for per-platform initialization +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_mem.h> // HAL memory definitions +#include <cyg/infra/cyg_type.h> + +// The memory map is weakly defined, allowing the application to redefine +// it if necessary. The regions defined below are the minimum requirements. +CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = { + // Mapping for the Motorola MPC8260 development board + CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM + CYGARC_MEMDESC_NOCACHEGUARD( 0x04000000, 0x00400000 ), // Local Bus SDRAM + // The BCSR are actually only 8 registers, but they repeatedly map + // into the 1 MB space described here. + // The BAT register uses a Block Length of 4MB so that both the BCSRs + // and the IMMR space is Managed thru the MMU. In fact, the ATM UNI + // Proc. Control is also mapped into this block. + // See MPC8260 PowerQUICC II ADS User's Manual, p. 3-35, note 2 + CYGARC_MEMDESC_NOCACHE( 0x04500000, 0x00400000 ), // BCSR registers + CYGARC_MEMDESC_NOCACHE( 0xff800000, 0x00800000 ), // ROM region + + CYGARC_MEMDESC_TABLE_END +}; + +static volatile CYG_WORD *BCSR0 = (CYG_WORD *)0x04500000; +static volatile CYG_WORD *BCSR1 = (CYG_WORD *)0x04500004; +static volatile CYG_WORD *BCSR2 = (CYG_WORD *)0x04500008; + +// Some macros used for debugging +#define GREEN_LED_ON (*BCSR0 &= 0xFDFFFFFF) +#define RED_LED_OFF (*BCSR0 |= 0x01000000) +#define GREEN_LED_OFF (*BCSR0 |= 0x02000000) +#define RED_LED_ON (*BCSR0 &= 0xFEFFFFFF) + +//-------------------------------------------------------------------------- +// Platform init code. +void +hal_platform_init(void) +{ + /*----------------------------------------------------------------------*/ + /* Enable RS232 interface on the VADS board via BCSR1. BCSR1 is a Board */ + /* Control and Status Register that resides in a programmable logic */ + /* device. */ + /*----------------------------------------------------------------------*/ + + //*BCSR1 &= 0xFFFFFFFD; /* Assert the RS232EN_1/ bit */ + /* The Pilot revision of the MPC8260ADS board has moved the 8 bits + * in the 32 bit BCSR0 and BCSR1 from D24-D31 to D0-D7. + */ + *BCSR1 &= 0xFDFFFFFF; /* Assert the RS232EN_1/ bit */ + + hal_if_init(); +} + +// EOF hal_aux.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/src/hal_diag.c @@ -0,0 +1,302 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt, jskov +// Date: 1999-06-08 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt macros + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/mpc8260.h> +#ifdef CYGPKG_HAL_QUICC +#include <cyg/hal/quicc/quicc_smc1.h> +#endif + +// This prototype probably needs to be in an include file +void +cyg_hal_plf_serial_init(void); + + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + +/* This is where I will put the SCC1 initialization code */ +#define PF_ADDING_VIRTUAL_VECTORS +#ifdef PF_ADDING_VIRTUAL_VECTORS + cyg_hal_plf_serial_init(); +#else +# ifdef CYGPKG_HAL_QUICC + cyg_hal_plf_serial_init(); +# endif +#endif +} + + +#ifdef LATER +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +//----------------------------------------------------------------------------- +// Select default diag channel to use + +//#define CYG_KERNEL_DIAG_ROMART +//#define CYG_KERNEL_DIAG_SERIAL + +#if !defined(CYG_KERNEL_DIAG_SERIAL) +#define CYG_KERNEL_DIAG_SERIAL +#endif + +#ifdef CYGDBG_DIAG_BUF +// Keep diag messages in a buffer for later [re]display + +int enable_diag_uart = 1; +int enable_diag_buf = 1; +static char diag_buf[40960*4]; +static int diag_buf_ptr = 0; + +static void +diag_putc(char c) +{ + if (enable_diag_buf) { + diag_buf[diag_buf_ptr++] = c; + if (diag_buf_ptr == sizeof(diag_buf)) diag_buf_ptr--; + } +} + +void +dump_diag_buf(int start, int len) +{ + int i; + enable_diag_uart = 1; + enable_diag_buf = 0; + if (len == 0) len = diag_buf_ptr; + diag_printf("\nDiag buf\n"); + for (i = start; i < len; i++) { + hal_diag_write_char(diag_buf[i]); + } +} +#endif // CYGDBG_DIAG_BUF + + +//----------------------------------------------------------------------------- +// MBX board specific serial output; using GDB protocol by default: + + +#if defined(CYG_KERNEL_DIAG_SERIAL) + +t_PQ2IMM *IMM; + +void hal_diag_init(void) +{ + static int init = 0; + if (init) return; + init++; + + // hardwired base + //eppc = eppc_base(); + IMM = (t_PQ2IMM *) 0x04700000; + + // init the actual serial port + cyg_hal_plf_serial_init_channel(); +#ifdef CYGSEM_HAL_DIAG_MANGLER_GDB +#ifndef CYG_HAL_STARTUP_ROM + // We are talking to GDB; ack the "go" packet! + cyg_hal_plf_serial_putc('+'); +#endif +#endif +} + +void hal_diag_write_char_serial( char c ) +{ + unsigned long __state; + HAL_DISABLE_INTERRUPTS(__state); + cyg_hal_plf_serial_putc(c); + HAL_RESTORE_INTERRUPTS(__state); +} + +#if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN) +void hal_diag_write_char(char c) +{ +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + hal_diag_write_char_serial(c); +} + +#else // RAM start so encode for GDB + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + +#ifndef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + // only gobble characters if no interrupt handler to grab ^Cs + // is installed (which is exclusive with device driver use) + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + c = cyg_hal_plf_serial_getc(eppc); + + if( c == '+' ) + break; // a good acknowledge +#if 0 + if( c1 == 3 ) { + // Ctrl-C: breakpoint. + breakpoint(); + break; + } +#endif + // otherwise, loop round again +#else + break; +#endif + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + + } +} +#endif // NOT def CYG_HAL_STARTUP_ROM + +#if 0 +// These should not need to be prototyped here, but where???? +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data); + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); +#endif + +void hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(); +} + +#endif // CYG_KERNEL_DIAG_SERIAL + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG +#endif + +// EOF hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/vads/current/src/vads.S @@ -0,0 +1,1393 @@ +#============================================================================== +## +## vads.S +## +## MPC8260 VADS board hardware setup +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2002 Gary Thomas +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: wpd, gthomas +## Date: 2002-12-09 +## Purpose: VADS MPC8260 board hardware setup +## Description: This file contains any code needed to initialize the +## hardware on the Motorola VADS MPC8260 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/arch.inc> +#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */ +#------------------------------------------------------------------------------ + + .globl hal_hardware_init +hal_hardware_init: +// It is possible that the board may experience a soft reset, which +// will cause this hal_hardware_init routine to be called. As a +// result of the soft reset, the IMMR, memory controller, system +// protection logic, interrupt controller and parallel I/O pins are +// NOT reset (MPC8260 User Manual p 5-2), and therefor we do not want to +// run the setup in this routine. Luckily, a hard reset will clear +// the NHR bit (bit 15) of the HID0 register. We will check for this bit +// to be 0 (implying a hard reset). If it is 0, we will run the +// initialization. If non-zero, we will skip the initialization. +// +// If we do the initialization, then we must set the NHR bit so that +// next time we hit this point in the routine, we can determine the type +// of reset. +//#ifdef DCSPRI_HAL_VADS_ROM_MLT_RAM + // Today, we will totally skip over all of this if we are using + // the RAM memory layout +// b hardware_init_done +//#endif + + mfspr r22,CYGARC_REG_HID0 # Get contents of HID0 + rlwinm r23,r22,0,15,15 #shift r0 by 0, mask HID0 with 0x10000, store in r23 + cmpwi r23,0 # Compare r23 with 0 + bne hardware_init_done + + mfspr r31,CYGARC_REG_LR + + + #---------------------------------------------- + # Load the IMMR register with the base address + #---------------------------------------------- + + addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We add + # 0x10000 because using relative addressing + # in load and store instructions only allow a + # offset from the base of +/-32767. + addis r5,0,0x0470 + + addis r3,0,0x0F01 + +# The default IMMR base address was 0x0F0000000 as +# originally programmed into the Hard Reset +# Configuration Word. + stw r5,CYGARC_REG_IMM_IMMR(r3) + + + + mfspr r21,CYGARC_REG_HID0 # get HID0 in R21 + oris r21,r21,0x1 # Set bit 15 of HID0 (NHR) + + mtspr CYGARC_REG_HID0,r21 # load HID0 with NHR set + + + #******************************************* + # Main System Clock Configuration Registers + #******************************************* + + #------------------------------------------------------------------------- + # We only need to program the System Clock Control Register (SCCR). The + # System Clock Mode Register (SCMR) doesn t need to be programmed here + # because the MODCLK_HI bits in the Hard Reset Configuration Word and the + # MODCK pins dictate the values in the SCCR during power-on reset. + #------------------------------------------------------------------------- + + #------------------------------------------------------------------------- + # Program the System Clock Control Register (SCCR). + # + # - Bits 0 - 28 Reserved. Clear to 0. + # + # - CLPD (CPM Low Power Disable) = 0 = + # + # CPM does not enter low power mode when the core enters low power + # mode. + # + # - DFBRG (Division Factor of BRGCLK) = 01 - Divide by 8. + # + #------------------------------------------------------------------------- + + + addis r3,0,0x0000 + ori r3,r3,0x0001 # SCCR = 0x00000001 + stw r3,CYGARC_REG_IMM_SCCR(r4) + + #~~~~~~~~~~~~~~~~~~~~ + # Initialize the SIU + #~~~~~~~~~~~~~~~~~~~~ + + bl init_siu + + #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + # Initialize the memory controller and SDRAM + #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + bl init_memc + + mtspr CYGARC_REG_LR,r31 # restore original Link Register value + +hardware_init_done: + bclr 20,0 + + +######################################################################### +# Function: init_siu +# +# Description: Initializes the System Interface Unit +# +# History: +# +# +######################################################################### + +init_siu: + + #----------------------------------------------------------------------- + # Program the System Protection Control Register with the following + # values: + # + # - SWTC (Software Watchdog Timer Count) = 0xFFFF = programmed to max + # count value. + # + # - BMT (Bus Monitor Timing) = 0xFF = Set to max timeout period. + # + # - PBME (60x Bus Monitor Enable) = 1 = enabled. + # + # - LBME (Local Bus Monitor Enable) = 1 = enabled. + # + # - Bits 26-28 Reserved. Set to 0. + # + # - SWE (Software Watchdog Enabled) = 0 = disabled for now. User will + # have to enable this in a non-debug application. + # + # - SWRI (Software Watchdog Reset/Interrupt Select) = 1 = Software + # watchdog timeout or bus monitor time-out causes a soft reset. + # + # - SWP (Software Watchdog Prescale) = 1 = clock is prescaled. + #----------------------------------------------------------------------- + + addis r3,0,0xFFFF + ori r3,r3,0xFFC3 # SYPCR = 0xFFFFFFC3 + stw r3,CYGARC_REG_IMM_SYPCR(r4) + + + #------------------------------------------------------------------------- + # Program the Bus Configuration Register. The details are as follows: + # + # - EBM (External Bus Mode) = 0 = Single MPC8260 bus mode is assumed. + # + # - APD (Address Phase delay) = 001 = + # + # One address tenure wait states for address operations initiated by + # a 60x bus master. + # + # - L2C (Secondary Cache Controller) = 0 = No secondary cache controller + # is assumed. + # + # - L2D (L2 cache hit Delay) = 000 = This is a don t care because we re + # not using the L2 cache. + # + # - PLDP (PipeLine maximum Depth) = 0 = The pipeline max depth is one. + # + # - Bits 9-11 = Reserved. Set to 0. + # + # - ETM (Compatibility Mode enable) = 1 = Extended transfer mode is + # enabled. + # + # - LETM (Local Bus Compatibility Mode Enable) = 1 = + # + # Extended transfer mode is enabled on the local bus. + # + # - EPAR (Even Parity) = 0 = This is a do not care. + # + # - LEPAR (Local Bus Even Parity) = 0 = This is a do not care. + # + # - Bits 16-20 = Reserved. Set to 0. + # + # - EXDD (External Master Delay Disable) = 0 = + # + # The memory controller inserts one wait state between the assertion + # of TS and the assertion of CS when an external master accesses an + # address space controlled by the memory controller. + # + # - Bits 22-26 = Reserved. Set to 0. + # + # - ISPS (Internal Space Port Size) = 0 = + # + # MPC8260 acts as a 64-bit slave to external master accesses to its + # internal space. + # + # - Bits 28-31 = Reserved. Set to 0. + # + #------------------------------------------------------------------------- + + addis r3,0,0x100c + stw r3,CYGARC_REG_IMM_BCR(r4) + + #------------------------------------------------------------------------- + # Program the 60x Bus Arbiter Configuration Register. The details are as + # follows: + # + # - Bits 0-1 = Reserved. Set to 0. + # + # - DBGD (Data Bus Grant Delay) = Minimum of zero wait states for PowerPC + # master-initiated data operations. This + # is the minimum delay between TS/ and + # DBG/. + # + # - Bits 3 = Reserved. Set to 0. + # + # - PRKM (Parking Master) = 0010 = CPM is at a low request level for the + # parked master. + # + #------------------------------------------------------------------------- + + addi r3,0,0x0002 + stb r3,CYGARC_REG_IMM_PPC_ACR(r4) + + + #------------------------------------------------------------------------- + # Program the 60x Bus Arbitration-Level[High] Register. The priority for + # potential bus masters are defined by locating the value associated with + # a particular master from the PRKM field in the PPC_ACR register and + # inserting its value in the priority field. Priority field 0 is the + # highest priority and the lowest is Priority field 15 in the PPC_ALRH + # register. + # + # - Priority Field 0 = 0000 = CPM high request level + # + # - Priority Field 1 = 0001 = CPM middle request level + # + # - Priority Field 2 = 0010 = CPM low request level + # + # - Priority Field 3 = 0110 = Internal Core + # + # - Priority Field 4 = 0111 = External Master 1 + # + # - Priority Field 5 = 1000 = External Master 2 + # + # - Priority Field 6 = 1001 = External Master 3 + # + # - Priority Field 7 = 0011 = Reserved + # + #------------------------------------------------------------------------- + + addis r3,0,0x0126 + ori r3,r3,0x7893 + stw r3,CYGARC_REG_IMM_PPC_ALRH(r4) + + + #------------------------------------------------------------------------ + # + # First program the SIUMCR. The details are as follows: + # + # - BBD (Bus Busy Disable) = 0 = [ABB/]/[IRQ2] pin is ABB/ and [DBB/]/IRQ2 + # pin is DBB/. + # + # - ESE (External Snoop Enable = 0 = [GPL/]/[IRQ1/] pin is IRQ1/ + # + # - PBSE (Parity Byte Select Enable) = 0 = Parity byte select is disabled. + # + # - CDIS (Core DISable) = 0 = The PowerQUICCII CPU core is enabled. + # + # - DPPC (Data Parity Pins Configuration) = 10 = + # + # Gives the following pin meanings: DP(0)|RSRV/|EXT_BR2/ = RSRV/ + # DP(1)|IRQ1/|EXT_BG2/ = IRQ1/ + # DP(2)|TLBISYNC/|IRQ2/ = TLBISYNC/ + # DP(3)|IRQ3/ = IRQ3/ + # DP(4)|IRQ4/ = IRQ4/ + # DP(5)|TBEN/|IRQ5 = TBEN/ + # DP(6)|CSE(0)|IRQ6/ = CSE(0) + # DP(7)|CSE(1)|IRQ7/ = CSE(1) + # + # - L2CPC (L2 Cache Pins Configuration) = 00 = + # + # Gives the following pin meanings: CI/|BADDR(29)|IRQ2/ = CI/ + # WT/|BADDR(30)|IRQ3/ = WT/ + # L2_HIT/|IRQ4 = L2_HIT/ + # + # CPU_BG/|BADDR(31) + # |IRQ5/ = CPU_BG/ + # + # - LBPC (Local Bus Pins Configuration) = 00 = + # + # Local Bus pins function as local bus. + # + # - APPC (Address Parity Pins Configuration) = 10 = + # + # Gives the following pin meanings: MODCK1|AP(1)|TC(0) = BNKSEL(0) + # MODCK2|AP(2)|TC(1) = BNKSEL(1) + # MODCK3|AP(3)|TC(2) = BNKSEL(2) + # IRQ7/|APE/|INT_OUT/ = IRQ7/+INT_OUT/ + # CS11/|AP(0) = CS11/ + # + # - CS10PC (Chip Select 10-pin Configuration) = 00 = + # + # CS10/|BCTL1/|DBG_DIS/ = CS10/ + # + # - BCTLC (Buffer Control Configuration) = 00 = + # + # BCTL0 pin is used as W|R/ control. BCTL1 is used as OE/ control if + # BCTL1 was connected to its alternate pin. + # + # - MMR (Mask Masters Requests) = 00 = No masking on bus request lines. + # + # - LPBSE (Local Bus Parity Byte Select Enable) = 0 + # + # Parity byte select is disabled. + # + # Bits 19-31 are reserved and set to 0. + # + #------------------------------------------------------------------------ + + #-------------------------------------------------------------------------- + # Program the 60x Bus Transfer Error Status and Control Register 1. The + # details are as follows: + # + # - DMD (Data Errors Disable) = 1 = + # + # Disable all data errors on the 60x bus. Also parity single and double + # ECC error. + # + # - All other bits are either status or reserved bits. All reserved bits + # should be set to 0. + #-------------------------------------------------------------------------- + + addis r3,0,0x0000 + ori r3,r3,0x4000 + stw r3,CYGARC_REG_IMM_TESCR1(r4) + + #-------------------------------------------------------------------------- + # Program the Local Bus Transfer Error Status and Control Register 1. The + # details are as follows: + # + # - DMD (Data Errors Disable) = 1 = + # + # Disable parity errors on the Local bus. + # + # - All other bits are either status or reserved bits. All reserved bits + # should be set to 0. + #-------------------------------------------------------------------------- + + addis r3,0,0x0000 + ori r3,r3,0x4000 + stw r3,CYGARC_REG_IMM_LTESCR1(r4) + + + #------------------------------------------------------------------------- + # First, program the Memory Periodic Timer Prescaler Register (MPTPR). + # Finding the value to this ties in with the desired SDRAM Refresh + # Timer (PSRT) value and the required Refresh Command interval for + # refreshing each row. The Refresh Command interval is found by + # determining the number of rows on the SDRAM device. In this case + # its 2048. The "total time between refresh" value in the AC characteristic + # section of the data sheet is 32.8 msec. This value is divided by the + # number of rows to give the number of Refresh commands that needs to be + # sent in a 32.8 msec interval. This value is 32.8 Msec/2048 = 16.02 usec. + # Due to probable contention from time to time with other memory + # controller bus requests, lets make the refresh command interval to be + # around 15.5 usec. + # + # Now let us divide the input VADs system clock by 64 (somewhat arbitrary). + # If this is our prescaler value then the input frequency to the Refresh + # timer is 1.031 Mhz. Using the formula: + # + # Timer Period = PSRT + # ---- + # F(MPTC) + # + # - Where F(MPTC) is the output from the MPT Prescaler block + # or 66 Mhz/64 = 1.031 Mhz. + # + # - Timer Period = 15.5 usec + # + # The PSRT value would be approximately 16. + # + # The clock distribution block diagram looks like this: + # + # ---------- ------------- ----------- ------------- + # | Clock | | MPT | | SDRAM | | Refresh | + # | Gen. |-----| Prescaler |---------| Refresh |----| Command | + # | 66 Mhz | ------------- | Timer | | Logic in | + # | on Vads | ----------- | Mem.Cont. | + # | Board | ------------- + # ----------- + # + #------------------------------------------------------------------------- + + addi r5,0,0x4000 # load 0x40 or 64 into the PTP field of MPTPR + sth r5,CYGARC_REG_IMM_MPTPR(r4) # store half word - bits[16-31] + + + + #----------------------- + # return from init_siu + #----------------------- + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_memc +# +# Description: +# +# The following registers directly control the memory controllers +# operation: +# +# BR0-BR11 - Base Register Banks 0-11 +# OR0-OR11 - Option Register Banks 0-11 +# PSDMR - 60x bus SDRAM machine mode register +# LSDMR - Local bus SDRAM machine mode register +# MAMR - UPMA mode register +# MBMR - UPMB mode register +# MCMR - UPMC mode register +# MDR - Memory data register +# MAR - Memory address register +# MPTPR - Memory periodic timer pre-scaler register +# PURT - 60x bus assigned UPM refresh timer +# PSRT - 60x bus assigned SDRAM refresh timer +# LURT - Local Bus assigned UPM refresh timer +# LSRT - Local Bus assigned SDRAM refresh timer +# +# This example will program the following registers. The rest will remain at +# their default values. +# +# BR0 - Base Register for Flash Memory +# OR0 - Option Register for Flash Memory +# BR1 - Base Register for BCSR (Board Control and Status Registers) +# OR1 - Option Register for BCSR +# BR2 - Base Register for 60x SDRAM +# OR2 - Option Register for 60x SDRAM +# BR3 - Base Register for 60x Local Bus SDRAM +# OR3 - Option Register for 60x Local Bus SDRAM +# PSDMR - 60x bus SDRAM machine mode register +# LSDMR - Local bus SDRAM machine mode register +# MPTPR - Memory periodic timer pre-scaler register +# PSRT - 60x bus assigned SDRAM refresh timer +# LSRT - Local Bus assigned SDRAM refresh timer +# +# +# History: +# +######################################################################### + +init_memc: + + mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers + # value will be restored so that this function + # can return to the calling address. + + bl init_flash # 8 Mbyte of flash memory + + bl init_bcsr # Board Control and Status Registers + + bl init_local_sdram # Local Bus SDRAM + + bl init_60x_sdram # Main 60x Bus SDRAM + + #----------------------- + # return from init_memc + #----------------------- + + mtspr CYGARC_REG_LR,r30 # restore original Link Register value + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + + +############################################################################ +# Function: init_flash +# +# Description: This function programs Base Register 0 and Option Register 0 +# designating bank 0 for the 8Mbyte flash SIMM on the VADS +# board. Programming these two registers describes how the +# MPC8260 will inter-operate with this memory space and thus +# this memory device. +# +# History: +# +############################################################################ + +init_flash: + + #------------------------------------------------------------------------- + # Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + # flash that resides on the MPC8260 VADS board. + # The particulars are defined here. + # + # BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- +#define nPFHACK +#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000 + addis r3,0,0xFE00 # R3 holds the value temporarily +#else + addis r3,0,0xFF80 # R3 holds the value temporarily +#endif + ori r3,r3,0x1801 + #------------------------------------------------------------------------- + # Option Register 0 (OR0) for GPCM use: further flash definitions + # + # AM (Address Mask) = 0xFF80+0b = We have masked the upper 9 bits which + # defines a 8 Mbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter + # of a clock early. + # + # ACS (Address To Chip-Select Setup) = 00 = CS/ is output the same time as + # the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0011 = Add a 3 clock cycle wait state + # + # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated + # internally by the memory + # controller unless GTA/ is + # asserted earlier externally. + # + # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 1 = + # + # Extended hold time is generated by the memory controller. An idle + # clock cycle is inserted between a read access from the current bank + # and any write or read access to a different bank. + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + +#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000 + addis r5,0,0xFE00 # R5 holds the value temporarily +#else + addis r5,0,0xFF80 # R5 holds the value temporarily +#endif + ori r5,r5,0x0836 + + #------------------------------------------------------------------------ + # It is important to note the order in which OR0 and BR0 are programmed. + # When coming out of reset and CS0 is the global chip select, OR0 MUST be + # programmed AFTER BR0. In all other cases BRx would be programmed after + # ORx. + #------------------------------------------------------------------------ + + #------------------ + # Write the values + #------------------ + + stw r3,CYGARC_REG_IMM_BR0(r4) + stw r5,CYGARC_REG_IMM_OR0(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_bcsr +# +# Description: This function programs Base Register 1 and Option Register 1 +# designating bank 1 for BCSR0, BCSR1, and BCSR2 on the VADS +# board. BCSR stands for Board Control and Status Register. +# This space is treated as general I/O. Programming the +# following 2 registers describes how the MPC8260 will inter- +# operate with this memory space. +# +# History: +# +# Jan 9/99 jay +# +######################################################################### + +init_bcsr: + + + #------------------------------------------------------------------------- + # Base Register 1 (BR1): Bank 1 is assigned to the Board Control and + # Status Registers (BCSRs). There are 3 + # that resides on the MPC8260 VADS board. + # The particulars are defined here. + # + # BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value + # represents the upper 17 bits of the base address. + # + # Bits 17-18 reserved. = 00 + # + # PS (Port Size) = 11b = 32 bit port size + # + # DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # WP (Write Protect) = 0 = both read and write accesses are allowed + # + # MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM) + # for 60x bus Selected + # + # EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by + # the memory controller + # according to MSEL. + # + # ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # DR (Delayed Read) = 0 = Normal operation. + # + # V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0450 # R3 holds the value temporarily + ori r3,r3,0x1801 + + #------------------------------------------------------------------------- + # Option Register 1 (OR1) for GPCM use: further BCSR definitions + # + # AM (Address Mask) = 0xFFFF +1b = We have masked the upper 17 bits which + # which defines a 32 Kbyte memory block. + # + # Bits 17-19 Reserved - set to 000. + # + # CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally. + # + # ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same + # time as the addr lines. + # + # Bit 23 Reserved - set to 0. + # + # SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state + # + # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated + # internally by the memory + # controller unless GTA/ is + # asserted earlier externally. + # + # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM. + # + # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is + # generated by the memory + # controller + # + # Bit 31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFFFF # R5 holds the value temporarily + ori r5,r5,0x8010 + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR1(r4) + stw r3,CYGARC_REG_IMM_BR1(r4) + + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + + +######################################################################### +# Function: init_60x_sdram +# +# Description: This function programs the 16 Mbyte SDRAM DIMM on the VADS +# board. This memory functions as the RAM for the 603 core and +# is connected to the 60x bus. Base and Option Register 2 are +# used as well as the SDRAM Machine #1 and Chip Select #2. +# +# History: +# +# Jan /9/99 jay Initial Release +# +######################################################################### + +init_60x_sdram: + + + ################## + # Program Refresh + ################## + + + #------------------------------------------------------------------------- + # Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT). + #------------------------------------------------------------------------- + + addi r5,0,0x0010 # load 0x10 or 16 + stb r5,CYGARC_REG_IMM_PSRT(r4) # store byte - bits[24-31] + + + ######################### + # Program Bank Registers + ######################### + + + #------------------------------------------------------------------------- + # Base Register 2 (BR2): Bank 2 is assigned to the 16 Mbyte 60x SDRAM DIMM + # that resides on the MPC8260 VADS board. The + # particulars are defined here. + # + # - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This + # value represents the upper 17 bits of the base + # address. + # + # - Bits 17-18 reserved. = 00 = cleared to 0. + # + # - PS (Port Size) = 00b = 64 bit port size + # + # - DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # - WP (Write Protect) = 0 = both read and write accesses are allowed + # + # - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected + # + # - EMEMC (External Memory Controller Enable) = 0 = + # + # Accesses are handled by the memory controller according to MSEL. + # + # - ATOM (Atomic Operation) = 00 = The address space controlled by the + # memory controller bank is not used for + # atomic operations. + # + # - DR (Delayed Read) = 0 = Normal operation. + # + # - V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0000 # R3 holds the value temporarily + ori r3,r3,0x0041 + + #------------------------------------------------------------------------- + # Option Register 2 (OR2) for SDRAM Machine use: further SDRAM definitions + # + # - USDAM (Upper SDRAM Address Mask) = 11111b = + # + # We have masked all 5 bits which defines a maximum 128 Mbyte block. + # Note that since the maximum SDRAM block size is 128 Mbyte, this field + # should always be 11111b. + # + # - SDAM (SDRAM Address Mask) = 1110000b = 16 Mbyte block. + # + # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size. + # + # - BPD (Banks Per Device) = 00 = 2 internal banks per device. + # + # - ROWST (Row Start Address Bit) = 011 = A9 being the row start address + # bit. + # + # - Bit 22 Reserved - set to 0. + # + # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines. + # + # - PMSEL (Page Mode Select) = 1 = Reserved + # + # - IBID (Internal bank interleaving within same device disable) = 0 = + # + # Bank interleaving allowed. + # + # - AACKR (AACK/ release) = 0 = Normal operation. + # + # - Bits 29-31 Reserved - set to 0. + #------------------------------------------------------------------------- + +#define nCYGHWR_HAL_POWERPC_VADS_64MB_DIMM +#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM + addis r5,0,0xFC00 # R5 holds the value temporarily + ori r5,r5,0x28E0 +#else + addis r5,0,0xFF00 # R5 holds the value temporarily + ori r5,r5,0x0CA0 +#endif + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR2(r4) + stw r3,CYGARC_REG_IMM_BR2(r4) + + + ########################################### + # Perform Initialization sequence to SDRAM + ########################################### + + #------------------------------------------------------------------------- + # Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used + # to configure operations pertaining to SDRAM. Program the PSDMR, turning + # off refresh services and changing the SDRAM operation to "Precharge all + # banks". Then do a single write to an arbitrary location. Writing 0xFF + # to address 0 will do the trick. + # + # - Bit 0 is reserved. Set to 0. + # + # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit + # will be set later in this function as a + # last step. + # + # - OP (SDRAM Operation) = 000 = Precharge all banks. + # + # - SDAM (Address Multiplex Size = 001 = + # + # Coming up the value for this field is one of the most confusing + # and non-intuitive steps in the SDRAM programming process. This is how + # it works... The SDRAM device is a 16 Mbit DIMM that has a data width + # of 64 bits or 8 bytes. The bank size is 64 bits so the SDRAM will + # ignore the least significant 3 bits. Given this information and + # knowing that the number of row address lines is 11 and the column + # addresses is 9 and also knowing that the row addresses must be + # multiplexed, write out the following: + # + # addresses ignored by SDRAM : A29 A30 A31 + # + # column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28 + # + # row addresses: A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 + # + # When the memory controller multiplexes the addresses it puts the + # column addresses out on the actual physical pins that matches its + # corresponding effective address bits. + # + # According to the SDRAM Address Multiplexing table in the memory + # controller section of the manual, SDAM selection of 001 fits the + # address layout given above. Because its the row that is multiplexed on + # designated column address pins, the row addresses are put out on the + # following column pins: + # + # column ----------------------> A20 A21 A22 A23 A24 A25 A26 A27 A28 + # | | | | | | | | | + # row address -----------> A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 + # on corresponding + # column pins. + # + # Column pins A19, A18, and A17 were not connected to the DIMM device so + # A9 and A10 as well as the bank select address which is A8 are put out + # on their respective pins because it was decided that these address + # pins would be directly connected to the DIMM. That is, A10 of the real + # address is put out on the A10 pin, A9 on the A9 pin, etc. + # + # As a final note on this subject, the row address is output on the + # address bus first on the actual column address pins according to the + # multiplexing scheme in the SDRAM address multiplexing table, then the + # column address follows which makes up the most significant part of the + # real address which is connected to the memory device. + # + # Any entries in the multiplexing table that show a "-" means nothing is + # multiplexed on the physical pins shown on the top row of the table + # and therefore any part of the row address will also show up on its + # respective physical pin if this pin is not used for multiplexing. For + # example, for a SDAM of 001, the multiplexing table shows that A13 + # through A0 are not multiplexed because they have "-" in their + # respective boxes. This means that A13 through A5 of the real address + # will show up multiplexed on address pins A22 through A14 and A13 + # through A0 of the real address will also show up on their actual + # respective physical pins. + # + # - BSMA (Bank Select Multiplexed Address line) = 011 = A15-A17 + # + # BSMA determines how BNKSEL[0:2] will operate. This SDRAM has only 2 + # banks, so only BANKSEL2 is of concern because its the least + # significant bit. BANKSEL2 should be programmed to operate as physical + # pin A17. Because we are multiplexing 9 column addresses, it will + # actually behave as A8. + # + # - SDA10 ("A10 Control") = 011 = + # + # A9 is the address pin used for the activate command. The A10/AP pin + # the SDRAM needs to act as a command line during on phase of the + # access and as an address line in the other phase. The SDA10 pin on + # MPC8260 takes care of this function. Instead of connecting the + # A10/AP pin to A9 on the address bus, connect it to SDA10 and program + # SDA10 to function as A9. + # + # - RFRC (ReFresh ReCovery) = 101 = + # + # Once a refresh request is granted, the memory controller begins + # issuing auto-refresh commands to each device associated with the + # refresh timer in one clock intervals. After the last REFRESH + # command is issued, the memory controller waits for 7 clocks before + # the ACTIVATE command and before normal read/write operations can + # resume. + # + # - PRETOACT (PREcharge TO ACTivate interval) = 011 = + # + # Wait 3 clock cycles before an activate command. This parameter is + # determined by the requirements of the SDRAM at a particular clock + # speed. + # + # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles. + # + # - BL (Burst Length) = 0 = SDRAM burst length is 4. This is programmed + # into the SDRAM via the MRS commmand. + # + # - LDOTOPRE (Last Data Out TO PREcharge) = 01 = + # + # The delay required from the last data out to precharge state is 1 clock + # cycle. This parameter is determined by the requirements of the SDRAM at + # a particular clock speed. + # + # - WRC (Write Recovery Time) = 01 = + # + # Time needed to elapse before another operation is 1 clock cycle. This + # parameter is determined by the requirements of the SDRAM at a + # particular clock speed. + # + # - EAMUX (External Address MUltipleXing) = 0 No external address + # multiplexing. + # + # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control + # lines. + # + # - CL (CAS Latency) = 10 = + # + # CAS latency is 2. Two cycles after column address is registered, data + # is valid. This parameter is determined by the requirements of the + # SDRAM at a particular clock speed. + # + #------------------------------------------------------------------------- + +#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM + addis r3,0,0x294E + ori r3,r3,0xB452 +#else + addis r3,0,0x296E + ori r3,r3,0xB452 +#endif + stw r3,CYGARC_REG_IMM_PSDMR(r4) + addis r0,0,0 + + addi r3,0,0x00FF # Load 0x000000FF into r3 + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + + #------------------------------------------------------------------------- + # Program the PSDMR keeping refresh services off and changing the + # SDRAM operation to "CBR Refresh". This step is responsible for issuing + # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine + # by issuing the CBR Refresh command by programming the OP field of the + # PSDMR register and writing 0xFF 8 times to an arbitrary address. + #------------------------------------------------------------------------- + +#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM + addis r3,0,0x094E + ori r3,r3,0xB452 +#else + addis r3,0,0x096E + ori r3,r3,0xB452 +#endif + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + #------------------------------------------ + # Loop 8 times, writing 0xFF to address 0 + #------------------------------------------ + + addi r6,0,0x0008 + mtspr CYGARC_REG_CTR,r6 # Load CTR with 8. The CTR special purpose + # is spr 9 + + addi r3,0,0x00FF # Load 0x000000FF into r3 + +write_loop: + + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + bc 16,0,write_loop # Decrement CTR, then branch if the decremented CTR + # is not equal to 0 + + #------------------------------------------------------------------------- + # Program the PSDMR again turning off refresh services and changing the + # SDRAM operation to "Mode Register Write". Then do a single write to an + # arbitrary location. The various fields that will be programmed in the + # mode register on the SDRAM were specified in fields of the PSDMR, like + # the BR (burst length) and the CL (CAS Latency) field. + #------------------------------------------------------------------------- + +#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM + addis r3,0,0x194E + ori r3,r3,0xB452 +#else + addis r3,0,0x196E + ori r3,r3,0xB452 +#endif + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + addi r3,0,0x00FF # Load 0x000000FF into r3 + stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31] + + #------------------------------------------------------------------------- + # Program the PSDMR one last time turning on refresh services and changing + # the SDRAM operation to "Normal Operation". + #------------------------------------------------------------------------- + +#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM + addis r3,0,0x414E + ori r3,r3,0xB452 +#else + addis r3,0,0x416E + ori r3,r3,0xB452 +#endif + stw r3,CYGARC_REG_IMM_PSDMR(r4) + + #---------------------------- + # return from init_60x_sdram + #---------------------------- + + bclr 20,0 # jump unconditionally to effective address in Link + # register + + +######################################################################### +# Function: init_local_sdram +# +# Description: This function programs the 4 Mbytes of SDRAM on the Local +# Bus on the VADS board. This memory functions as storage for +# connection tables and data buffers for the CPM peripherals. +# Base and Option Register 4 are used. SDRAM Machine #2 +# and Chip Select #4 is used in the memory controller. +# +# History: +# +# Jan 9/99 jay +# +######################################################################### + +init_local_sdram: + + ################## + # Program Refresh + ################## + + #------------------------------------------------------------------------- + # Program the Local Bus Assigned SDRAM Refresh Timer (LSRT). Note that the + # MPTPR register was programmed in the init_siu function which also + # dictates the frequency to the LSRT block. Because the frequency rating + # for the local bus SDRAM is same as the 60x SDRAM DIMM, only the LSRT + # needs to be programmed and it is going to be the same as the PSRT + # register. + #------------------------------------------------------------------------- + + addi r5,0,0x0010 # load 0x10 or 16 + stb r5,CYGARC_REG_IMM_LSRT(r4) # store byte - bits[24-31] + + + ######################### + # Program Bank Registers + ######################### + + + #------------------------------------------------------------------------- + # Base Register 4 (BR4): Bank 4 is assigned to the 4 Mbyte Local SDRAM + # bank that resides on the MPC8260 VADS board. The + # particulars are defined here. + # + # - BA (Base Address) = 0x0400+0b for a total of 17 address bits. This + # value represents the upper 17 bits of the base + # address. + # + # - Bits 17-18 reserved. = 00 = cleared to 0. + # + # - PS (Port Size) = 11b = 32 bit port size + # + # - DECC (Data Error Correction and Checking) = 00 = Data errors checking + # Disabled. + # + # - WP (Write Protect) = 0 = both read and write accesses are allowed + # + # - MS (Machine Select) = 011 = SDRAM Machine for Local bus Selected + # + # - EMEMC (External Memory Controller Enable) = 0 = + # + # Accesses are handled by the memory controller according to MSEL. + # + # - ATOM (Atomic Operation) = 00 = + # + # The address space controlled by the memory controller bank is not + # used for atomic operations. + # + # - DR (Delayed Read) = 0 = Normal operation. + # + # - V (Valid Bit) = 1 = Valid bit set + #------------------------------------------------------------------------- + + addis r3,0,0x0400 # R3 holds the value temporarily + ori r3,r3,0x1861 + + #------------------------------------------------------------------------- + # Option Register 4 (OR4) for SDRAM Machine use: further SDRAM definitions + # + # - USDAM (Upper SDRAM Address Mask) = 11111b = + # + # We have masked all 5 bits which defines a maximum 128 Mbyte block Note + # that since the maximum SDRAM block size is 128 Mbyte, this field + # should always be 11111b. + # + # - SDAM (SDRAM Address Mask) = 1111100b = 4 Mbyte block. + # + # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size. + # + # - BPD (Banks Per Device) = 00 = 2 internal banks per device. + # + # - ROWST (Row Start Address Bit) = 101 = A11 being the row start address + # bit. + # + # - Bit 22 Reserved - set to 0. + # + # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines. + # + # - PMSEL (Page Mode Select) = 0 = back-to-back page mode (normal + # operation). + # + # - IBID (Internal bank interleaving within same device disable) = 0 = + # + # Bank interleaving allowed. + # + # - AACKR (AACK/ release) = 0 = Normal operation. + # + # - Bits 29-31 Reserved - set to 0. + #------------------------------------------------------------------------- + + addis r5,0,0xFFC0 # R5 holds the value temporarily + ori r5,r5,0x1480 + + #------------------ + # Write the values + #------------------ + + stw r5,CYGARC_REG_IMM_OR4(r4) + stw r3,CYGARC_REG_IMM_BR4(r4) + + + ########################################### + # Perform Initialization sequence to SDRAM + ########################################### + + #------------------------------------------------------------------------- + # Program the Local SDRAM Mode Registr (LSDMR). This register is used + # to configure operations pertaining to SDRAM on the Local bus. Turn off + # refresh services and change the SDRAM operation to "Precharge all banks". + # Then do a single write to an arbitrary location. Writing 0 top + # address 0 will do the trick. + # + # - Bit 0 is reserved. Set to 0. + # + # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit + # will be set later in this function as a + # last step. + # + # - OP (SDRAM Operation) = 101 = Precharge all banks. + # + # - SDAM (Address Multiplex Size = 000 = + # + # Coming up the value for this field is one of the most confusing + # and non-intuitive steps in the SDRAM programming process. This is how + # it works... The SDRAM device is a 4 Mbit chip set that has a data + # width of 32 bits or 4 bytes so the SDRAM will ignore the least + # significant 2 bits. Given this information and knowing that the + # number of row address lines is 11 and the column addresses is 8 and + # also knowing that the row addresses must be multiplexed, write out the + # following: + # + # addresses ignored by SDRAM : A30 A31 + # + # column addresses: A22 A23 A24 A25 A26 A27 A28 A29 + # + # row addresses: A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 + # + # When the memory controller multiplexes the addresses it puts the + # column addresses out on the actual physical pins that matches its + # corresponding effective address bits. + # + # According to the SDRAM Address Multiplexing table in the memory + # controller section of the manual, SDAM selection of 000 fits the + # address layout given above. Because the row is what is multiplexed + # on designated column address pins, the row addresses are put out on the + # following column pins: + # + #. 8 column addresses + # | + # column ------------->A19 A20 A21|A22 A23 A24 A25 A26 A27 A28 A29 + # | | | | | | | | | | | + #. 11 row addresses---->A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 + # on corresponding + # column pins. + # + # The row address is output on the address bus first, then the column + # address. + # + # - BSMA (Bank Select Multiplexed Address line) = 100 = A16-A18 + # + # For Local bus accesses, this field is a "do not care". BNKSEL[0:2] + # are associated with this field and these pins are only used for + # 60x compatible mode for 60x bus transactions. + # + # - SDA10 ("A10 Control") = 001 = A11 is the address pin used for the + # activate command. + # + # - RFRC (ReFresh ReCovery) = 101 = + # + # Once a refresh request is granted, the memory controller begins + # issuing auto-refresh commands to each device associated with the + # refresh timer in one clock intervals. After the last REFRESH + # command is issued, the memory controller waits for 7 clocks before + # the ACTIVATE command and before normal read/write operations can + # resume. + # + # - PRETOACT (PREcharge TO ACTivate interval) = 010 = + # + # Wait 2 clock cycles before an activate command. + # + # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles. + # + # - BL (Burst Length) = 1 = SDRAM burst length is 8. This is programmed + # into the SDRAM via the MRS commmand. + # + # - LDOTOPRE (Last Data Out TO PREcharge) = 00 = + # + # The delay required from the last data out to precharge state is 0 clock + # cycles. + # + # - WRC (Write Recovery Time) = 01 = + # + # Time needed to elapse before another operation is 1 clock cycle. + # + # - EAMUX (External Address MUltipleXing) = 0 No external address + # multiplexing. + # + # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control + # lines. + # + # - CL (CAS Latency) = 10 = CAS latency is 2. Two cycles after column + # address is registered, data is valid. + # + #------------------------------------------------------------------------- + + addis r3,0,0x2886 + ori r3,r3,0xA522 + stw r3,CYGARC_REG_IMM_LSDMR(r4) + + addis r2,0,0x0400 + addi r3,0,-1 + stb r3,0(r2) # Write 0xFF to address 0x04000000 + + + #------------------------------------------------------------------------- + # Program the LSDMR keeping refresh services off and changing the + # SDRAM operation to "CBR Refresh". This step is responsible for issuing + # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine + # by issuing the CBR Refresh command by programming the OP field of the + # PSDMR register and writing 0xFF 8 times to an arbitrary address. + #------------------------------------------------------------------------- + + addis r3,0,0x0886 + ori r3,r3,0xA522 + stw r3,CYGARC_REG_IMM_LSDMR(r4) + + #-------------------------------------------------- + # Loop 8 times, writing 0xFF to address 0x04000000 + #-------------------------------------------------- + + addis r6,0,0 + ori r6,r6,8 + mtspr CYGARC_REG_CTR,r6 # Load CTR with 8. + + addi r3,0,-1 # Load 0xFs into r3 + +write_loop1: + + stb r3,0(r2) # Write 0 to address 0x04000000 + + bc 16,0,write_loop1 # Decrement CTR, then branch if the decremented CTR + # is not equal to 0 + + #------------------------------------------------------------------------- + # Program the LSDMR again turning off refresh services and changing the + # SDRAM operation to "Mode Register Write". Then do a single write to an + # arbitrary location. The various fields that will be programmed in the + # mode register on the SDRAM were specified in fields of the LSDMR, like + # the BR (burst length) and the CL (CAS Latency) field. + #------------------------------------------------------------------------- + + addis r3,0,0x1886 + ori r3,r3,0xA522 + stw r3,CYGARC_REG_IMM_LSDMR(r4) + + addi r3,0,-1 + stb r3,0(r2) # Write 0xFF to address 0x04000000 + + #------------------------------------------------------------------------- + # Program the LSDMR one last time turning on refresh services and changing + # the SDRAM operation to "Normal Operation". + #------------------------------------------------------------------------- + + addis r3,0,0x4086 + ori r3,r3,0xA522 + stw r3,CYGARC_REG_IMM_LSDMR(r4) + + #------------------------------ + # return from init_local_sdram + #------------------------------ + + bclr 20,0 # jump unconditionally to effective address in Link + # register + +#------------------------------------------------------------------------------ +# end of vads.S