Mercurial > flash_v2
changeset 887:bcaf5c94f174
Use GCC/linker construct for buffer alignment
| author | gthomas |
|---|---|
| date | Fri, 28 Mar 2003 18:21:02 +0000 |
| parents | a6c0f4a333e5 |
| children | 237e9c388bd6 |
| files | packages/devs/eth/powerpc/fec/current/ChangeLog packages/devs/eth/powerpc/fec/current/src/if_fec.c packages/devs/eth/powerpc/quicc/current/ChangeLog packages/devs/eth/powerpc/quicc/current/src/if_quicc.c packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c |
| diffstat | 5 files changed, 34 insertions(+), 35 deletions(-) [+] |
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--- a/packages/devs/eth/powerpc/fec/current/ChangeLog +++ b/packages/devs/eth/powerpc/fec/current/ChangeLog @@ -1,8 +1,8 @@ 2003-03-28 Gary Thomas <gary@mlbassoc.com> * src/if_fec.c: Use new CPM/DPRAM buffer allocation scheme. Also, - better handling when aligning buffers to cache lines. - + better handling when aligning buffers to cache lines. + 2003-01-20 Gary Thomas <gary@mlbassoc.com> * cdl/fec_eth_drivers.cdl: Increase number of allowed buffers.
--- a/packages/devs/eth/powerpc/fec/current/src/if_fec.c +++ b/packages/devs/eth/powerpc/fec/current/src/if_fec.c @@ -79,12 +79,10 @@ #include "fec.h" // Align buffers on a cache boundary -#define CACHE_ALIGN(b) (((unsigned long)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1)) - -#define RxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE+HAL_DCACHE_LINE_SIZE -#define TxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE+HAL_DCACHE_LINE_SIZE -static unsigned char fec_eth_rxbufs[RxBUFSIZE]; -static unsigned char fec_eth_txbufs[TxBUFSIZE]; +#define RxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE +#define TxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE +static unsigned char fec_eth_rxbufs[RxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char fec_eth_txbufs[TxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); static struct fec_eth_info fec_eth0_info; static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x7A, 0xBA}; @@ -296,8 +294,8 @@ fec_eth_reset(struct eth_drv_sc *sc, uns qi->rbase = qi->rxbd = qi->rnext = rxbd; qi->txactive = 0; - RxBUF = (unsigned char *)CACHE_ALIGN(&fec_eth_rxbufs[0]); - TxBUF = (unsigned char *)CACHE_ALIGN(&fec_eth_txbufs[0]); + RxBUF = &fec_eth_rxbufs[0]; + TxBUF = &fec_eth_txbufs[0]; // setup buffer descriptors for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM; i++) {
--- a/packages/devs/eth/powerpc/quicc/current/ChangeLog +++ b/packages/devs/eth/powerpc/quicc/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-28 Gary Thomas <gary@mlbassoc.com> + + * src/if_quicc.c: Align data buffers on cache boundary. + 2003-03-14 Nick Garnett <nickg@calivar.com> * src/if_quicc.c: Fixed several bugs, mostly dealing with getting
--- a/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c +++ b/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c @@ -87,9 +87,9 @@ #include "quicc_eth.h" static unsigned char quicc_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM] - [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE]; + [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM] - [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE]; + [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); static struct quicc_eth_info quicc_eth0_info; static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8};
--- a/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c +++ b/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @@ -65,9 +65,6 @@ #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC -// macro for aligning buffers to cache lines -#define ALIGN_TO_CACHELINES(b) ((cyg_uint8 *)(((CYG_ADDRESS)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1))) - #include "quicc_smc_serial.h" typedef struct quicc_sxx_serial_info { @@ -140,8 +137,8 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c ); #endif -static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE+HAL_DCACHE_LINE_SIZE]; -static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE+HAL_DCACHE_LINE_SIZE]; +static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); DEVTAB_ENTRY(quicc_smc_serial_io_smc1, CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME, @@ -185,8 +182,8 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c CYG_SERIAL_FLAGS_DEFAULT ); #endif -static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE+HAL_DCACHE_LINE_SIZE]; -static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE+HAL_DCACHE_LINE_SIZE]; +static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); DEVTAB_ENTRY(quicc_smc_serial_io_smc2, CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME, @@ -230,8 +227,8 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c CYG_SERIAL_FLAGS_DEFAULT ); #endif -static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE+HAL_DCACHE_LINE_SIZE]; -static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE+HAL_DCACHE_LINE_SIZE]; +static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); DEVTAB_ENTRY(quicc_smc_serial_io_scc1, CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_NAME, @@ -275,8 +272,8 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c CYG_SERIAL_FLAGS_DEFAULT ); #endif -static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE+HAL_DCACHE_LINE_SIZE]; -static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE+HAL_DCACHE_LINE_SIZE]; +static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); DEVTAB_ENTRY(quicc_smc_serial_io_scc2, CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_NAME, @@ -320,8 +317,8 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c CYG_SERIAL_FLAGS_DEFAULT ); #endif -static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE+HAL_DCACHE_LINE_SIZE]; -static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE+HAL_DCACHE_LINE_SIZE]; +static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); +static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE))); DEVTAB_ENTRY(quicc_smc_serial_io_scc3, CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME, @@ -632,11 +629,11 @@ quicc_sxx_serial_init(struct cyg_devtab_ TxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE, - ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0]), + &quicc_smc1_txbuf[0], RxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE, - ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0]), + &quicc_smc1_rxbuf[0], 0xC0, // PortB mask QUICC_CPM_SMC1 ); @@ -652,11 +649,11 @@ quicc_sxx_serial_init(struct cyg_devtab_ TxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE, - ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0]), + &quicc_smc2_txbuf[0], RxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE, - ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0]), + &quicc_smc2_rxbuf[0], 0xC00, // PortB mask QUICC_CPM_SMC2 ); @@ -672,11 +669,11 @@ quicc_sxx_serial_init(struct cyg_devtab_ TxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc1_txbuf[0]), + &quicc_scc1_txbuf[0], RxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc1_rxbuf[0]), + &quicc_scc1_rxbuf[0], 0x0003, // PortA mask 0x1000, // PortB mask 0x0800, // PortC mask @@ -694,11 +691,11 @@ quicc_sxx_serial_init(struct cyg_devtab_ TxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc2_txbuf[0]), + &quicc_scc2_txbuf[0], RxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc2_rxbuf[0]), + &quicc_scc2_rxbuf[0], 0x000C, // PortA mask 0x2000, // PortB mask 0x0C00, // PortC mask @@ -716,11 +713,11 @@ quicc_sxx_serial_init(struct cyg_devtab_ TxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc3_txbuf[0]), + &quicc_scc3_txbuf[0], RxBD, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM, CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE, - ALIGN_TO_CACHELINES(&quicc_scc3_rxbuf[0]), + &quicc_scc3_rxbuf[0], 0x0000, // PortA mask 0x00C0, // PortB mask 0x0000, // PortC mask