Mercurial > flash_v2
changeset 835:d6cfbed66cf9
New XScale ports
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -1,3 +1,7 @@ +2003-03-18 Mark Salter <msalter@redhat.com> + + * ecos.db: Add support for XScale IXP425, IXDP425, GRG. + 2003-03-05 John Dallaway <jld@ecoscentric.com> * ecosadmin.tcl: Prevent calls to 'cygpath' with an empty
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,5 @@ +* New ports for Intel XScale IXP425 boards (IXDP425 and Generic Residential + Gateway). * SNMP code now works with the FreeBSD stack * Simple Network Time Protocol (SNTP) client contributed by Andrew Lunn. * Added port for NMI uE250 (ARM Xscale PXA250) platform, contributed
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/grg/i82559/current/ChangeLog @@ -0,0 +1,38 @@ +2003-02-07 Mark Salter <msalter@redhat.com> + + * Initial checkin. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/grg/i82559/current/cdl/grg_i82559_eth_driver.cdl @@ -0,0 +1,141 @@ +# ==================================================================== +# +# grg_i82559_eth_driver.cdl +# +# Ethernet driver +# GRG and Intel PRO/100+ platform specific support +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Original data: hmt +# Contributors: gthomas +# Date: 2002-04-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ARM_GRG_I82559 { + display "GRG with Intel PRO/100+ (PCI) ethernet driver" + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_ARM_XSCALE_GRG + + include_dir cyg/io + + # FIXME: This really belongs in the INTEL_I82559 package + cdl_interface CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED { + display "Intel i82559 ethernet driver required" + } + + define_proc { + puts $::cdl_system_header "/***** ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_INL <cyg/io/grg_i82559.inl>" + + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_CFG <pkgconf/devs_eth_arm_grg_i82559.h>" + + puts $::cdl_system_header "/***** ethernet driver proc output end *****/" + } + + + cdl_component CYGPKG_DEVS_ETH_ARM_GRG_I82559_ETH0 { + display "GRG ethernet port driver for an I82559-based ethernet NIC card" + flavor bool + default_value 1 + description " + This option includes the GRG ethernet device driver for a + I82559-based ethernet PCI card." + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED + + cdl_option CYGDAT_DEVS_ETH_ARM_GRG_I82559_ETH0_NAME { + display "Device name for the ETH0 ethernet port driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the ethernet device for a + I82559-based ethernet NIC card." + } + } + + + # note that this option's name is NOT grg-specific, but i82559 + # generic - other instantiations can set these also. + cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA { + display "RedBoot manages ESA initialization data" + flavor bool + default_value 1 + + active_if CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + + description "Enabling this option will allow the ethernet + station address to be acquired from RedBoot's configuration data, + stored in flash memory. It can be overridden individually by the + 'Set the ethernet station address' option for each interface." + + cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_VARS { + display "Build-in flash config fields for ESAs" + flavor bool + default_value 1 + + active_if CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT_FLASH + active_if CYGSEM_REDBOOT_FLASH_CONFIG + active_if CYGPKG_REDBOOT_NETWORKING + + description " + This option controls the presence of RedBoot flash + configuration fields for the ESAs of the interfaces when you + are building RedBoot. It is independent of whether RedBoot + itself uses the network or any particular interface; this + support is more for the application to use than for RedBoot + itself, though the application gets at the data by vector + calls; this option cannot be enabled outside of building + RedBoot." + + cdl_option CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0 { + display "RedBoot manages ESA for eth0" + flavor bool + default_value 1 + } + + cdl_option CYGDAT_DEVS_ETH_ARM_GRG_ETH0_DEFAULT_ESA { + display "The ethernet station address" + flavor data + default_value {"{0x00, 0x03, 0x47, 0xdf, 0x32, 0xa8}"} + description "The default ethernet station address. This is the + address used as the default value in the RedBoot + flash configuration field." + } + } + } +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/grg/i82559/current/include/grg_i82559.inl @@ -0,0 +1,180 @@ +//========================================================================== +// +// grg_i82559.inl +// +// GRG ethernet I/O definitions. +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): +// Contributors:msalter +// Date: 2003-02-05 +// Purpose: grg ethernet definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHERNET +#include <cyg/hal/hal_cache.h> // HAL_DCACHE_LINE_SIZE +#include <cyg/hal/plf_io.h> // CYGARC_UNCACHED_ADDRESS + +// Bus hardware takes care of IO endianess issues. +#define CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO 1 + +// NB: Bus masters can only get to first 64MB SDRAM +#define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) \ + ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_)) + +#define MAX_PACKET_SIZE 1536 +#define SIZEOF_DESCRIPTOR 16 +#define MISC_MEM 1128 // selftest, ioctl and statistics + +#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE \ + (((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \ + (CYGNUM_DEVS_ETH_INTEL_I82559_MAX_TX_DESCRIPTORS + \ + CYGNUM_DEVS_ETH_INTEL_I82559_MAX_RX_DESCRIPTORS)) + \ + MISC_MEM)*CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT + +// The PCI Window is 64MB starting at 0x00000000, so as long as the bss +// section is within addresses 0x00000000-0x04000000, pci_mem_buffer[] will be +// in the true PCI Window. Because pci_mem_buffer[] is in the bss section, +// wanted its size to be only as large as required so as to not waste memory. +// Therefore, had to compute it's size in this file and not in the memory +// layout files. So no __pci_window label was ever defined, therefore, +// CYGMEM_SECTION_pci_window does not exist. Define CYGMEM_SECTION_pci_window +// here in order to satisfy the ASSERT within if_i82559.c. +static char pci_mem_buffer[CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE + + HAL_DCACHE_LINE_SIZE]; + +#define CYGMEM_SECTION_pci_window (((unsigned)pci_mem_buffer \ + + HAL_DCACHE_LINE_SIZE - 1) \ + & ~(HAL_DCACHE_LINE_SIZE - 1)) + +#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE \ + (CYGARC_UNCACHED_ADDRESS(CYGMEM_SECTION_pci_window)) + + +#ifdef CYGPKG_DEVS_ETH_ARM_GRG_I82559_ETH0 + +static I82559 i82559_eth0_priv_data = { + hardwired_esa: 0, +#if defined(CYGPKG_REDBOOT) && defined(CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0) + mac_address: CYGDAT_DEVS_ETH_ARM_GRG_ETH0_DEFAULT_ESA +#endif +}; + +ETH_DRV_SC(i82559_sc0, + &i82559_eth0_priv_data, // Driver specific data + CYGDAT_DEVS_ETH_ARM_GRG_I82559_ETH0_NAME, // Name for device + i82559_start, + i82559_stop, + i82559_ioctl, + i82559_can_send, + i82559_send, + i82559_recv, + i82559_deliver, + i82559_poll, + i82559_int_vector + ); + +NETDEVTAB_ENTRY(i82559_netdev0, + "i82559_" CYGDAT_DEVS_ETH_ARM_GRG_I82559_ETH0_NAME, + i82559_init, + &i82559_sc0); +#endif // CYGPKG_DEVS_ETH_ARM_IXP425_I82559_ETH0 + + +// These arrays are used for sanity checking of pointers +I82559 * +i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_GRG_I82559_ETH0 + &i82559_eth0_priv_data, +#endif +}; + +#ifdef CYGDBG_USE_ASSERTS +// These are only used when assertions are enabled +cyg_netdevtab_entry_t * +i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_GRG_I82559_ETH0 + &i82559_netdev0, +#endif +}; + +struct eth_drv_sc * +i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_GRG_I82559_ETH0 + &i82559_sc0, +#endif +}; +#endif // CYGDBG_USE_ASSERTS + +// -------------------------------------------------------------- +// RedBoot configuration options for managing ESAs for us + +// Decide whether to have redboot config vars for it... +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#ifdef CYGPKG_REDBOOT_NETWORKING +#include <redboot.h> +#include <flash_config.h> + +#ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0 +RedBoot_config_option("Network hardware address [MAC] for eth0", + eth0_esa, + ALWAYS_ENABLED, true, + CONFIG_ESA, i82559_eth0_priv_data.mac_address + ); +#endif + +#endif // CYGPKG_REDBOOT_NETWORKING +#endif // CYGSEM_REDBOOT_FLASH_CONFIG +#endif // CYGPKG_REDBOOT + +// and initialization code to read them +// - independent of whether we are building RedBoot right now: +#ifdef CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA + +#include <cyg/hal/hal_if.h> + +#ifndef CONFIG_ESA +#define CONFIG_ESA (6) +#endif + +#define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA( p_i82559, mac_address, ok ) \ +CYG_MACRO_START \ + ok = false; \ + if ( 0 == p_i82559->index ) \ + ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \ + "eth0_esa", mac_address, CONFIG_ESA); \ + else if ( 1 == p_i82559->index ) \ + ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \ + "eth1_esa", mac_address, CONFIG_ESA); \ +CYG_MACRO_END + +#endif // CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/ixdp425/i82559/current/ChangeLog @@ -0,0 +1,43 @@ +2003-02-07 Mark Salter <msalter@redhat.com> + + * cdl/ixdp425_i82559_eth_driver.cdl: CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA. + * include/ixdp425_i82559.inl: Support ESA in RedBoot flash. + +2002-12-17 Mark Salter <msalter@redhat.com> + + * include/ixdp425_i82559.inl: Define CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/ixdp425/i82559/current/cdl/ixdp425_i82559_eth_driver.cdl @@ -0,0 +1,141 @@ +# ==================================================================== +# +# ixdp425_i82559_eth_driver.cdl +# +# Ethernet driver +# IXDP425 and Intel PRO/100+ platform specific support +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Original data: hmt +# Contributors: gthomas +# Date: 2002-04-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 { + display "IXDP425 with Intel PRO/100+ (PCI) ethernet driver" + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_ARM_XSCALE_IXDP425 + + include_dir cyg/io + + # FIXME: This really belongs in the INTEL_I82559 package + cdl_interface CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED { + display "Intel i82559 ethernet driver required" + } + + define_proc { + puts $::cdl_system_header "/***** ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_INL <cyg/io/ixdp425_i82559.inl>" + + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_CFG <pkgconf/devs_eth_arm_ixdp425_i82559.h>" + + puts $::cdl_system_header "/***** ethernet driver proc output end *****/" + } + + + cdl_component CYGPKG_DEVS_ETH_ARM_IXDP425_I82559_ETH0 { + display "IXDP425 ethernet port driver for an I82559-based ethernet NIC card" + flavor bool + default_value 1 + description " + This option includes the IXDP425 ethernet device driver for a + I82559-based ethernet PCI card." + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED + + cdl_option CYGDAT_DEVS_ETH_ARM_IXDP425_I82559_ETH0_NAME { + display "Device name for the ETH0 ethernet port driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the ethernet device for a + I82559-based ethernet NIC card." + } + } + + + # note that this option's name is NOT ixdp-specific, but i82559 + # generic - other instantiations can set these also. + cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA { + display "RedBoot manages ESA initialization data" + flavor bool + default_value 1 + + active_if CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + + description "Enabling this option will allow the ethernet + station address to be acquired from RedBoot's configuration data, + stored in flash memory. It can be overridden individually by the + 'Set the ethernet station address' option for each interface." + + cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_VARS { + display "Build-in flash config fields for ESAs" + flavor bool + default_value 1 + + active_if CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT_FLASH + active_if CYGSEM_REDBOOT_FLASH_CONFIG + active_if CYGPKG_REDBOOT_NETWORKING + + description " + This option controls the presence of RedBoot flash + configuration fields for the ESAs of the interfaces when you + are building RedBoot. It is independent of whether RedBoot + itself uses the network or any particular interface; this + support is more for the application to use than for RedBoot + itself, though the application gets at the data by vector + calls; this option cannot be enabled outside of building + RedBoot." + + cdl_option CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0 { + display "RedBoot manages ESA for eth0" + flavor bool + default_value 1 + } + + cdl_option CYGDAT_DEVS_ETH_ARM_IXDP425_ETH0_DEFAULT_ESA { + display "The ethernet station address" + flavor data + default_value {"{0x00, 0x03, 0x47, 0xdf, 0x32, 0xa8}"} + description "The default ethernet station address. This is the + address used as the default value in the RedBoot + flash configuration field." + } + } + } +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/arm/ixdp425/i82559/current/include/ixdp425_i82559.inl @@ -0,0 +1,180 @@ +//========================================================================== +// +// ixdp425_i82559.inl +// +// IXDP425 ethernet I/O definitions. +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): +// Contributors:msalter +// Date: 2002-05-14 +// Purpose: ixdp425 ethernet definitions +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHERNET +#include <cyg/hal/hal_cache.h> // HAL_DCACHE_LINE_SIZE +#include <cyg/hal/plf_io.h> // CYGARC_UNCACHED_ADDRESS + +// Bus hardware takes care of IO endianess issues. +#define CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO 1 + +// NB: Bus masters can only get to first 64MB SDRAM +#define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) \ + ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_)) + +#define MAX_PACKET_SIZE 1536 +#define SIZEOF_DESCRIPTOR 16 +#define MISC_MEM 1128 // selftest, ioctl and statistics + +#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE \ + (((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \ + (CYGNUM_DEVS_ETH_INTEL_I82559_MAX_TX_DESCRIPTORS + \ + CYGNUM_DEVS_ETH_INTEL_I82559_MAX_RX_DESCRIPTORS)) + \ + MISC_MEM)*CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT + +// The PCI Window is 64MB starting at 0x00000000, so as long as the bss +// section is within addresses 0x00000000-0x04000000, pci_mem_buffer[] will be +// in the true PCI Window. Because pci_mem_buffer[] is in the bss section, +// wanted its size to be only as large as required so as to not waste memory. +// Therefore, had to compute it's size in this file and not in the memory +// layout files. So no __pci_window label was ever defined, therefore, +// CYGMEM_SECTION_pci_window does not exist. Define CYGMEM_SECTION_pci_window +// here in order to satisfy the ASSERT within if_i82559.c. +static char pci_mem_buffer[CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE + + HAL_DCACHE_LINE_SIZE]; + +#define CYGMEM_SECTION_pci_window (((unsigned)pci_mem_buffer \ + + HAL_DCACHE_LINE_SIZE - 1) \ + & ~(HAL_DCACHE_LINE_SIZE - 1)) + +#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE \ + (CYGARC_UNCACHED_ADDRESS(CYGMEM_SECTION_pci_window)) + + +#ifdef CYGPKG_DEVS_ETH_ARM_IXDP425_I82559_ETH0 + +static I82559 i82559_eth0_priv_data = { + hardwired_esa: 0, +#if defined(CYGPKG_REDBOOT) && defined(CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0) + mac_address: CYGDAT_DEVS_ETH_ARM_IXDP425_ETH0_DEFAULT_ESA +#endif +}; + +ETH_DRV_SC(i82559_sc0, + &i82559_eth0_priv_data, // Driver specific data + CYGDAT_DEVS_ETH_ARM_IXDP425_I82559_ETH0_NAME, // Name for device + i82559_start, + i82559_stop, + i82559_ioctl, + i82559_can_send, + i82559_send, + i82559_recv, + i82559_deliver, + i82559_poll, + i82559_int_vector + ); + +NETDEVTAB_ENTRY(i82559_netdev0, + "i82559_" CYGDAT_DEVS_ETH_ARM_IXDP425_I82559_ETH0_NAME, + i82559_init, + &i82559_sc0); +#endif // CYGPKG_DEVS_ETH_ARM_IXP425_I82559_ETH0 + + +// These arrays are used for sanity checking of pointers +I82559 * +i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_IXDP425_I82559_ETH0 + &i82559_eth0_priv_data, +#endif +}; + +#ifdef CYGDBG_USE_ASSERTS +// These are only used when assertions are enabled +cyg_netdevtab_entry_t * +i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_IXDP425_I82559_ETH0 + &i82559_netdev0, +#endif +}; + +struct eth_drv_sc * +i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ARM_IXDP425_I82559_ETH0 + &i82559_sc0, +#endif +}; +#endif // CYGDBG_USE_ASSERTS + +// -------------------------------------------------------------- +// RedBoot configuration options for managing ESAs for us + +// Decide whether to have redboot config vars for it... +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#ifdef CYGPKG_REDBOOT_NETWORKING +#include <redboot.h> +#include <flash_config.h> + +#ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0 +RedBoot_config_option("Network hardware address [MAC] for eth0", + eth0_esa, + ALWAYS_ENABLED, true, + CONFIG_ESA, i82559_eth0_priv_data.mac_address + ); +#endif + +#endif // CYGPKG_REDBOOT_NETWORKING +#endif // CYGSEM_REDBOOT_FLASH_CONFIG +#endif // CYGPKG_REDBOOT + +// and initialization code to read them +// - independent of whether we are building RedBoot right now: +#ifdef CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA + +#include <cyg/hal/hal_if.h> + +#ifndef CONFIG_ESA +#define CONFIG_ESA (6) +#endif + +#define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA( p_i82559, mac_address, ok ) \ +CYG_MACRO_START \ + ok = false; \ + if ( 0 == p_i82559->index ) \ + ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \ + "eth0_esa", mac_address, CONFIG_ESA); \ + else if ( 1 == p_i82559->index ) \ + ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \ + "eth1_esa", mac_address, CONFIG_ESA); \ +CYG_MACRO_END + +#endif // CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/grg/current/ChangeLog @@ -0,0 +1,38 @@ +2003-02-07 Mark Salter <msalter@redhat.com> + + * Initial checkin. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/grg/current/cdl/flash_grg.cdl @@ -0,0 +1,69 @@ +# ==================================================================== +# +# flash_grg.cdl +# +# FLASH memory - Hardware support on GRG board +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Original data: msalter +# Contributors: +# Date: 2003-02-05 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_GRG { + display "GRG board FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_XSCALE_GRG + requires CYGPKG_DEVS_FLASH_STRATA + + implements CYGHWR_IO_FLASH_BLOCK_LOCKING + + include_dir cyg/io + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED { + display "Generic StrataFLASH driver required" + } + + implements CYGINT_DEVS_FLASH_STRATA_REQUIRED + + define_proc { + puts $::cdl_system_header "/***** grg flash driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL <cyg/io/grg_strataflash.inl>" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG <pkgconf/devs_flash_grg.h>" + puts $::cdl_system_header "/***** GRG flash driver proc output end *****/" + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/grg/current/include/grg_strataflash.inl @@ -0,0 +1,67 @@ +#ifndef CYGONCE_DEVS_FLASH_GRG_STRATAFLASH_INL +#define CYGONCE_DEVS_FLASH_GRG_STRATAFLASH_INL +//========================================================================== +// +// grg_strataflash.inl +// +// Flash programming - device constants, etc. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-05 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// The grg has one 16-bit device. +// StrataFlash 28F128. + +#define CYGNUM_FLASH_DEVICES (1) +#define CYGNUM_FLASH_BASE_MASK (0xFF000000u) // 16Mb + +#define CYGNUM_FLASH_BASE (0x50000000u) +#define CYGNUM_FLASH_WIDTH (16) +#define CYGNUM_FLASH_BLANK (1) + +#endif // CYGONCE_DEVS_FLASH_GRG_STRATAFLASH_INL +// ------------------------------------------------------------------------ +// EOF grg_strataflash.inl
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/ixdp425/current/ChangeLog @@ -0,0 +1,36 @@ + + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/ixdp425/current/cdl/flash_ixdp425.cdl @@ -0,0 +1,69 @@ +# ==================================================================== +# +# flash_ixdp425.cdl +# +# FLASH memory - Hardware support on IXDP425 board +# +# ==================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Red Hat eCos Public License +# Version 1.1 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://www.redhat.com/ +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Configurable Operating System, +# released September 30, 1998. +# +# The Initial Developer of the Original Code is Red Hat. +# Portions created by Red Hat are +# Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +# All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Original data: msalter +# Contributors: +# Date: 2002-12-11 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_IXDP425 { + display "IXDP425 board FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_XSCALE_IXDP425 + requires CYGPKG_DEVS_FLASH_STRATA + + implements CYGHWR_IO_FLASH_BLOCK_LOCKING + + include_dir cyg/io + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED { + display "Generic StrataFLASH driver required" + } + + implements CYGINT_DEVS_FLASH_STRATA_REQUIRED + + define_proc { + puts $::cdl_system_header "/***** ixdp425 flash driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL <cyg/io/ixdp425_strataflash.inl>" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG <pkgconf/devs_flash_ixdp425.h>" + puts $::cdl_system_header "/***** ixdp425 flash driver proc output end *****/" + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/flash/arm/ixdp425/current/include/ixdp425_strataflash.inl @@ -0,0 +1,67 @@ +#ifndef CYGONCE_DEVS_FLASH_IXDP425_STRATAFLASH_INL +#define CYGONCE_DEVS_FLASH_IXDP425_STRATAFLASH_INL +//========================================================================== +// +// ixdp425_strataflash.inl +// +// Flash programming - device constants, etc. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas, hmt +// Contributors: gthomas +// Date: 2001-02-24 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// The ixdp425 has one 16-bit device. +// StrataFlash 28F128. + +#define CYGNUM_FLASH_DEVICES (1) +#define CYGNUM_FLASH_BASE_MASK (0xFF000000u) // 16Mb + +#define CYGNUM_FLASH_BASE (0x50000000u) +#define CYGNUM_FLASH_WIDTH (16) +#define CYGNUM_FLASH_BLANK (1) + +#endif // CYGONCE_DEVS_FLASH_IXDP425_STRATAFLASH_INL +// ------------------------------------------------------------------------ +// EOF ixdp425_strataflash.inl
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -462,6 +462,26 @@ package CYGPKG_DEVS_FLASH_IQ80321 { on the IQ80321 platform." } +package CYGPKG_DEVS_FLASH_IXDP425 { + alias { "FLASH memory support for IXDP425" flash_ixdp425 } + directory devs/flash/arm/ixdp425 + script flash_ixdp425.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the IXDP425 platform." +} + +package CYGPKG_DEVS_FLASH_GRG { + alias { "FLASH memory support for GRG" flash_grg } + directory devs/flash/arm/grg + script flash_grg.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the Intel Generic Residential Gateway platform." +} + package CYGPKG_DEVS_FLASH_ARM_INTEGRATOR { alias { "FLASH memory support for ARM INTEGRATOR" flash_integrator } directory devs/flash/arm/integrator @@ -1393,6 +1413,24 @@ package CYGPKG_DEVS_ETH_ARM_XSCALE_IQ803 description "Ethernet driver for Intel IQ80310 with onboard 82559 NIC." } +package CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 { + alias { "IXDP425 (PCI) / Intel 82559 ethernet driver" + devs_eth_arm_ixdp425_i82559 } + hardware + directory devs/eth/arm/ixdp425/i82559 + script ixdp425_i82559_eth_driver.cdl + description "Ethernet driver for IXDP425 with Intel 82559 PCI NIC." +} + +package CYGPKG_DEVS_ETH_ARM_GRG_I82559 { + alias { "GRG / Intel 82559 ethernet driver" + devs_eth_arm_grg_i82559 } + hardware + directory devs/eth/arm/grg/i82559 + script grg_i82559_eth_driver.cdl + description "Ethernet driver for GRG with Intel 82559 PCI NIC." +} + package CYGPKG_DEVS_ETH_I386_PC_I82559 { alias { "Standard PC with EtherPro 10/100 ethernet device" devs_eth_i386_pc_i82559 pc_etherpro } @@ -2253,6 +2291,36 @@ package CYGPKG_HAL_ARM_XSCALE_IQ80321 { eCos on an Intel XScale IQ80321 evaluation board." } +package CYGPKG_HAL_ARM_XSCALE_IXP425 { + alias { "Intel XScale IXP425 Network Processor" hal_arm_xscale_ixp425 } + directory hal/arm/xscale/ixp425 + script hal_arm_xscale_ixp425.cdl + hardware + description " + The XScale IXP425 HAL package provides the support needed to run + eCos on Intel XScale IXP425 network processor based systems." +} + +package CYGPKG_HAL_ARM_XSCALE_IXDP425 { + alias { "Intel XScale IXDP425 Network Processor eval board" hal_arm_xscale_ixdp425 } + directory hal/arm/xscale/ixdp425 + script hal_arm_xscale_ixdp425.cdl + hardware + description " + The IXDP425 HAL package provides the support needed to run + eCos on an Intel XScale IXDP425 network processor evaluation board." +} + +package CYGPKG_HAL_ARM_XSCALE_GRG { + alias { "Intel XScale Generic Residential Gateway" hal_arm_xscale_grg } + directory hal/arm/xscale/grg + script hal_arm_xscale_grg.cdl + hardware + description " + The GRG HAL package provides the support needed to run eCos on an + Intel Generic Residential Gateway evaluation board." +} + package CYGPKG_HAL_ARM_XSCALE_PXA2X0 { alias { "Intel PXA2X0" hal_arm_xscale_pxa2x0 } directory hal/arm/xscale/pxa2x0 @@ -3633,6 +3701,40 @@ target iq80321 { eCos on an Intel XScale IQ80321 board." } +target ixdp425 { + alias { "IXDP425 board" ixdp425 } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_XSCALE_CORE + CYGPKG_HAL_ARM_XSCALE_IXP425 + CYGPKG_HAL_ARM_XSCALE_IXDP425 + CYGPKG_IO_PCI + CYGPKG_DEVS_ETH_INTEL_I82559 + CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 + CYGPKG_DEVS_FLASH_STRATA + CYGPKG_DEVS_FLASH_IXDP425 + } + description " + The ixdp425 target provides the packages needed to run + eCos on an Intel network processor evaluation board." +} + +target grg { + alias { "Generic Residential Gateway" grg } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_XSCALE_CORE + CYGPKG_HAL_ARM_XSCALE_IXP425 + CYGPKG_HAL_ARM_XSCALE_GRG + CYGPKG_IO_PCI + CYGPKG_DEVS_ETH_INTEL_I82559 + CYGPKG_DEVS_ETH_ARM_GRG_I82559 + CYGPKG_DEVS_FLASH_STRATA + CYGPKG_DEVS_FLASH_GRG + } + description " + The grg target provides the packages needed to run + eCos on an Intel Generic Residential Gateway board." +} + target edb7xxx { alias { "Cirrus Logic EDB7xxx development board" edb7211 eb7xxx eb7211 } packages { CYGPKG_HAL_ARM
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/ChangeLog @@ -0,0 +1,51 @@ +2003-02-22 Mark Salter <msalter@redhat.com> + + * cdl/hal_arm_xscale_grg.cdl: Fix HAL_PLATFORM_MACHINE_TYPE. + +2003-02-13 Mark Salter <msalter@redhat.com> + + * include/hal_platform_extras.h: Move uncached area. Create RAM + alias area. + +2003-02-12 Mark Salter <msalter@redhat.com> + + * misc/*.ecm: Turn on CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM. + +2003-02-07 Mark Salter <msalter@redhat.com> + + * Initial checkin. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/cdl/hal_arm_xscale_grg.cdl @@ -0,0 +1,300 @@ +# ==================================================================== +# +# hal_arm_xscale_grg.cdl +# +# Intel XScale GRG Network Processor Eval Board HAL package +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Contributors: msalter +# Date: 2003-02-05 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_XSCALE_GRG { + display "Intel Generic Residential Gateway Platform" + parent CYGPKG_HAL_ARM_XSCALE + implements CYGINT_HAL_ARM_BIGENDIAN + hardware + include_dir cyg/hal + define_header hal_arm_xscale_grg.h + description " + This HAL platform package provides support for + the Intel Generic Residential Gateway board." + + compile grg_misc.c grg_pci.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_xscale_ixp425.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_xscale_grg.h>" + puts $::cdl_header "#define CYGBLD_HAL_PLF_INTS_H <cyg/hal/hal_plf_ints.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Intel Generic Residential Gateway\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 290" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targeting the GRG board it is possible to configure the system + for either RAM bootstrap or ROM bootstrap(s). Select 'ram' when + building programs to load into RAM using onboard debug software + such as RedBoot or eCos GDB stubs." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=xscale -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -mapcs-frame" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=xscale -mbig-endian -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ + } + } + } + + cdl_component CYGPKG_HAL_ARM_XSCALE_GRG_OPTIONS { + display "Intel XScale GRG build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_XSCALE_GRG_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale GRG HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_XSCALE_GRG_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale GRG HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { + display "Number of breakpoints supported by the HAL." + flavor data + default_value 32 + description " + This option determines the number of breakpoints supported by the HAL." + } + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART1 { + display "GRG uses IXP425 high-speed UART" + flavor bool + default_value 0 + description " + Enable this option if the IXP425 high-speed UART is used + as a virtual vector communications channel." + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART2 { + display "GRG uses IXP425 console UART" + flavor bool + default_value 1 + description " + Enable this option if the IXP425 console UART is to be used + as a virtual vector communications channel." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_xscale_grg_ram" : \ + "arm_xscale_grg_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_xscale_grg_ram.ldi>" : \ + "<pkgconf/mlt_arm_xscale_grg_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_xscale_grg_ram.h>" : \ + "<pkgconf/mlt_arm_xscale_grg_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/grg.h @@ -0,0 +1,94 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H +#define CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H + +/*============================================================================= +// +// grg.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-05 +// Purpose: Intel GRG specific support routines +// Description: +// Usage: #include <cyg/hal/grg.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <pkgconf/hal_arm_xscale_grg.h> +#include <cyg/hal/hal_ixp425.h> + +// These must match setup in the page table in hal_platform_extras.h +#define SDRAM_PHYS_BASE 0x00000000 +#define SDRAM_BASE 0x00000000 +#define SDRAM_UNCACHED_BASE 0x10000000 +#define SDRAM_SIZE 0x02000000 // 32MB + +// CS0 (flash optimum timing) +#define IXP425_EXP_CS0_INIT \ + (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \ + EXP_RECOVERY_T(15) | EXP_SZ_16M | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN) + +#define IXP425_SDRAM_CONFIG_INIT (SDRAM_CONFIG_CAS_3 | SDRAM_CONFIG_2x8Mx16) +#define IXP425_SDRAM_REFRESH_CNT 0x81A +#define IXP425_SDRAM_SET_MODE_CMD SDRAM_IR_MODE_SET_CAS3 + + +// ------------------------------------------------------------------------ +// No Hex Display +// +#ifdef __ASSEMBLER__ + // Display hex digits in 'value' not masked by 'mask'. + .macro DISPLAY value, reg0, reg1 + .endm +#else +static inline void HEX_DISPLAY(int value) +{ +} +#endif // __ASSEMBLER__ + +// ------------------------------------------------------------------------ + +#endif // CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H +// EOF grg.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/hal_platform_extras.h @@ -0,0 +1,223 @@ +#ifndef CYGONCE_HAL_PLATFORM_EXTRAS_H +#define CYGONCE_HAL_PLATFORM_EXTRAS_H + +/*============================================================================= +// +// hal_platform_extras.h +// +// Platform specific MMU table. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-08 +// Purpose: Intel XScale Generic Residential Platform specific mmu table +// Description: +// Usage: #include <cyg/hal/hal_platform_extras.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#if defined(CYG_HAL_STARTUP_ROMRAM) + .section .text + .ltorg + .p2align 13 +#else + .section .mmu_tables, "a" +#endif + + mmu_table: + // This page table sets up the preferred mapping: + // + // Virtual Address Physical Address XCB Size (MB) Description + // --------------- ---------------- --- --------- ----------- + // 0x00000000 0x00000000 010 32 SDRAM (cached) + // 0x10000000 0x10000000 000 32 SDRAM (alias) + // 0x20000000 0x00000000 000 32 SDRAM (uncached) + // 0x48000000 0x48000000 000 64 PCI Data + // 0x50000000 0x50000000 010 16 Flash (CS0) + // 0x51000000 0x51000000 000 112 CS1 - CS7 + // 0x60000000 0x60000000 000 64 Queue Manager + // 0xC0000000 0xC0000000 000 1 PCI Controller + // 0xC4000000 0xC4000000 000 1 Exp. Bus Config + // 0xC8000000 0xC8000000 000 1 Misc IXP425 IO + // 0xCC000000 0xCC000000 000 1 SDRAM Config + + // 32MB SDRAM + .set __base,0x000 + .rept 0x020 - 0x000 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // 224MB Unused + .rept 0x100 - 0x020 + .word 0 + .set __base,__base+1 + .endr + + // 32MB SDRAM Alias + .rept 0x120 - 0x100 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // 224MB Unused + .rept 0x200 - 0x120 + .word 0 + .set __base,__base+1 + .endr + + // 32MB SDRAM (uncached) + .set __base,0x000 + .rept 0x220 - 0x200 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 224MB Unused + .set __base,0x220 + .rept 0x300 - 0x220 + .word 0 + .set __base,__base+1 + .endr + + // 384MB Unused + .rept 0x480 - 0x300 + .word 0 + .set __base,__base+1 + .endr + + // 64MB PCI Data + .rept 0x4C0 - 0x480 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 64MB Unused + .rept 0x500 - 0x4C0 + .word 0 + .set __base,__base+1 + .endr + + // 16MB Flash (Expansion bus CS0) + .rept 0x510 - 0x500 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // Rest of Expansion bus (CS1-CS7) + .rept 0x600 - 0x510 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 64MB Queue Manager + .rept 0x640 - 0x600 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 1472MB Unused + .rept 0xC00 - 0x640 + .word 0 + .set __base,__base+1 + .endr + + // 1MB PCI Controller + .rept 0xC01 - 0xC00 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xC40 - 0xC01 + .word 0 + .set __base,__base+1 + .endr + + // 1MB Expansion bus config + .rept 0xC41 - 0xC40 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xC80 - 0xC41 + .word 0 + .set __base,__base+1 + .endr + + // 1MB Misc IO + .rept 0xC81 - 0xC80 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xCC0 - 0xC81 + .word 0 + .set __base,__base+1 + .endr + + // 1MB SDRAM Config + .rept 0xCC1 - 0xCC0 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xD00 - 0xCC1 + .word 0 + .set __base,__base+1 + .endr + + // Rest is Unused + .rept 0x1000 - 0xD00 + .word 0 + .set __base,__base+1 + .endr + +#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */ + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_extras.h */ +#endif /* CYGONCE_HAL_PLATFORM_EXTRAS_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/hal_platform_setup.h @@ -0,0 +1,316 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-06 +// Purpose: Intel XScale GRG specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/hal_mm.h> // more MMU definitions +#include <cyg/hal/grg.h> // Platform specific hardware definitions + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 _platform_setup1 +#define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h> +#define CYGHWR_HAL_ARM_HAS_MMU + +// ------------------------------------------------------------------------ +// Define macro used to diddle the LEDs during early initialization. +// Can use r0+r1. Argument in \x. +#define CYGHWR_LED_MACRO + +// Delay a bit +.macro DELAY cycles, reg0 +#if 0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc +#endif +.endm + +// ------------------------------------------------------------------------ +// This macro represents the initial startup code for the platform + .macro _platform_setup1 + +#ifdef CYGINT_HAL_ARM_BIGENDIAN + // set big-endian + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x80 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 +#endif + + ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr, r0 + + // invalidate I & D caches & BTB + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + // invalidate I & Data TLB + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + // drain write and fill buffers + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + // disable write buffer coalescing + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 1 + CPWAIT r0 + + // Setup chip selects + ldr r1, =IXP425_EXP_CFG_BASE +#ifdef IXP425_EXP_CS0_INIT + ldr r0, =IXP425_EXP_CS0_INIT + str r0, [r1, #IXP425_EXP_CS0] +#endif +#ifdef IXP425_EXP_CS1_INIT + ldr r0, =IXP425_EXP_CS1_INIT + str r0, [r1, #IXP425_EXP_CS1] +#endif +#ifdef IXP425_EXP_CS2_INIT + ldr r0, =IXP425_EXP_CS2_INIT + str r0, [r1, #IXP425_EXP_CS2] +#endif +#ifdef IXP425_EXP_CS3_INIT + ldr r0, =IXP425_EXP_CS3_INIT + str r0, [r1, #IXP425_EXP_CS3] +#endif +#ifdef IXP425_EXP_CS4_INIT + ldr r0, =IXP425_EXP_CS4_INIT + str r0, [r1, #IXP425_EXP_CS4] +#endif +#ifdef IXP425_EXP_CS5_INIT + ldr r0, =IXP425_EXP_CS5_INIT + str r0, [r1, #IXP425_EXP_CS5] +#endif +#ifdef IXP425_EXP_CS6_INIT + ldr r0, =IXP425_EXP_CS6_INIT + str r0, [r1, #IXP425_EXP_CS6] +#endif +#ifdef IXP425_EXP_CS7_INIT + ldr r0, =IXP425_EXP_CS7_INIT + str r0, [r1, #IXP425_EXP_CS7] +#endif + + // Enable the Icache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // Setup SDRAM controller + + ldr r0, =IXP425_SDRAM_CFG_BASE + + ldr r1, =IXP425_SDRAM_CONFIG_INIT + str r1, [r0, #IXP425_SDRAM_CONFIG] + + // disable refresh cycles + mov r1, #0 + str r1, [r0, #IXP425_SDRAM_REFRESH] + + // send nop command + mov r1, #SDRAM_IR_NOP + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // set SDRAM internal refresh val + ldr r1, =IXP425_SDRAM_REFRESH_CNT + str r1, [r0, #IXP425_SDRAM_REFRESH] + DELAY 0x10000, r1 + + // send precharge-all command to close all open banks + mov r1, #SDRAM_IR_PRECHARGE + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // provide 8 auto-refresh cycles + mov r1, #SDRAM_IR_AUTO_REFRESH + mov r2, #8 + 1: + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x800, r3 + subs r2, r2, #1 + bne 1b + + // set mode register in sdram + mov r1, #IXP425_SDRAM_SET_MODE_CMD + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // start normal operation + mov r1, #SDRAM_IR_NORMAL + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + +#if defined(CYG_HAL_STARTUP_ROMRAM) + ldr r0,=0x00000000 + ldr r1,=0x10000000 + ldr r2,=__bss_start + 0: ldr r3,[r0],#4 + str r3,[r1],#4 + cmp r0,r2 + bne 0b +#endif + + // value to load into pc to jump to real runtime address + ldr r0, =1f + + // Setup EXP_CNFG0 value to switch EXP bus out of low memory + ldr r2, =IXP425_EXP_CFG_BASE + ldr r1, [r2, #IXP425_EXP_CNFG0] + bic r1, r1, #EXP_CNFG0_MEM_MAP + + b icache_boundary + .p2align 5 +icache_boundary: + // Here is where we switch from boot address (0x000000000) to the + // actual flash runtime address. We align to cache boundary so we + // execute from cache during the switchover. Cachelines are 8 words. + str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch + nop + nop + nop + nop + mov pc, r0 + nop + // display FFFF and loop forever. + 0: b 0b + 1: + +#if defined(CYG_HAL_STARTUP_ROM) + // Move mmu tables into RAM so page table walks by the cpu + // don't interfere with FLASH programming. + ldr r0, =mmu_table + add r2, r0, #0x4000 // End of tables + mov r1, #SDRAM_PHYS_BASE + orr r1, r1, #0x4000 // RAM tables + + // everything can go as-is + 1: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r0, r2 + bne 1b +#endif + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // Set the TTB register to DRAM mmu_table + ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables + mcr p15, 0, r0, c2, c0, 0 // load page table pointer + CPWAIT r0 + + // enable permission checks in all domains + ldr r0, =0x55555555 + mcr p15, 0, r0, c3, c0, 0 + CPWAIT r0 + + // enable mmu + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_M + orr r0, r0, #MMU_Control_R + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // enable D cache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_C + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // Enable branch target buffer + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_BTB + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB + CPWAIT r0 + + mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs + CPWAIT r0 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // save SDRAM size + ldr r1, =hal_dram_size /* [see hal_intr.h] */ + mov r8, #SDRAM_SIZE + str r8, [r1] + + .endm // _platform_setup1 + +#else // defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 +#endif + +#define PLATFORM_VECTORS _platform_vectors + .macro _platform_vectors + .endm + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/hal_plf_ints.h @@ -0,0 +1,78 @@ +#ifndef CYGONCE_HAL_PLF_INTS_H +#define CYGONCE_HAL_PLF_INTS_H +//========================================================================== +// +// hal_plf_ints.h +// +// HAL Platform Interrupt support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-07-15 +// Purpose: Define Interrupt support +// Description: The interrupt details for a specific platform is defined here. +// Usage: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// start with variant ints +#include CYGBLD_HAL_VAR_INTS_H + +// NB: Commented out because of errata on reset function of watchdog timer +// +#if 0 +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + cyg_uint32 __ctrl; \ + /* By disabling interupts we will just hang in the loop below */ \ + /* if for some reason the software reset fails. */ \ + HAL_DISABLE_INTERRUPTS(__ctrl); \ + *IXP425_OST_WDOG_KEY = 0x482e; \ + *IXP425_OST_WDOG = 10; \ + *IXP425_OST_WDOG_ENA = 5; \ + for(;;); /* hang here forever if reset fails */ \ + CYG_MACRO_END +#else +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT +#endif + +#endif // CYGONCE_HAL_PLF_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_ram.h @@ -0,0 +1,18 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x02000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x20000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_ram.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 02000000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 20000 20000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_rom.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x02000000 + rom : ORIGIN = 0x50000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.mmu_tables)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/pkgconf/mlt_arm_xscale_grg_rom.mlt @@ -0,0 +1,15 @@ +version 0 +region ram 0 02000000 0 ! +region rom 50000000 40000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 mmu_tables mmu_tables ! +section mmu_tables 0 4000 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/include/plf_io.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-05 +// Purpose: Intel GRG IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/grg.h> +#include CYGBLD_HAL_PLF_INTS_H + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/misc/redboot_RAM.ecm @@ -0,0 +1,123 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware grg ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_GRG current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_GRG current ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ; + package -hardware CYGPKG_DEVS_ETH_ARM_GRG_I82559 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x600000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_option CYGOPT_DEVS_FLASH_STRATA_NOT_IN_RAM { + inferred_value 0 +}; + +cdl_component CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM { + user_value 1 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/misc/redboot_ROM.ecm @@ -0,0 +1,128 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware grg ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_GRG current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_GRG current ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ; + package -hardware CYGPKG_DEVS_ETH_ARM_GRG_I82559 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x600000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM { + user_value 1 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/src/grg_misc.c @@ -0,0 +1,85 @@ +//========================================================================== +// +// grg_misc.c +// +// HAL misc board support code for Intel XScale GRG +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-05 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_ixp425.h> // Hardware definitions +#include <cyg/hal/grg.h> // Platform specifics + +#include <cyg/infra/diag.h> // diag_printf + +// +// Platform specific initialization +// + +void +plf_hardware_init(void) +{ +#ifdef CYGPKG_IO_PCI + extern void hal_plf_pci_init(void); + hal_plf_pci_init(); +#endif +} + +// ------------------------------------------------------------------------ +// EOF grg_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/grg/current/src/grg_pci.c @@ -0,0 +1,133 @@ +//========================================================================== +// +// grg_pci.c +// +// HAL PCI board support code for Intel XScale GRG +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2003-02-05 +// Purpose: HAL PCI board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGPKG_IO_PCI + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // calling interface API +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/io/pci_hw.h> +#include <cyg/io/pci.h> + + +#define IXP425_PCI_MAX_DEV 4 +#define IXP425_PCI_IRQ_LINES 4 + +// PCI pin mappings +#define PCI_CLK_GPIO 14 // CLK0 +#define PCI_RESET_GPIO 12 +#define PCI_INTA_GPIO 11 + +#define INTA CYGNUM_HAL_INTERRUPT_GPIO11 + +void +cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn, + CYG_ADDRWORD *vec, cyg_bool *valid) +{ + *vec = INTA; + *valid = true; +} + + +#define HAL_PCI_CLOCK_ENABLE() \ + *IXP425_GPCLKR |= GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock + +#define HAL_PCI_CLOCK_DISABLE() \ + *IXP425_GPCLKR &= ~GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock + +#define HAL_PCI_CLOCK_CONFIG() \ + *IXP425_GPCLKR |= GPCLKR_CLK0_PCLK2; + +#define HAL_PCI_RESET_ASSERT() \ + HAL_GPIO_OUTPUT_CLEAR(PCI_RESET_GPIO); + +#define HAL_PCI_RESET_DEASSERT() \ + HAL_GPIO_OUTPUT_SET(PCI_RESET_GPIO); + +void +hal_plf_pci_init(void) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + HAL_PCI_RESET_ASSERT(); + HAL_PCI_CLOCK_DISABLE(); + + // Set GPIO line direction + HAL_GPIO_OUTPUT_ENABLE(PCI_CLK_GPIO); + HAL_GPIO_OUTPUT_ENABLE(PCI_RESET_GPIO); + HAL_GPIO_OUTPUT_DISABLE(PCI_INTA_GPIO); + + // configure PCI interrupt lines for active low irq + HAL_INTERRUPT_CONFIGURE(INTA, 1, 0); + + // wait 1ms to satisfy "minimum reset assertion time" of the PCI spec. + HAL_DELAY_US(1000); + HAL_PCI_CLOCK_CONFIG(); + HAL_PCI_CLOCK_ENABLE(); + + // wait 100us to satisfy "minimum reset assertion time from clock stable" + // requirement of the PCI spec. + HAL_DELAY_US(100); + HAL_PCI_RESET_DEASSERT(); +#endif +} + +#endif // CYGPKG_IO_PCI
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/ChangeLog @@ -0,0 +1,107 @@ +2003-02-22 Mark Salter <msalter@redhat.com> + + * misc/redboot_ROM.ecm: Fix linux exec address. + * misc/redboot_RAM.ecm: Ditto + + * cdl/hal_arm_xscale_ixdp425.cdl: Fix HAL_PLATFORM_MACHINE_TYPE. + +2003-02-13 Mark Salter <msalter@redhat.com> + + * include/hal_platform_extras.h: Move uncached area. Create RAM + alias area. + +2003-02-12 Mark Salter <msalter@redhat.com> + + * misc/*.ecm: Turn on CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM. + +2003-01-28 Mark Salter <msalter@redhat.com> + + * misc/redboot_RAM.ecm: Turn on fileio support. + * misc/redboot_ROM.ecm: Ditto. + * misc/redboot_ROMRAM.ecm: Ditto. + +2003-01-22 Mark Salter <msalter@redhat.com> + + * include/hal_platform_setup.h: Tweak LED display. + +2002-12-20 Mark Salter <msalter@redhat.com> + + * include/hal_plf_ints.h: Don't use watchdog reset (CPU errata). + +2002-12-19 Mark Salter <msalter@redhat.com> + + * include/ixdp425.h (IXP425_EXP_CS0_INIT): Add in bit to allow + 8-bit access to 16-bit device. + + * cdl/hal_arm_xscale_ixdp425.cdl: Add back ROM startup now that + bus controller supports 8-bit access to flash. + + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.h: Add. + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.ldi: Ditto. + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.mlt: Ditto. + + * misc/redboot_RAM.ecm: Allow flash verify. + * misc/redboot_ROMRAM.ecm: Ditto. + * misc/redboot_ROM.ecm: Add. + +2002-12-18 Mark Salter <msalter@redhat.com> + + * src/ixdp425_pci.c (cyg_hal_plf_pci_translate_interrupt): Fix + interrupt vector determination. + + * include/pkgconf/mlt_arm_xscale_ixdp425_ram.mlt: Adjust start to + work with romram startup. + * include/pkgconf/mlt_arm_xscale_ixdp425_ram.ldi: Ditto. + +2002-12-17 Mark Salter <msalter@redhat.com> + + * misc/redboot_ROMRAM.ecm: New file. + * misc/redboot_ROM.ecm: Remove. + + * include/ixdp425.h: Don't define DCACHE_FLUSH_AREA. + + * include/hal_platform_setup.h: Support ROMRAM. + * include/hal_platform_extras.h: Ditto. + * cdl/hal_arm_xscale_ixdp425.cdl: Ditto. + + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.h: Remove. + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.ldi: Ditto. + * include/pkgconf/mlt_arm_xscale_ixdp425_rom.mlt: Ditto. + * include/pkgconf/mlt_arm_xscale_ixdp425_romram.h: New file. + * include/pkgconf/mlt_arm_xscale_ixdp425_romram.ldi: Ditto. + * include/pkgconf/mlt_arm_xscale_ixdp425_romram.mlt: Ditto. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/cdl/hal_arm_xscale_ixdp425.cdl @@ -0,0 +1,300 @@ +# ==================================================================== +# +# hal_arm_xscale_ixdp425.cdl +# +# Intel XScale IXDP425 Network Processor Eval Board HAL package +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Contributors: msalter +# Date: 2002-12-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_XSCALE_IXDP425 { + display "Intel XScale IXDP425 Network Processor Development Platform" + parent CYGPKG_HAL_ARM_XSCALE + implements CYGINT_HAL_ARM_BIGENDIAN + hardware + include_dir cyg/hal + define_header hal_arm_xscale_ixdp425.h + description " + This HAL platform package provides support for + the Intel XScale IXDP425 board." + + compile ixdp425_misc.c ixdp425_pci.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_xscale_ixp425.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_xscale_ixdp425.h>" + puts $::cdl_header "#define CYGBLD_HAL_PLF_INTS_H <cyg/hal/hal_plf_ints.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"IXDP425 Development Platform\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 245" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targeting the IXDP425 eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as RedBoot or eCos GDB stubs." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=xscale -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -mapcs-frame" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=xscale -mbig-endian -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ + } + } + } + + cdl_component CYGPKG_HAL_ARM_XSCALE_IXDP425_OPTIONS { + display "Intel XScale Ixdp425 build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_XSCALE_IXDP425_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale Ixdp425 HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_XSCALE_IXDP425_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale Ixdp425 HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { + display "Number of breakpoints supported by the HAL." + flavor data + default_value 32 + description " + This option determines the number of breakpoints supported by the HAL." + } + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART1 { + display "IXDP425 uses IXP425 high-speed UART" + flavor bool + default_value 1 + description " + Enable this option if the IXP425 high-speed UART is used + as a virtual vector communications channel." + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART2 { + display "IXDP425 uses IXP425 console UART" + flavor bool + default_value 1 + description " + Enable this option if the IXP425 console UART is to be used + as a virtual vector communications channel." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_xscale_ixdp425_ram" : \ + "arm_xscale_ixdp425_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_xscale_ixdp425_ram.ldi>" : \ + "<pkgconf/mlt_arm_xscale_ixdp425_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_xscale_ixdp425_ram.h>" : \ + "<pkgconf/mlt_arm_xscale_ixdp425_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/hal_platform_extras.h @@ -0,0 +1,205 @@ +#ifndef CYGONCE_HAL_PLATFORM_EXTRAS_H +#define CYGONCE_HAL_PLATFORM_EXTRAS_H + +/*============================================================================= +// +// hal_platform_extras.h +// +// Platform specific MMU table. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-08 +// Purpose: Intel XScale IXDP425 platform specific mmu table +// Description: +// Usage: #include <cyg/hal/hal_platform_extras.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#if defined(CYG_HAL_STARTUP_ROMRAM) + .section .text + .ltorg + .p2align 13 +#else + .section .mmu_tables, "a" +#endif + + mmu_table: + // This page table sets up the preferred mapping: + // + // Virtual Address Physical Address XCB Size (MB) Description + // --------------- ---------------- --- --------- ----------- + // 0x00000000 0x00000000 010 256 SDRAM (cached) + // 0x10000000 0x10000000 010 256 SDRAM (alias) + // 0x20000000 0x00000000 000 256 SDRAM (uncached) + // 0x48000000 0x48000000 000 64 PCI Data + // 0x50000000 0x50000000 010 16 Flash (CS0) + // 0x51000000 0x51000000 000 112 CS1 - CS7 + // 0x60000000 0x60000000 000 64 Queue Manager + // 0xC0000000 0xC0000000 000 1 PCI Controller + // 0xC4000000 0xC4000000 000 1 Exp. Bus Config + // 0xC8000000 0xC8000000 000 1 Misc IXP425 IO + // 0xCC000000 0xCC000000 000 1 SDRAM Config + + // 256MB SDRAM + .set __base,0x000 + .rept 0x100 - 0x000 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // 256MB SDRAM (alias) + .rept 0x200 - 0x100 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // 256MB SDRAM (uncached) + .set __base,0x000 + .rept 0x300 - 0x200 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 384MB Unused + .set __base,0x300 + .rept 0x480 - 0x300 + .word 0 + .set __base,__base+1 + .endr + + // 64MB PCI Data + .rept 0x4C0 - 0x480 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 64MB Unused + .rept 0x500 - 0x4C0 + .word 0 + .set __base,__base+1 + .endr + + // 16MB Flash (Expansion bus CS0) + .rept 0x510 - 0x500 + FL_SECTION_ENTRY __base,0,3,0,0,1,0 + .set __base,__base+1 + .endr + + // Rest of Expansion bus (CS1-CS7) + .rept 0x600 - 0x510 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 64MB Queue Manager + .rept 0x640 - 0x600 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 1472MB Unused + .rept 0xC00 - 0x640 + .word 0 + .set __base,__base+1 + .endr + + // 1MB PCI Controller + .rept 0xC01 - 0xC00 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xC40 - 0xC01 + .word 0 + .set __base,__base+1 + .endr + + // 1MB Expansion bus config + .rept 0xC41 - 0xC40 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xC80 - 0xC41 + .word 0 + .set __base,__base+1 + .endr + + // 1MB Misc IO + .rept 0xC81 - 0xC80 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xCC0 - 0xC81 + .word 0 + .set __base,__base+1 + .endr + + // 1MB SDRAM Config + .rept 0xCC1 - 0xCC0 + FL_SECTION_ENTRY __base,0,3,0,0,0,0 + .set __base,__base+1 + .endr + + // 63MB Unused + .rept 0xD00 - 0xCC1 + .word 0 + .set __base,__base+1 + .endr + + // Rest is Unused + .rept 0x1000 - 0xD00 + .word 0 + .set __base,__base+1 + .endr + +#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */ + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_extras.h */ +#endif /* CYGONCE_HAL_PLATFORM_EXTRAS_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/hal_platform_setup.h @@ -0,0 +1,340 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-10 +// Purpose: Intel XScale IXPD specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// Only used by "vectors.S" +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/hal_mm.h> // more MMU definitions +#include <cyg/hal/ixdp425.h> // Platform specific hardware definitions + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 _platform_setup1 +#define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h> +#define CYGHWR_HAL_ARM_HAS_MMU + +// ------------------------------------------------------------------------ +// Define macro used to diddle the LEDs during early initialization. +// Can use r0+r1. Argument in \x. +#define CYGHWR_LED_MACRO DISPLAY \x, r0, r1 + +// Delay a bit +.macro DELAY cycles, reg0 +#if 0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc +#endif +.endm + +// ------------------------------------------------------------------------ +// This macro represents the initial startup code for the platform + .macro _platform_setup1 + +#ifdef CYGINT_HAL_ARM_BIGENDIAN + // set big-endian + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x80 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 +#endif + + ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr, r0 + + // invalidate I & D caches & BTB + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + // invalidate I & Data TLB + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + // drain write and fill buffers + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + // disable write buffer coalescing + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 1 + CPWAIT r0 + + // Setup chip selects + ldr r1, =IXP425_EXP_CFG_BASE +#ifdef IXP425_EXP_CS0_INIT + ldr r0, =IXP425_EXP_CS0_INIT + str r0, [r1, #IXP425_EXP_CS0] +#endif +#ifdef IXP425_EXP_CS1_INIT + ldr r0, =IXP425_EXP_CS1_INIT + str r0, [r1, #IXP425_EXP_CS1] +#endif +#ifdef IXP425_EXP_CS2_INIT + ldr r0, =IXP425_EXP_CS2_INIT + str r0, [r1, #IXP425_EXP_CS2] +#endif +#ifdef IXP425_EXP_CS3_INIT + ldr r0, =IXP425_EXP_CS3_INIT + str r0, [r1, #IXP425_EXP_CS3] +#endif +#ifdef IXP425_EXP_CS4_INIT + ldr r0, =IXP425_EXP_CS4_INIT + str r0, [r1, #IXP425_EXP_CS4] +#endif +#ifdef IXP425_EXP_CS5_INIT + ldr r0, =IXP425_EXP_CS5_INIT + str r0, [r1, #IXP425_EXP_CS5] +#endif +#ifdef IXP425_EXP_CS6_INIT + ldr r0, =IXP425_EXP_CS6_INIT + str r0, [r1, #IXP425_EXP_CS6] +#endif +#ifdef IXP425_EXP_CS7_INIT + ldr r0, =IXP425_EXP_CS7_INIT + str r0, [r1, #IXP425_EXP_CS7] +#endif + + DISPLAY 0x1001, r7, r8 + + // Enable the Icache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + DISPLAY 0x1002, r7, r8 + + // Setup SDRAM controller + + ldr r0, =IXP425_SDRAM_CFG_BASE + + ldr r1, =IXP425_SDRAM_CONFIG_INIT + str r1, [r0, #IXP425_SDRAM_CONFIG] + + // disable refresh cycles + mov r1, #0 + str r1, [r0, #IXP425_SDRAM_REFRESH] + + // send nop command + mov r1, #SDRAM_IR_NOP + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // set SDRAM internal refresh val + ldr r1, =IXP425_SDRAM_REFRESH_CNT + str r1, [r0, #IXP425_SDRAM_REFRESH] + DELAY 0x10000, r1 + + // send precharge-all command to close all open banks + mov r1, #SDRAM_IR_PRECHARGE + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // provide 8 auto-refresh cycles + mov r1, #SDRAM_IR_AUTO_REFRESH + mov r2, #8 + 1: + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x800, r3 + subs r2, r2, #1 + bne 1b + + // set mode register in sdram + mov r1, #IXP425_SDRAM_SET_MODE_CMD + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // start normal operation + mov r1, #SDRAM_IR_NORMAL + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + DISPLAY 0x1003, r7, r8 + +#if defined(CYG_HAL_STARTUP_ROMRAM) + ldr r0,=0x00000000 + ldr r1,=0x10000000 + ldr r2,=__bss_start + 0: ldr r3,[r0],#4 + str r3,[r1],#4 + cmp r0,r2 + bne 0b +#endif + + // value to load into pc to jump to real runtime address + ldr r0, =1f + + // Setup EXP_CNFG0 value to switch EXP bus out of low memory + ldr r2, =IXP425_EXP_CFG_BASE + ldr r1, [r2, #IXP425_EXP_CNFG0] + bic r1, r1, #EXP_CNFG0_MEM_MAP + ldr r3, =0xFFFF + ldr r4, =IXDP425_LED_DATA + + b icache_boundary + .p2align 5 +icache_boundary: + // Here is where we switch from boot address (0x000000000) to the + // actual flash runtime address. We align to cache boundary so we + // execute from cache during the switchover. Cachelines are 8 words. + str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch + nop + nop + nop + nop + mov pc, r0 + strh r3, [r4] // We should never reach this point. If we do, + // display FFFF and loop forever. + 0: b 0b + 1: + + DISPLAY 0x1004, r7, r8 + +#if defined(CYG_HAL_STARTUP_ROM) + // Move mmu tables into RAM so page table walks by the cpu + // don't interfere with FLASH programming. + ldr r0, =mmu_table + add r2, r0, #0x4000 // End of tables + mov r1, #SDRAM_PHYS_BASE + orr r1, r1, #0x4000 // RAM tables + + // everything can go as-is + 1: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r0, r2 + bne 1b +#endif + + DISPLAY 0x1005, r7, r8 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // Set the TTB register to DRAM mmu_table + ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables + mcr p15, 0, r0, c2, c0, 0 // load page table pointer + CPWAIT r0 + + // enable permission checks in all domains + ldr r0, =0x55555555 + mcr p15, 0, r0, c3, c0, 0 + CPWAIT r0 + + DISPLAY 0x1006, r7, r8 + + // enable mmu + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_M + orr r0, r0, #MMU_Control_R + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + DISPLAY 0x1007, r7, r8 + + // enable D cache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_C + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + DISPLAY 0x1008, r7, r8 + + // Enable branch target buffer + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_BTB + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + DISPLAY 0x1009, r7, r8 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB + CPWAIT r0 + + mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs + CPWAIT r0 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + DISPLAY 0x100A, r7, r8 + + // save SDRAM size + ldr r1, =hal_dram_size /* [see hal_intr.h] */ + mov r8, #SDRAM_SIZE + str r8, [r1] + + DISPLAY 0x100B, r7, r8 + + .endm // _platform_setup1 + +#else // defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 +#endif + +#define PLATFORM_VECTORS _platform_vectors + .macro _platform_vectors + .endm + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/hal_plf_ints.h @@ -0,0 +1,78 @@ +#ifndef CYGONCE_HAL_PLF_INTS_H +#define CYGONCE_HAL_PLF_INTS_H +//========================================================================== +// +// hal_plf_ints.h +// +// HAL Platform Interrupt support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-07-15 +// Purpose: Define Interrupt support +// Description: The interrupt details for a specific platform is defined here. +// Usage: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// start with variant ints +#include CYGBLD_HAL_VAR_INTS_H + +// NB: Commented out because of errata on reset function of watchdog timer +// +#if 0 +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + cyg_uint32 __ctrl; \ + /* By disabling interupts we will just hang in the loop below */ \ + /* if for some reason the software reset fails. */ \ + HAL_DISABLE_INTERRUPTS(__ctrl); \ + *IXP425_OST_WDOG_KEY = 0x482e; \ + *IXP425_OST_WDOG = 10; \ + *IXP425_OST_WDOG_ENA = 5; \ + for(;;); /* hang here forever if reset fails */ \ + CYG_MACRO_END +#else +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT +#endif + +#endif // CYGONCE_HAL_PLF_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/ixdp425.h @@ -0,0 +1,115 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_IXDP425_IXDP425_H +#define CYGONCE_HAL_ARM_XSCALE_IXDP425_IXDP425_H + +/*============================================================================= +// +// ixdp425.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-10 +// Purpose: Intel IXDP425 specific support routines +// Description: +// Usage: #include <cyg/hal/ixdp425.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <pkgconf/hal_arm_xscale_ixdp425.h> +#include <cyg/hal/hal_ixp425.h> + +// These must match setup in the page table in hal_platform_extras.h +#define SDRAM_PHYS_BASE 0x00000000 +#define SDRAM_BASE 0x00000000 +#define SDRAM_UNCACHED_BASE 0x10000000 +#define SDRAM_SIZE 0x10000000 // 256MB + +#define IXDP425_LED_DATA REG16(0, 0x52000000) + +// CS0 (flash optimum timing) +#define IXP425_EXP_CS0_INIT \ + (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \ + EXP_RECOVERY_T(15) | EXP_SZ_16M | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN) + +// CS2 (LED display) +#define IXP425_EXP_CS2_INIT \ + (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \ + EXP_RECOVERY_T(15) | EXP_SZ_512 | EXP_WR_EN | EXP_CS_EN) + +#define IXP425_SDRAM_CONFIG_INIT (SDRAM_CONFIG_CAS_3 | SDRAM_CONFIG_4x32Mx16) +#define IXP425_SDRAM_REFRESH_CNT 0x081 +#define IXP425_SDRAM_SET_MODE_CMD SDRAM_IR_MODE_SET_CAS3 + + +// ------------------------------------------------------------------------ +// 4 Digit Hex Display +// +// The board has two 4 hex digit display controlled by three board registers. +// Each digit has a decimal point and may be individually blanked. + +#ifdef __ASSEMBLER__ + // Display hex digits in 'value' not masked by 'mask'. + .macro DISPLAY value, reg0, reg1 + ldr \reg0, =\value + ldr \reg1, =IXDP425_LED_DATA + strh \reg0, [\reg1] +#if 0 + // delay + ldr \reg0, =0x780000 + 0: + subs \reg0, \reg0, #1 + bne 0b +#endif + .endm +#else +static inline void HEX_DISPLAY(int value) +{ + *IXDP425_LED_DATA = value; +} +#endif // __ASSEMBLER__ + +// ------------------------------------------------------------------------ + +#endif // CYGONCE_HAL_ARM_XSCALE_IXDP425_IXDP425_H +// EOF ixdp425.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_ram.h @@ -0,0 +1,18 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x10000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x10000000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x10000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x20000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_ram.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 10000000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 20000 20000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x10000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x10000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_rom.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x10000000 + rom : ORIGIN = 0x50000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.mmu_tables)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/pkgconf/mlt_arm_xscale_ixdp425_rom.mlt @@ -0,0 +1,15 @@ +version 0 +region ram 0 10000000 0 ! +region rom 50000000 40000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 mmu_tables mmu_tables ! +section mmu_tables 0 4000 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/include/plf_io.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-01-10 +// Purpose: Intel IXDP425 IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/ixdp425.h> +#include CYGBLD_HAL_PLF_INTS_H + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/misc/redboot_RAM.ecm @@ -0,0 +1,124 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ixdp425 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXDP425 current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_IXDP425 current ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ; + package -hardware CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x6000000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_option CYGOPT_DEVS_FLASH_STRATA_NOT_IN_RAM { + inferred_value 0 +} + +cdl_component CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM { + user_value 1 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/misc/redboot_ROM.ecm @@ -0,0 +1,128 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ixdp425 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXDP425 current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_IXDP425 current ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ; + package -hardware CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x6000000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM { + user_value 1 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/src/ixdp425_misc.c @@ -0,0 +1,85 @@ +//========================================================================== +// +// ixdp425_misc.c +// +// HAL misc board support code for Intel XScale IXDP425 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-11 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_ixp425.h> // Hardware definitions +#include <cyg/hal/ixdp425.h> // Platform specifics + +#include <cyg/infra/diag.h> // diag_printf + +// +// Platform specific initialization +// + +void +plf_hardware_init(void) +{ +#ifdef CYGPKG_IO_PCI + extern void hal_plf_pci_init(void); + hal_plf_pci_init(); +#endif +} + +// ------------------------------------------------------------------------ +// EOF ixdp425_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixdp425/current/src/ixdp425_pci.c @@ -0,0 +1,160 @@ +//========================================================================== +// +// ixdp425_pci.c +// +// HAL PCI board support code for Intel XScale IXDP425 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-11 +// Purpose: HAL PCI board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // calling interface API +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/io/pci_hw.h> +#include <cyg/io/pci.h> + +#ifdef CYGPKG_IO_PCI + +#define IXP425_PCI_MAX_DEV 4 +#define IXP425_PCI_IRQ_LINES 4 + +// PCI pin mappings +#define PCI_CLK_GPIO 14 // CLK0 +#define PCI_RESET_GPIO 13 +#define PCI_INTA_GPIO 11 +#define PCI_INTB_GPIO 10 +#define PCI_INTC_GPIO 9 +#define PCI_INTD_GPIO 8 + +#define INTA CYGNUM_HAL_INTERRUPT_GPIO11 +#define INTB CYGNUM_HAL_INTERRUPT_GPIO10 +#define INTC CYGNUM_HAL_INTERRUPT_GPIO9 +#define INTD CYGNUM_HAL_INTERRUPT_GPIO8 + +static const int pci_irq_table[IXP425_PCI_MAX_DEV][IXP425_PCI_IRQ_LINES] = { + {INTA, INTB, INTC, INTD}, + {INTB, INTC, INTD, INTA}, + {INTC, INTD, INTA, INTB}, + {INTD, INTA, INTB, INTC} +}; + +void +cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn, + CYG_ADDRWORD *vec, cyg_bool *valid) +{ + cyg_uint8 pin; + cyg_uint32 slot = 3 - (CYG_PCI_DEV_GET_DEV(devfn) - 18); + + HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, pin); + *vec = -1; + *valid = false; + + if (slot < IXP425_PCI_MAX_DEV && pin <= IXP425_PCI_IRQ_LINES) { + *vec = pci_irq_table[slot][pin-1]; + *valid = true; + } +} + + +#define HAL_PCI_CLOCK_ENABLE() \ + *IXP425_GPCLKR |= GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock + +#define HAL_PCI_CLOCK_DISABLE() \ + *IXP425_GPCLKR &= ~GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock + +#define HAL_PCI_CLOCK_CONFIG() \ + *IXP425_GPCLKR |= GPCLKR_CLK0_PCLK2; + +#define HAL_PCI_RESET_ASSERT() \ + HAL_GPIO_OUTPUT_CLEAR(PCI_RESET_GPIO); + +#define HAL_PCI_RESET_DEASSERT() \ + HAL_GPIO_OUTPUT_SET(PCI_RESET_GPIO); + +void +hal_plf_pci_init(void) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + HAL_PCI_RESET_ASSERT(); + HAL_PCI_CLOCK_DISABLE(); + + // Set GPIO line direction + HAL_GPIO_OUTPUT_ENABLE(PCI_CLK_GPIO); + HAL_GPIO_OUTPUT_ENABLE(PCI_RESET_GPIO); + HAL_GPIO_OUTPUT_DISABLE(PCI_INTA_GPIO); + HAL_GPIO_OUTPUT_DISABLE(PCI_INTB_GPIO); + HAL_GPIO_OUTPUT_DISABLE(PCI_INTC_GPIO); + HAL_GPIO_OUTPUT_DISABLE(PCI_INTD_GPIO); + + // configure PCI interrupt lines for active low irq + HAL_INTERRUPT_CONFIGURE(INTA, 1, 0); + HAL_INTERRUPT_CONFIGURE(INTB, 1, 0); + HAL_INTERRUPT_CONFIGURE(INTC, 1, 0); + HAL_INTERRUPT_CONFIGURE(INTD, 1, 0); + + // wait 1ms to satisfy "minimum reset assertion time" of the PCI spec. + HAL_DELAY_US(1000); + HAL_PCI_CLOCK_CONFIG(); + HAL_PCI_CLOCK_ENABLE(); + + // wait 100us to satisfy "minimum reset assertion time from clock stable" + // requirement of the PCI spec. + HAL_DELAY_US(100); + HAL_PCI_RESET_DEASSERT(); +#endif +} + +#endif // CYGPKG_IO_PCI
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/ChangeLog @@ -0,0 +1,66 @@ +2003-02-22 Mark Salter <msalter@redhat.com> + + * src/ixp425_pci.c (cyg_hal_plf_pci_init): Don't reinit PCI + controller on warm reset. + * cdl/hal_arm_xscale_ixp425.cdl: Fix requirement for linux exec + address. + +2003-02-13 Mark Salter <msalter@redhat.com> + + * include/var_io.h (CYGARC_UNCACHED_ADDRESS): Move uncached area. + +2003-02-07 Mark Salter <msalter@redhat.com> + + * src/ixp425_diag.c: Support platform config of ports used. + * src/ixp425_misc.c: Ditto. + * src/ixp425_pci.c: Ditto. + + * include/var_io.h: Fix compile errors when building without PCI. + +2002-12-19 Mark Salter <msalter@redhat.com> + + * include/hal_ixp425.h (EXP_BYTE_RD16): New definition. + +2002-12-18 Mark Salter <msalter@redhat.com> + + * src/ixp425_misc.c (hal_interrupt_configure): Fix tests and + GPIO register selection. + +2002-12-17 Mark Salter <msalter@redhat.com> + + * src/ixp425_pci.c (cyg_hal_plf_pci_init): Fix PCI read/write functions. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/cdl/hal_arm_xscale_ixp425.cdl @@ -0,0 +1,208 @@ +# ==================================================================== +# +# hal_arm_xscale_ixp425.cdl +# +# Intel XScale architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: msalter +# Contributors: +# Date: 2002-12-06 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_XSCALE_IXP425 { + display "Intel XScale IXP425 Network Processor" + parent CYGPKG_HAL_ARM + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + hardware + include_dir cyg/hal + define_header hal_arm_xscale_ixp425.h + description " + This HAL variant package provides generic support + for the Intel IXP425 network processors. It is also + necessary to select a specific target platform HAL + package." + + # Let the architectural HAL see this variant's interrupts file + define_proc { + puts $::cdl_header \ + "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>" + puts $::cdl_header \ + "#define CYGBLD_HAL_VAR_H <cyg/hal/hal_ixp425.h>" + + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" + } + + compile ixp425_misc.c ixp425_pci.c ixp425_diag.c + + cdl_option CYGHWR_HAL_ARM_XSCALE_PROCESSOR_CCLK { + display "Processor clock rate" + flavor data + default_value { CYGHWR_HAL_ARM_XSCALE_PROCESSOR_CCLK_DEFAULT ? + CYGHWR_HAL_ARM_XSCALE_PROCESSOR_CCLK_DEFAULT : 533333} + description " + The XScale processor can run at various frequencies. + These values are expressed in KHz." + } + + cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + display "Enable IXP425 PCI NP read problem workaround" + flavor bool + default_value 0 + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + description " + This option selects the heartbeat rate for the real-time clock. + The rate is specified in ticks per second. Change this value + with caution - too high and your system will become saturated + just handling clock interrupts, too low and some operations + such as thread scheduling may become sluggish." + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated 1000000/CYGNUM_HAL_RTC_DENOMINATOR + description " + This value gives the RTC period in microseconds. It is + translated into the actual clock period value in the clock + init and read functions." + } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_ARM_IXP425_SERIAL_CHANNELS { + display "Number of IXP425 serial ports used on the board" + flavor data + calculated { (CYGSEM_HAL_IXP425_PLF_USES_UART1 && CYGSEM_HAL_IXP425_PLF_USES_UART2) ? 2 : \ + (CYGSEM_HAL_IXP425_PLF_USES_UART1 || CYGSEM_HAL_IXP425_PLF_USES_UART2) ? 1 : \ + 0 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated { CYGNUM_HAL_ARM_IXP425_SERIAL_CHANNELS + \ + CYGNUM_HAL_IXP425_PLF_SERIAL_CHANNELS } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + IXP425 boards may use two or more serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "Debug serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the GDB port." + } + + cdl_component CYGPKG_REDBOOT_XSCALE_OPTIONS { + display "Redboot for XScale options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + # RedBoot details + requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT != 0 } + define_proc { + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/include/hal_diag.h @@ -0,0 +1,94 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_if.h> + +/*---------------------------------------------------------------------------*/ + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +// Not the best place for this, but ... +extern void hal_delay_us(cyg_int32 usecs); + +#define HAL_DELAY_US(n) hal_delay_us(n); + +#else + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c */ + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +#define HAL_DIAG_INIT() hal_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/include/hal_ixp425.h @@ -0,0 +1,302 @@ +/*============================================================================= +// +// hal_ixp425.h +// +// IXP425 Network Processor support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-08 +// Purpose: +// Description: IXP425 Processor support. +// Usage: #include <cyg/hal/hal_ixp425.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ +#ifndef CYGONCE_HAL_ARM_XSCALE_HAL_IXP425_H +#define CYGONCE_HAL_ARM_XSCALE_HAL_IXP425_H + +#include <pkgconf/system.h> +#include <cyg/hal/hal_xscale.h> + +// -------------------------------------------------------------------------- +// PCI Registers (Chapter 6) +#define IXP425_PCI_CFG_BASE 0xC0000000 +#define IXP425_PCI_NP_AD REG32(IXP425_PCI_CFG_BASE,0x00) +#define IXP425_PCI_NP_CBE REG32(IXP425_PCI_CFG_BASE,0x04) +#define IXP425_PCI_NP_WDATA REG32(IXP425_PCI_CFG_BASE,0x08) +#define IXP425_PCI_NP_RDATA REG32(IXP425_PCI_CFG_BASE,0x0C) +#define IXP425_PCI_CRP_AD_CPE REG32(IXP425_PCI_CFG_BASE,0x10) +#define IXP425_PCI_CRP_WDATA REG32(IXP425_PCI_CFG_BASE,0x14) +#define IXP425_PCI_CRP_RDATA REG32(IXP425_PCI_CFG_BASE,0x18) +#define IXP425_PCI_CSR REG32(IXP425_PCI_CFG_BASE,0x1C) +#define IXP425_PCI_ISR REG32(IXP425_PCI_CFG_BASE,0x20) +#define IXP425_PCI_INTEN REG32(IXP425_PCI_CFG_BASE,0x24) +#define IXP425_PCI_DMACTRL REG32(IXP425_PCI_CFG_BASE,0x28) +#define IXP425_PCI_AHBMEMBASE REG32(IXP425_PCI_CFG_BASE,0x2C) +#define IXP425_PCI_AHBIOBASE REG32(IXP425_PCI_CFG_BASE,0x30) +#define IXP425_PCI_PCIMEMBASE REG32(IXP425_PCI_CFG_BASE,0x34) +#define IXP425_PCI_AHBDOORBELL REG32(IXP425_PCI_CFG_BASE,0x38) +#define IXP425_PCI_PCIDOORBELL REG32(IXP425_PCI_CFG_BASE,0x3C) +#define IXP425_PCI_ATPDMA0_AHBADDR REG32(IXP425_PCI_CFG_BASE,0x40) +#define IXP425_PCI_ATPDMA0_PCIADDR REG32(IXP425_PCI_CFG_BASE,0x44) +#define IXP425_PCI_ATPDMA0_LENGTH REG32(IXP425_PCI_CFG_BASE,0x48) +#define IXP425_PCI_ATPDMA1_AHBADDR REG32(IXP425_PCI_CFG_BASE,0x4C) +#define IXP425_PCI_ATPDMA1_PCIADDR REG32(IXP425_PCI_CFG_BASE,0x50) +#define IXP425_PCI_ATPDMA1_LENGTH REG32(IXP425_PCI_CFG_BASE,0x54) +#define IXP425_PCI_PTADMA0_AHBADDR REG32(IXP425_PCI_CFG_BASE,0x58) +#define IXP425_PCI_PTADMA0_PCIADDR REG32(IXP425_PCI_CFG_BASE,0x5C) +#define IXP425_PCI_PTADMA0_LENGTH REG32(IXP425_PCI_CFG_BASE,0x60) +#define IXP425_PCI_PTADMA1_AHBADDR REG32(IXP425_PCI_CFG_BASE,0x64) +#define IXP425_PCI_PTADMA1_PCIADDR REG32(IXP425_PCI_CFG_BASE,0x68) +#define IXP425_PCI_PTADMA1_LENGTH REG32(IXP425_PCI_CFG_BASE,0x6C) + +// PCI_NP_CBE bits +#define PCI_NP_CMD_IOR 0x2 +#define PCI_NP_CMD_IOW 0x3 +#define PCI_NP_CMD_CONFIGR 0xA +#define PCI_NP_CMD_CONFIGW 0xB +#define PCI_NP_BE_SHIFT 4 + +// PCI_CRP_AD_CBE bits +#define PCI_CRP_AD_CBE_READ 0 +#define PCI_CRP_AD_CBE_WRITE (1 << 16) +#define PCI_CRP_AD_CBE_BE_SHIFT 20 + +// PCI_CSR bits +#define PCI_CSR_HOST (1 << 0) +#define PCI_CSR_ARBEN (1 << 1) +#define PCI_CSR_ADS (1 << 2) +#define PCI_CSR_PDS (1 << 3) +#define PCI_CSR_ABE (1 << 4) +#define PCI_CSR_DBT (1 << 5) +#define PCI_CSR_ASE (1 << 8) +#define PCI_CSR_IC (1 << 15) +#define PCI_CSR_PRST (1 << 16) + +// PCI_ISR bits +#define PCI_ISR_PSE (1 << 0) +#define PCI_ISR_PFE (1 << 1) +#define PCI_ISR_PPE (1 << 2) +#define PCI_ISR_AHBE (1 << 3) +#define PCI_ISR_APDC (1 << 4) +#define PCI_ISR_PADC (1 << 5) +#define PCI_ISR_ADB (1 << 6) +#define PCI_ISR_PDB (1 << 7) + +// PCI_INTEN bits +#define PCI_INTEN_PSE (1 << 0) +#define PCI_INTEN_PFE (1 << 1) +#define PCI_INTEN_PPE (1 << 2) +#define PCI_INTEN_AHBE (1 << 3) +#define PCI_INTEN_APDC (1 << 4) +#define PCI_INTEN_PADC (1 << 5) +#define PCI_INTEN_ADB (1 << 6) +#define PCI_INTEN_PDB (1 << 7) + +// -------------------------------------------------------------------------- +// SDRAM Registers (Chapter 7) +#define IXP425_SDRAM_CFG_BASE 0xCC000000 +#define IXP425_SDRAM_CONFIG REG32(IXP425_SDRAM_CFG_BASE,0x00) +#define IXP425_SDRAM_REFRESH REG32(IXP425_SDRAM_CFG_BASE,0x04) +#define IXP425_SDRAM_IR REG32(IXP425_SDRAM_CFG_BASE,0x08) + +// SDRAM_CONFIG bits +#define SDRAM_CONFIG_2x8Mx16 0 +#define SDRAM_CONFIG_4x8Mx16 1 +#define SDRAM_CONFIG_2x16Mx16 2 +#define SDRAM_CONFIG_4x16Mx16 3 +#define SDRAM_CONFIG_2x32Mx16 4 +#define SDRAM_CONFIG_4x32Mx16 5 +#define SDRAM_CONFIG_CAS_3 (1 << 3) +#define SDRAM_CONFIG_RAS_3 (1 << 4) + +// SDRAM_IR commands +#define SDRAM_IR_MODE_SET_CAS2 0 +#define SDRAM_IR_MODE_SET_CAS3 1 +#define SDRAM_IR_PRECHARGE 2 +#define SDRAM_IR_NOP 3 +#define SDRAM_IR_AUTO_REFRESH 4 +#define SDRAM_IR_BURST_TERMINATE 5 +#define SDRAM_IR_NORMAL 6 + +// -------------------------------------------------------------------------- +// Expansion Bus Register (Chapter 9) +#define IXP425_EXP_CFG_BASE 0xC4000000 +#define IXP425_EXP_CS0 REG32(IXP425_EXP_CFG_BASE,0x00) +#define IXP425_EXP_CS1 REG32(IXP425_EXP_CFG_BASE,0x04) +#define IXP425_EXP_CS2 REG32(IXP425_EXP_CFG_BASE,0x08) +#define IXP425_EXP_CS3 REG32(IXP425_EXP_CFG_BASE,0x0C) +#define IXP425_EXP_CS4 REG32(IXP425_EXP_CFG_BASE,0x10) +#define IXP425_EXP_CS5 REG32(IXP425_EXP_CFG_BASE,0x14) +#define IXP425_EXP_CS6 REG32(IXP425_EXP_CFG_BASE,0x18) +#define IXP425_EXP_CS7 REG32(IXP425_EXP_CFG_BASE,0x1C) +#define IXP425_EXP_CNFG0 REG32(IXP425_EXP_CFG_BASE,0x20) +#define IXP425_EXP_CNFG1 REG32(IXP425_EXP_CFG_BASE,0x24) + +// EXP_CSn bits +#define EXP_BYTE_EN (1 << 0) +#define EXP_WR_EN (1 << 1) +#define EXP_SPLT_EN (1 << 3) +#define EXP_MUX_EN (1 << 4) +#define EXP_HRDY_POL (1 << 5) +#define EXP_BYTE_RD16 (1 << 6) +#define EXP_SZ_512 (0 << 10) +#define EXP_SZ_1K (1 << 10) +#define EXP_SZ_2K (2 << 10) +#define EXP_SZ_4K (3 << 10) +#define EXP_SZ_8K (4 << 10) +#define EXP_SZ_16K (5 << 10) +#define EXP_SZ_32K (6 << 10) +#define EXP_SZ_64K (7 << 10) +#define EXP_SZ_128K (8 << 10) +#define EXP_SZ_256K (9 << 10) +#define EXP_SZ_512K (10 << 10) +#define EXP_SZ_1M (11 << 10) +#define EXP_SZ_2M (12 << 10) +#define EXP_SZ_4M (13 << 10) +#define EXP_SZ_8M (14 << 10) +#define EXP_SZ_16M (15 << 10) +#define EXP_CYC_INTEL (0 << 14) +#define EXP_CYC_MOTO (1 << 14) +#define EXP_CYC_HPI (2 << 14) + +#define EXP_RECOVERY_SHIFT 16 +#define EXP_HOLD_SHIFT 20 +#define EXP_STROBE_SHIFT 22 +#define EXP_SETUP_SHIFT 26 +#define EXP_ADDR_SHIFT 28 +#define EXP_CS_EN (1 << 31) + +#define EXP_RECOVERY_T(x) (((x) & 15) << EXP_RECOVERY_SHIFT) +#define EXP_HOLD_T(x) (((x) & 3) << EXP_HOLD_SHIFT) +#define EXP_STROBE_T(x) (((x) & 15) << EXP_STROBE_SHIFT) +#define EXP_SETUP_T(x) (((x) & 3) << EXP_SETUP_SHIFT) +#define EXP_ADDR_T(x) (((x) & 3) << EXP_ADDR_SHIFT) + +// EXP_CNFG0 bits +#define EXP_CNFG0_8BIT (1 << 0) +#define EXP_CNFG0_PCI_HOST (1 << 1) +#define EXP_CNFG0_PCI_ARB (1 << 2) +#define EXP_CNFG0_PCI_66MHZ (1 << 4) +#define EXP_CNFG0_MEM_MAP (1 << 31) + +// EXP_CNFG1 bits +#define EXP_CNFG1_SW_INT0 (1 << 0) +#define EXP_CNFG1_SW_INT1 (1 << 1) + + +// -------------------------------------------------------------------------- +// GPIO (Chapter 13) +#define IXP425_GPIO_CFG_BASE 0xC8004000 +#define IXP425_GPOUTR REG32(IXP425_GPIO_CFG_BASE,0x00) +#define IXP425_GPOER REG32(IXP425_GPIO_CFG_BASE,0x04) +#define IXP425_GPINR REG32(IXP425_GPIO_CFG_BASE,0x08) +#define IXP425_GPISR REG32(IXP425_GPIO_CFG_BASE,0x0C) +#define IXP425_GPIT1R REG32(IXP425_GPIO_CFG_BASE,0x10) +#define IXP425_GPIT2R REG32(IXP425_GPIO_CFG_BASE,0x14) +#define IXP425_GPCLKR REG32(IXP425_GPIO_CFG_BASE,0x18) + +// GPCLKR bits +#define GPCLKR_CLK0DC_SHIFT 0 +#define GPCLKR_CLK0TC_SHIFT 4 +#define GPCLKR_CLK0_ENABLE (1 << 8) +#define GPCLKR_CLK1DC_SHIFT 16 +#define GPCLKR_CLK1TC_SHIFT 20 +#define GPCLKR_CLK1_ENABLE (1 << 24) + +#define GPCLKR_CLK0_PCLK2 \ + ((0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT)) + +#define GPCLKR_CLK1_PCLK2 \ + ((0xf << GPCLKR_CLK1DC_SHIFT) | (0xf << GPCLKR_CLK1TC_SHIFT)) + +#define HAL_GPIO_OUTPUT_ENABLE(line) \ + *IXP425_GPOER &= ~(1 << (line)) + +#define HAL_GPIO_OUTPUT_DISABLE(line) \ + *IXP425_GPOER |= (1 << (line)) + +#define HAL_GPIO_OUTPUT_SET(line) \ + *IXP425_GPOUTR |= (1 << (line)) + +#define HAL_GPIO_OUTPUT_CLEAR(line) \ + *IXP425_GPOUTR &= ~(1 << (line)) + +// -------------------------------------------------------------------------- +// Interrupts (Chapter 14) +#define IXP425_INTR_CFG_BASE 0xC8003000 +#define IXP425_INTR_ST REG32(IXP425_INTR_CFG_BASE,0x00) +#define IXP425_INTR_EN REG32(IXP425_INTR_CFG_BASE,0x04) +#define IXP425_INTR_SEL REG32(IXP425_INTR_CFG_BASE,0x08) +#define IXP425_INTR_IRQ_ST REG32(IXP425_INTR_CFG_BASE,0x0C) +#define IXP425_INTR_FIQ_ST REG32(IXP425_INTR_CFG_BASE,0x10) +#define IXP425_INTR_PRTY REG32(IXP425_INTR_CFG_BASE,0x14) +#define IXP425_INTR_IRQ_ENC_ST REG32(IXP425_INTR_CFG_BASE,0x18) +#define IXP425_INTR_FIQ_ENC_ST REG32(IXP425_INTR_CFG_BASE,0x18) + +// -------------------------------------------------------------------------- +// Timers (Chapter 15) +#define IXP425_OST_CFG_BASE 0xC8005000 +#define IXP425_OST_TS REG32(IXP425_OST_CFG_BASE,0x00) +#define IXP425_OST_TIM0 REG32(IXP425_OST_CFG_BASE,0x04) +#define IXP425_OST_TIM0_RL REG32(IXP425_OST_CFG_BASE,0x08) +#define IXP425_OST_TIM1 REG32(IXP425_OST_CFG_BASE,0x0C) +#define IXP425_OST_TIM1_RL REG32(IXP425_OST_CFG_BASE,0x10) +#define IXP425_OST_WDOG REG32(IXP425_OST_CFG_BASE,0x14) +#define IXP425_OST_WDOG_ENA REG32(IXP425_OST_CFG_BASE,0x18) +#define IXP425_OST_WDOG_KEY REG32(IXP425_OST_CFG_BASE,0x1C) +#define IXP425_OST_STS REG32(IXP425_OST_CFG_BASE,0x20) + +// OST_STS bits +#define OST_STS_T0INT 0x01 +#define OST_STS_T1INT 0x02 +#define OST_STS_TSINT 0x04 +#define OST_STS_WDOGINT 0x08 +#define OST_STS_RESET 0x10 + +// OST_TIMx_RL bits +#define OST_TIM_RL_ENABLE 0x01 +#define OST_TIM_RL_ONESHOT 0x02 +#define OST_TIM_RL_MASK 0xFFFFFFFC + + +#endif // CYGONCE_HAL_ARM_XSCALE_HAL_IXP425_H +// EOF hal_ixp425.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/include/hal_var_ints.h @@ -0,0 +1,126 @@ +#ifndef CYGONCE_HAL_VAR_INTS_H +#define CYGONCE_HAL_VAR_INTS_H +//========================================================================== +// +// hal_var_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2001-12-03 +// Purpose: Define Interrupt support +// Description: The interrupt details for XScale CPUs are defined here. +// Usage: +// #include <pkgconf/system.h> +// #include CYGBLD_HAL_VARIANT_H +// #include CYGBLD_HAL_VAR_INTS_H +// +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/hal_ixp425.h> // registers + +// +// Values for the vector argument of cyg_drv_interrupt_create() and +// other interrupt related interfaces. +// +#define CYGNUM_HAL_INTERRUPT_NONE -1 +#define CYGNUM_HAL_INTERRUPT_NPEA 0 +#define CYGNUM_HAL_INTERRUPT_NPEB 1 +#define CYGNUM_HAL_INTERRUPT_NPEC 2 +#define CYGNUM_HAL_INTERRUPT_QM1 3 +#define CYGNUM_HAL_INTERRUPT_QM2 4 +#define CYGNUM_HAL_INTERRUPT_TIMER0 5 +#define CYGNUM_HAL_INTERRUPT_GPIO0 6 +#define CYGNUM_HAL_INTERRUPT_GPIO1 7 +#define CYGNUM_HAL_INTERRUPT_PCI_INT 8 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 +#define CYGNUM_HAL_INTERRUPT_TIMER1 11 +#define CYGNUM_HAL_INTERRUPT_USB 12 +#define CYGNUM_HAL_INTERRUPT_UART2 13 +#define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_WDOG 16 +#define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 +#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 +#define CYGNUM_HAL_INTERRUPT_GPIO2 19 +#define CYGNUM_HAL_INTERRUPT_GPIO3 20 +#define CYGNUM_HAL_INTERRUPT_GPIO4 21 +#define CYGNUM_HAL_INTERRUPT_GPIO5 22 +#define CYGNUM_HAL_INTERRUPT_GPIO6 23 +#define CYGNUM_HAL_INTERRUPT_GPIO7 24 +#define CYGNUM_HAL_INTERRUPT_GPIO8 25 +#define CYGNUM_HAL_INTERRUPT_GPIO9 26 +#define CYGNUM_HAL_INTERRUPT_GPIO10 27 +#define CYGNUM_HAL_INTERRUPT_GPIO11 28 +#define CYGNUM_HAL_INTERRUPT_GPIO12 29 +#define CYGNUM_HAL_INTERRUPT_SW_INT1 30 +#define CYGNUM_HAL_INTERRUPT_SW_INT2 31 + +#define CYGNUM_HAL_VAR_ISR_MAX 31 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VAR_ISR_MAX + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) + +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 + +// ------------------------------------------------------------------------ +// Dynamically set the timer interrupt rate. +// Not for application use at all. + +externC void +hal_clock_reinitialize( int *pfreq, /* inout */ + unsigned int *pperiod, /* inout */ + unsigned int old_hz ); /* in */ + +#define HAL_CLOCK_REINITIALIZE( _freq, _period, _old_hz ) \ + hal_clock_reinitialize( &_freq, &_period, _old_hz ) + +#define HAL_PLATFORM_RESET_ENTRY 0x00000000 + +#endif // CYGONCE_HAL_VAR_INTS_H +// EOF hal_var_ints.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/include/var_io.h @@ -0,0 +1,234 @@ +#ifndef CYGONCE_HAL_ARM_IXP425_VAR_IO_H +#define CYGONCE_HAL_ARM_IXP425_VAR_IO_H + +/*============================================================================= +// +// var_io.h +// +// Platform specific support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-12 +// Purpose: IXP425 specific support routines +// Description: +// Usage: #include <cyg/hal/hal_io.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <cyg/hal/plf_io.h> + +//----------------------------------------------------------------------------- + +extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset); +extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset); +extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset); +extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint32 val); +extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint16 val); +extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint8 val); + +extern void cyg_hal_plf_pci_io_outb(cyg_uint32 offset, cyg_uint8 value); +extern void cyg_hal_plf_pci_io_outw(cyg_uint32 offset, cyg_uint16 value); +extern void cyg_hal_plf_pci_io_outl(cyg_uint32 offset, cyg_uint32 value); +extern cyg_uint8 cyg_hal_plf_pci_io_inb(cyg_uint32 offset); +extern cyg_uint16 cyg_hal_plf_pci_io_inw(cyg_uint32 offset); +extern cyg_uint32 cyg_hal_plf_pci_io_inl(cyg_uint32 offset); + +extern void cyg_hal_plf_pci_init(void); +#define HAL_PCI_INIT() cyg_hal_plf_pci_init() + + +// Translate the PCI interrupt requested by the device (INTA#, INTB#, +// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector). +extern void cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn, + CYG_ADDRWORD *vec, cyg_bool *valid); +#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid)\ + cyg_hal_plf_pci_translate_interrupt(__bus, __devfn, &(__vec), &(__valid)) + + +#ifdef CYGPKG_IO_PCI + +// Read a value from the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \ + __val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset)) + +#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \ + __val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset)) + +#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \ + __val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset)) + +// Write a value to the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ + cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val)) + +#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ + cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val)) + +#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ + cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val)) +#else + +#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) +#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) +#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) +#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) +#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) +#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) +#endif + + +// Default memory mapping details +#ifndef CYGARC_PHYSICAL_ADDRESS +#define CYGARC_PHYSICAL_ADDRESS(x) (x) +#endif + +#ifndef CYGARC_UNCACHED_ADDRESS +#define CYGARC_UNCACHED_ADDRESS(x) \ + ((((cyg_uint32)(x)) < 0x10000000) ? (((cyg_uint32)(x))+0x20000000) : (x)) +#endif + +#ifndef CYGARC_VIRT_TO_BUS +// direct mapped at uncached address +#define CYGARC_VIRT_TO_BUS(x) (((cyg_uint32)(x) & 0xfffffff)) +#endif + +#ifndef CYGARC_BUS_TO_VIRT +// direct mapped +#define CYGARC_BUS_TO_VIRT(x) (x) +#endif + +#define HAL_PCI_ALLOC_BASE_MEMORY 0x48000000 +#define HAL_PCI_ALLOC_BASE_IO 0 + +#define HAL_PCI_PHYSICAL_MEMORY_BASE 0 +#define HAL_PCI_PHYSICAL_IO_BASE 0 + +//----------------------------------------------------------------------------- +// HAL IO macros. + +// Macro used to determine if given address corresponds to PCI IO address +// space. Evaluates to non-zero if address is for PCI IO. +#ifdef CYGPKG_IO_PCI +#define IXDP425_IS_PCI_IO(x) (((cyg_uint32)(x))<0x40000000) +#else +#define IXDP425_IS_PCI_IO(x) 0 +#endif + +//----------------------------------------------------------------------------- +// BYTE Register access. + +#define HAL_READ_UINT8( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + (_value_) = cyg_hal_plf_pci_io_inb((cyg_uint32)(_reg_)); \ + else \ + ((_value_) = *((volatile CYG_BYTE *)(_reg_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + cyg_hal_plf_pci_io_outb((cyg_uint32)(_reg_), _value_); \ + else \ + (*((volatile CYG_BYTE *)(_reg_)) = (_value_)); \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 16 bit access. + +#define HAL_READ_UINT16( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + (_value_) = cyg_hal_plf_pci_io_inw((cyg_uint32)(_reg_)); \ + else \ + ((_value_) = *((volatile CYG_WORD16 *)(_reg_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + cyg_hal_plf_pci_io_outw((cyg_uint32)(_reg_), _value_); \ + else \ + (*((volatile CYG_WORD16 *)(_reg_)) = (_value_)); \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 32 bit access. + +#define HAL_READ_UINT32( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + (_value_) = cyg_hal_plf_pci_io_inl((cyg_uint32)(_reg_)); \ + else \ + ((_value_) = *((volatile CYG_WORD32 *)(_reg_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32( _reg_, _value_ ) \ + CYG_MACRO_START \ + if (IXDP425_IS_PCI_IO(_reg_)) \ + cyg_hal_plf_pci_io_outl((cyg_uint32)(_reg_), _value_); \ + else \ + (*((volatile CYG_WORD32 *)(_reg_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_IO_MACROS_DEFINED + + +#endif // CYGONCE_HAL_ARM_IXP425_VAR_IO_H +// EOF var_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/src/ixp425_diag.c @@ -0,0 +1,435 @@ +/*============================================================================= +// +// ixp425_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors:msalter +// Date: 2002-12-08 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // basic machine info +#include <cyg/hal/hal_intr.h> // interrupt macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_misc.h> // Helper functions + +#if !defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && !defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) +#define IXP425_NUM_UARTS 0 +#elif defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) +#define IXP425_NUM_UARTS 2 +#else +#define IXP425_NUM_UARTS 1 +#endif + +#if IXP425_NUM_UARTS > 0 + +/*---------------------------------------------------------------------------*/ +/* 16550 compatible UARTS */ + +// Define the serial registers. +#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0 +#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define CYG_DEV_IER 0x01 // interrupt enable register, read/write, dlab = 0 +#define CYG_DEV_DLM 0x01 // divisor latch (MS), read/write, dlab = 1 +#define CYG_DEV_IIR 0x02 // interrupt identification register, read, dlab = 0 +#define CYG_DEV_FCR 0x02 // fifo control register, write, dlab = 0 +#define CYG_DEV_LCR 0x03 // line control register, write +#define CYG_DEV_MCR 0x04 // modem control register, write +#define CYG_DEV_LSR 0x05 // line status register, read +#define CYG_DEV_MSR 0x06 // modem status register, read +#define CYG_DEV_SCR 0x07 // scratch pad register + +// Interrupt Enable Register +#define SIO_IER_RCV 0x01 +#define SIO_IER_XMT 0x02 +#define SIO_IER_LS 0x04 +#define SIO_IER_MS 0x08 +#define SIO_IER_UUE 0x40 // UART Unit Enable + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// Modem Control Register +#define SIO_MCR_DTR 0x01 +#define SIO_MCR_RTS 0x02 +#define SIO_MCR_OUT1 0x04 +#define SIO_MCR_OUT2 0x08 +#define SIO_MCR_LOOP 0x10 +#define SIO_MCR_AFE 0x20 + +#define UART1_BASE 0xC8000000 +#define UART2_BASE 0xC8001000 + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint32* base; + cyg_int32 msec_timeout; + int isr_vector; + cyg_int32 baud_rate; +} channel_data_t; + + +//----------------------------------------------------------------------------- +// Based on 14.7456 MHz xtal +static int +set_baud( channel_data_t *chan ) +{ + cyg_uint32* base = chan->base; + cyg_uint16 div = 921600 / chan->baud_rate; + cyg_uint32 lcr; + + HAL_READ_UINT32(base+CYG_DEV_LCR, lcr); + HAL_WRITE_UINT32(base+CYG_DEV_LCR, lcr|SIO_LCR_DLAB); + HAL_WRITE_UINT32(base+CYG_DEV_DLL, div & 0xff); + HAL_WRITE_UINT32(base+CYG_DEV_DLM, (div >> 8) & 0xff); + HAL_WRITE_UINT32(base+CYG_DEV_LCR, lcr); + return 1; +} + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint32* base = ((channel_data_t*)__ch_data)->base; + channel_data_t* chan = (channel_data_t*)__ch_data; + + HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_UUE); + + // 8-1-no parity. + HAL_WRITE_UINT32(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); + chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; + set_baud( chan ); + HAL_WRITE_UINT32(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO + HAL_WRITE_UINT32(base+CYG_DEV_MCR, SIO_MCR_OUT2); // Enable interrupt to core +} + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c) +{ + cyg_uint32* base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 lsr, val; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT32(base+CYG_DEV_LSR, lsr); + } while ((lsr & SIO_LSR_THRE) == 0); + + val = c; + HAL_WRITE_UINT32(base+CYG_DEV_THR, val); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint32* base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 lsr, val; + + HAL_READ_UINT32(base+CYG_DEV_LSR, lsr); + if ((lsr & SIO_LSR_DR) == 0) + return false; + + HAL_READ_UINT32(base+CYG_DEV_RBR, val); + *ch = val; + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static channel_data_t plf_ser_channels[] = { +#if defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && !defined(HAL_PLATFORM_UART2_FIRST) + { (cyg_uint32*)UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1 }, +#endif +#if defined(CYGSEM_HAL_IXP425_PLF_USES_UART2) + { (cyg_uint32*)UART2_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART2 } +#endif +#if defined(CYGSEM_HAL_IXP425_PLF_USES_UART1) && defined(HAL_PLATFORM_UART2_FIRST) + { (cyg_uint32*)UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1 }, +#endif +}; + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_RCV | SIO_IER_UUE); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_WRITE_UINT32(chan->base+CYG_DEV_IER, SIO_IER_UUE); + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + { + cyg_uint32 b; + va_list ap; + + va_start(ap, __func); + b = va_arg(ap, cyg_int32); + va_end(ap); + + if (b < 300 || b > 115200) + ret = -1; + else { + chan->baud_rate = b; + ret = set_baud(chan); + } + break; + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + char c; + cyg_uint8 lsr; + CYGARC_HAL_SAVE_GP(); + + cyg_drv_interrupt_acknowledge(chan->isr_vector); + + *__ctrlc = 0; + HAL_READ_UINT32(chan->base+CYG_DEV_LSR, lsr); + if ( (lsr & SIO_LSR_DR) != 0 ) { + + HAL_READ_UINT32(chan->base+CYG_DEV_RBR, c); + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +void +cyg_hal_ixp425_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + for (i = 0; i < IXP425_NUM_UARTS; i++) { + + // Disable interrupts. + HAL_INTERRUPT_MASK(plf_ser_channels[i].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel(&plf_ser_channels[i]); + + // Setup procs in the vector table + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +// If the platform provides some channels of its own, then this function will be +// provided by that platform. +#if !defined(CYGNUM_HAL_IXP425_PLF_SERIAL_CHANNELS) || !CYGNUM_HAL_IXP425_PLF_SERIAL_CHANNELS +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_ixp425_serial_init(); +} +#endif + +#endif // IXP425_NUM_UARTS > 0 + +/*---------------------------------------------------------------------------*/ + +void +hal_diag_led(int n) +{ +} + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/src/ixp425_misc.c @@ -0,0 +1,409 @@ +//========================================================================== +// +// ixp425_misc.c +// +// HAL misc board support code for Intel IXP425 Network Processor +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-08 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H +#include CYGHWR_MEMORY_LAYOUT_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_stub.h> // Stub macros +#include <cyg/hal/hal_if.h> // calling interface API +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/plf_io.h> +#include <cyg/infra/diag.h> // diag_printf +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +// Most initialization has already been done before we get here. +// All we do here is set up the interrupt environment. +// FIXME: some of the stuff in hal_platform_setup could be moved here. + +externC void plf_hardware_init(void); + +void +hal_hardware_init(void) +{ + hal_xscale_core_init(); + + // all interrupt sources to IRQ and disabled + *IXP425_INTR_SEL = 0; + *IXP425_INTR_EN = 0; + + // Enable caches + HAL_DCACHE_ENABLE(); + HAL_ICACHE_ENABLE(); + + // Let the timer run at a default rate (for delays) + hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD); + + // Set up eCos/ROM interfaces + hal_if_init(); + + // Perform any platform specific initializations + plf_hardware_init(); + +#ifdef CYGPKG_IO_PCI + cyg_hal_plf_pci_init(); +#endif +} + +// ------------------------------------------------------------------------- +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. + +int +hal_IRQ_handler(void) +{ + cyg_uint32 sources; + int index; + + sources = *IXP425_INTR_IRQ_ST; + if (sources) { + HAL_LSBIT_INDEX(index, sources); + return index; + } + + sources = *IXP425_INTR_FIQ_ST; + if (sources) { + HAL_LSBIT_INDEX(index, sources); + return index; + } + + return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen! +} + +void +hal_interrupt_mask(int vector) +{ + if (vector < CYGNUM_HAL_ISR_MIN || CYGNUM_HAL_ISR_MAX < vector) + return; + +#if CYGNUM_HAL_ISR_MAX > CYGNUM_HAL_VAR_ISR_MAX + if (vector > CYGNUM_HAL_VAR_ISR_MAX) { + HAL_PLF_INTERRUPT_MASK(vector); + return; + } +#endif + + *IXP425_INTR_EN &= ~(1 << vector); +} + +void +hal_interrupt_unmask(int vector) +{ + if (vector < CYGNUM_HAL_ISR_MIN || CYGNUM_HAL_ISR_MAX < vector) + return; + +#if CYGNUM_HAL_ISR_MAX > CYGNUM_HAL_VAR_ISR_MAX + if (vector > CYGNUM_HAL_VAR_ISR_MAX) { + HAL_PLF_INTERRUPT_UNMASK(vector); + return; + } +#endif + + *IXP425_INTR_EN |= (1 << vector); +} + +void +hal_interrupt_acknowledge(int vector) +{ + if (vector < CYGNUM_HAL_ISR_MIN || CYGNUM_HAL_ISR_MAX < vector) + return; + +#if CYGNUM_HAL_ISR_MAX > CYGNUM_HAL_VAR_ISR_MAX + if (vector > CYGNUM_HAL_VAR_ISR_MAX) { + HAL_PLF_INTERRUPT_ACKNOWLEDGE(vector); + return; + } +#endif + + if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || + vector == CYGNUM_HAL_INTERRUPT_GPIO1) { + *IXP425_GPISR = 1 << (vector - CYGNUM_HAL_INTERRUPT_GPIO0); + return; + } + + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2 && + vector <= CYGNUM_HAL_INTERRUPT_GPIO12) { + *IXP425_GPISR = 4 << (vector - CYGNUM_HAL_INTERRUPT_GPIO2); + return; + } +} + + +// This function is used to configure the GPIO interrupts (and possibly +// some platform-specific interrupts). All of the GPIO pins can potentially +// generate an interrupt. + +// GPIO interrupts are configured as: +// +// level up interrupt on +// ----- -- ------------ +// 0 0 Falling Edge +// 0 1 Rising Edge +// 0 -1 Either Edge +// 1 0 Low level +// 1 1 High level +// +void +hal_interrupt_configure(int vector, int level, int up) +{ + int shift, ival = 0; + + if (vector < CYGNUM_HAL_ISR_MIN || CYGNUM_HAL_ISR_MAX < vector) + return; + +#if CYGNUM_HAL_ISR_MAX > CYGNUM_HAL_VAR_ISR_MAX + if (vector > CYGNUM_HAL_VAR_ISR_MAX) { + HAL_PLF_INTERRUPT_CONFIGURE(vector, level, up); + return; + } +#endif + + if (level) { + ival = up ? 0 : 1 ; + } else { + if (up == 0) + ival = 3; + else if (up == 1) + ival = 2; + else if (up == -1) + ival = 4; + } + + if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || + vector == CYGNUM_HAL_INTERRUPT_GPIO1) { + vector -= CYGNUM_HAL_INTERRUPT_GPIO0; + shift = vector * 3; + *IXP425_GPIT1R = (*IXP425_GPIT1R & ~(7 << shift)) | (ival << shift); + *IXP425_GPISR |= (1 << vector); + return; + } + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2 && + vector <= CYGNUM_HAL_INTERRUPT_GPIO7) { + vector = vector - CYGNUM_HAL_INTERRUPT_GPIO2 + 2; + shift = vector * 3; + *IXP425_GPIT1R = (*IXP425_GPIT1R & ~(7 << shift)) | (ival << shift); + *IXP425_GPISR |= (1 << vector); + return; + } + if (vector >= CYGNUM_HAL_INTERRUPT_GPIO8 && + vector <= CYGNUM_HAL_INTERRUPT_GPIO12) { + vector -= CYGNUM_HAL_INTERRUPT_GPIO8; + shift = vector * 3; + *IXP425_GPIT2R = (*IXP425_GPIT2R & ~(7 << shift)) | (ival << shift); + *IXP425_GPISR |= (1 << vector); + return; + } +} + + +// Should do something with priority here. +void +hal_interrupt_set_level(int vector, int level) +{ +} + + +/*------------------------------------------------------------------------*/ +// RTC Support + +static cyg_uint32 _period; + +#define CLOCK_MULTIPLIER 66 + +void +hal_clock_initialize(cyg_uint32 period) +{ + cyg_uint32 tmr_period; + + _period = period; + + tmr_period = (period * CLOCK_MULTIPLIER) & OST_TIM_RL_MASK; + + // clear pending interrupt + *IXP425_OST_STS = OST_STS_T0INT; + + // set reload value and enable + *IXP425_OST_TIM0_RL = tmr_period | OST_TIM_RL_ENABLE; +} + + +// Dynamically set the timer interrupt rate. +// Not for eCos application use at all, just special GPROF code in RedBoot. + +void +hal_clock_reinitialize( int *pfreq, /* inout */ + unsigned int *pperiod, /* inout */ + unsigned int old_hz ) /* in */ +{ + unsigned int newp = 0, period, i = 0; + int hz; + int do_set_hw; + +// Arbitrary choice somewhat - so the CPU can make +// progress with the clock set like this, we hope. +#define MIN_TICKS (2000) +#define MAX_TICKS N/A: 32-bit counter + + if ( ! pfreq || ! pperiod ) + return; // we cannot even report a problem! + + hz = *pfreq; + period = *pperiod; + +// Requested HZ: +// 0 => tell me the current value (no change, implemented in caller) +// - 1 => tell me the slowest (no change) +// - 2 => tell me the default (no change, implemented in caller) +// -nnn => tell me what you would choose for nnn (no change) +// MIN_INT => tell me the fastest (no change) +// +// 1 => tell me the slowest (sets the clock) +// MAX_INT => tell me the fastest (sets the clock) + + do_set_hw = (hz > 0); + if ( hz < 0 ) + hz = -hz; + + // Be paranoid about bad args, and very defensive about underflows + if ( 0 < hz && 0 < period && 0 < old_hz ) { + + newp = period * old_hz / (unsigned)hz; + + if ( newp < MIN_TICKS ) { + newp = MIN_TICKS; + // recalculate to get the exact delay for this integral hz + // and hunt hz down to an acceptable value if necessary + i = period * old_hz / newp; + if ( i ) do { + newp = period * old_hz / i; + i--; + } while (newp < MIN_TICKS && i); + } + // So long as period * old_hz fits in 32 bits, there is no need to + // worry about overflow; hz >= 1 in the initial divide. If the + // clock cannot do a whole second (period * old_hz >= 2^32), we + // will get overflow here, and random returned HZ values. + + // Recalculate the actual value installed. + i = period * old_hz / newp; + } + + *pfreq = i; + *pperiod = newp; + + if ( do_set_hw ) { + hal_clock_initialize( newp ); + } +} + +// This routine is called during a clock interrupt. +void +hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + // clear pending interrupt + *IXP425_OST_STS = OST_STS_T0INT; +} + +// Read the current value of the clock, returning the number of hardware +// "ticks" that have occurred (i.e. how far away the current value is from +// the start) +void +hal_clock_read(cyg_uint32 *pvalue) +{ + cyg_uint32 timer_val; + + // Translate timer value back into microseconds + timer_val = *IXP425_OST_TIM0 / CLOCK_MULTIPLIER; + + *pvalue = _period - timer_val; +} + +// Delay for some usecs. +void +hal_delay_us(cyg_int32 delay) +{ +#define _TICKS_PER_USEC CLOCK_MULTIPLIER + cyg_uint32 now, prev, diff, usecs; + cyg_uint32 tmr_period = _period * CLOCK_MULTIPLIER; + + diff = usecs = 0; + prev = *IXP425_OST_TIM0; + + while (delay > usecs) { + now = *IXP425_OST_TIM0; + + if (prev < now) + diff += (prev + (tmr_period - now)); + else + diff += (prev - now); + + prev = now; + + if (diff >= _TICKS_PER_USEC) { + usecs += (diff / _TICKS_PER_USEC); + diff %= _TICKS_PER_USEC; + } + } +} + +/*------------------------------------------------------------------------*/ +// EOF ixp425_misc.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c @@ -0,0 +1,446 @@ +//========================================================================== +// +// ixp425_pci.c +// +// HAL support code for IXP425 PCI +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2002-12-08 +// Purpose: PCI support +// Description: Implementations of HAL PCI interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGPKG_IO_PCI + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // calling interface API +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/io/pci_hw.h> +#include <cyg/io/pci.h> + + +static cyg_uint8 +ixp425_read_config_byte(int offset) +{ + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | PCI_CRP_AD_CBE_READ; + return *IXP425_PCI_CRP_RDATA >> (8*(offset & 3)); +} + +static cyg_uint16 +ixp425_read_config_word(int offset) +{ + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | PCI_CRP_AD_CBE_READ; + return *IXP425_PCI_CRP_RDATA >> (8*(offset & 3)); +} + +static cyg_uint32 +ixp425_read_config_dword(int offset) +{ + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | PCI_CRP_AD_CBE_READ; + return *IXP425_PCI_CRP_RDATA; +} + +void +ixp425_write_config_byte(int offset, cyg_uint8 value) +{ + static const cyg_uint32 _cbe[4] = { + (0xe << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0xd << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0xb << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0x7 << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE + }; + int pos = offset & 3; + + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | _cbe[pos]; + *IXP425_PCI_CRP_WDATA = value << (8 * pos); +} + +void +ixp425_write_config_word(int offset, cyg_uint16 value) +{ + static const cyg_uint32 _cbe[4] = { + (0xc << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0x9 << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0x3 << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE, + (0x7 << PCI_CRP_AD_CBE_BE_SHIFT) | PCI_CRP_AD_CBE_WRITE + }; + int pos = offset & 3; + + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | _cbe[pos]; + *IXP425_PCI_CRP_WDATA = value << (8 * pos); +} + +void +ixp425_write_config_dword(int offset, cyg_uint32 value) +{ + *IXP425_PCI_CRP_AD_CPE = (offset & ~3) | PCI_CRP_AD_CBE_WRITE; + *IXP425_PCI_CRP_WDATA = value; +} + +// Setup address/cbe/cmd for read/write. +// Return CBE register value to use. +// +static cyg_uint32 +pci_config(cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset, cyg_uint32 cmd, int size) +{ + static const cyg_uint8 byte_cbe[4] = { 0xe0, 0xd0, 0xb0, 0x70 }; + static const cyg_uint8 word_cbe[4] = { 0xc0, 0x90, 0x30, 0x70 }; + + if (bus == 0) { + // bus == 0 && devfn == 0 is a special case. Higher level config cycle + // code will not call this routine for bus 0, devfn 0 as that is the + // device address used by the IXP425 PCI device. When commands other + // than config read/write are desired, bus 0, devfn 0 is used to + // indicate that the offset should be used as the address. + if (devfn == 0) { + *IXP425_PCI_NP_AD = offset & ~3; + } else { + // type 0 + // + // Take care with device number as we use device 0 to indicate + // the IXP425 itself. This code makes device 1-21 externally + // addressable. + // + *IXP425_PCI_NP_AD = (0x400 << CYG_PCI_DEV_GET_DEV(devfn)) | + (CYG_PCI_DEV_GET_FN(devfn)<< 8) | (offset & ~3); + } + } else { + // type 1 + *IXP425_PCI_NP_AD = (bus << 16) | (CYG_PCI_DEV_GET_DEV(devfn) << 11) | + (CYG_PCI_DEV_GET_FN(devfn) << 8) | (offset & ~3) | 1; + } + + if (size == 1) + cmd |= byte_cbe[offset & 3]; + else if (size == 2) + cmd |= word_cbe[offset & 3]; + + return cmd; +} + +// check for abort after config access +static int +pci_check_abort(void) +{ + if (*IXP425_PCI_ISR & PCI_ISR_PFE) { + *IXP425_PCI_ISR = PCI_ISR_PFE; + return 1; + } + return 0; +} + +static cyg_uint32 +pci_np_read(cyg_uint32 cmd) +{ + cyg_uint32 data; +#ifdef CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND + // + // PCI NP Bug workaround - only works if NP PCI space reads have + // no side effects! Read 8 times. Last one will be good. + // + int i; + + for (i = 0; i < 8; i++) { + // set up and execute the read + *IXP425_PCI_NP_CBE = cmd; + // the result of the read is now in NP_RDATA (maybe) + data = *IXP425_PCI_NP_RDATA; + // the result of the read is now in NP_RDATA (for sure) + data = *IXP425_PCI_NP_RDATA; + } +#else + // set up and execute the read + *IXP425_PCI_NP_CBE = cmd; + // the result of the read is now in NP_RDATA + data = *IXP425_PCI_NP_RDATA; +#endif + if (pci_check_abort()) + return 0xffffffff; + return data; +} + +static void +pci_np_write(cyg_uint32 cmd, cyg_uint32 data) +{ + // set up the write + *IXP425_PCI_NP_CBE = cmd; + // write the date + *IXP425_PCI_NP_WDATA = data; + + (void)pci_check_abort(); +} + +static cyg_uint8 +bus_read_config_byte(cyg_uint32 bus, cyg_uint32 devfn, int offset) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGR, 1); + + return pci_np_read(cmd) >> ((offset & 3) * 8); +} + +static cyg_uint16 +bus_read_config_word(cyg_uint32 bus, cyg_uint32 devfn, int offset) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGR, 2); + + return pci_np_read(cmd) >> ((offset & 3) * 8); +} + +static cyg_uint32 +bus_read_config_dword(cyg_uint32 bus, cyg_uint32 devfn, int offset) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGR, 4); + + return pci_np_read(cmd); +} + +static void +bus_write_config_byte(cyg_uint32 bus, cyg_uint32 devfn, int offset, cyg_uint8 value) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGW, 1); + + pci_np_write(cmd, value << ((offset & 3) * 8)); +} + +static void +bus_write_config_word(cyg_uint32 bus, cyg_uint32 devfn, int offset, cyg_uint16 value) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGW, 2); + + pci_np_write(cmd, value << ((offset & 3) * 8)); +} + +static void +bus_write_config_dword(cyg_uint32 bus, cyg_uint32 devfn, int offset, cyg_uint32 value) +{ + cyg_uint32 cmd = pci_config(bus, devfn, offset, PCI_NP_CMD_CONFIGW, 4); + + pci_np_write(cmd, value); +} + + +cyg_uint32 +cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, cyg_uint32 devfn, cyg_uint32 offset) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + return bus_read_config_dword(bus, devfn, offset); + + return ixp425_read_config_dword(offset); +} + + +void +cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint32 data) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + bus_write_config_dword(bus, devfn, offset, data); + else + ixp425_write_config_dword(offset, data); +} + + +cyg_uint16 +cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + return bus_read_config_word(bus, devfn, offset); + + return ixp425_read_config_word(offset); +} + +void +cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint16 data) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + bus_write_config_word(bus, devfn, offset, data); + else + ixp425_write_config_word(offset, data); +} + +cyg_uint8 +cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + return bus_read_config_byte(bus, devfn, offset); + + return ixp425_read_config_byte(offset); +} + + +void +cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, + cyg_uint32 devfn, + cyg_uint32 offset, + cyg_uint8 data) +{ + if (bus || CYG_PCI_DEV_GET_DEV(devfn)) + bus_write_config_byte(bus, devfn, offset, data); + else + ixp425_write_config_byte(offset, data); +} + + +void +cyg_hal_plf_pci_io_outb(cyg_uint32 offset, cyg_uint8 value) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOW, 1); + + pci_np_write(cmd, value << ((offset & 3) * 8)); +} + +void +cyg_hal_plf_pci_io_outw(cyg_uint32 offset, cyg_uint16 value) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOW, 2); + + pci_np_write(cmd, value << ((offset & 3) * 8)); +} + +void +cyg_hal_plf_pci_io_outl(cyg_uint32 offset, cyg_uint32 value) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOW, 4); + + pci_np_write(cmd, value); +} + +cyg_uint8 +cyg_hal_plf_pci_io_inb(cyg_uint32 offset) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOR, 1); + + return pci_np_read(cmd) >> ((offset & 3) * 8); +} + +cyg_uint16 +cyg_hal_plf_pci_io_inw(cyg_uint32 offset) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOR, 2); + + return pci_np_read(cmd) >> ((offset & 3) * 8); +} + +cyg_uint32 +cyg_hal_plf_pci_io_inl(cyg_uint32 offset) +{ + cyg_uint32 cmd = pci_config(0, 0, offset, PCI_NP_CMD_IOR, 4); + + return pci_np_read(cmd); +} + + +void +cyg_hal_plf_pci_init(void) +{ + static int inited = 0; + + if (inited) + return; + else + inited = 1; + + // If IC is set, assume warm start + if (*IXP425_PCI_CSR & PCI_CSR_IC) + return; + + // We use identity AHB->PCI address translation + // in the 0x48000000 address space + *IXP425_PCI_PCIMEMBASE = 0x48494A4B; + + // We also use identity PCI->AHB address translation + // in 4 16MB BARs that begin at the physical memory start + *IXP425_PCI_AHBMEMBASE = 0x00010203; + + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_0, 0x00000000); + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_1, 0x01000000); + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_2, 0x02000000); + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_3, 0x03000000); + + cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY); + cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO); + + // This one should never get used, as we request the memory for + // work with PCI with GFP_DMA, which will return mem in the first 64 MB. + // But we still must initialize it so that it wont intersect with first 4 + // BARs + // XXX: Should we initialize the BAR5 to some very large value, so that + // it also will not be hit? + // + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_4, 0x80000000); + HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_5, 0x90000000); + + *IXP425_PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE; + + // + // Set Initialize Complete in PCI Control Register: allow IXP425 to + // respond to PCI configuration cycles. Specify that the AHB bus is + // operating in big endian mode. Set up byte lane swapping between + // little-endian PCI and the big-endian AHB bus + *IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; + + HAL_PCI_CFG_WRITE_UINT16(0, 0, CYG_PCI_CFG_COMMAND, + CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_MEMORY); +} + +#endif // CYGPKG_IO_PCI
--- a/packages/redboot/current/ChangeLog +++ b/packages/redboot/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-18 Mark Salter <msalter@redhat.com> + + * doc/redboot_installing.sgml: Add XScale IXDP425 and GRG. + 2003-03-05 Jonathan Larmour <jifl@eCosCentric.com> * src/main.c (do_version): Test for CYGPKG_REDBOOT_FLASH as
--- a/packages/redboot/current/doc/redboot_installing.sgml +++ b/packages/redboot/current/doc/redboot_installing.sgml @@ -10,7 +10,7 @@ <!-- ####COPYRIGHTBEGIN#### --> <!-- --> <!-- =============================================================== --> -<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. --> +<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. --> <!-- This material may be distributed only subject to the terms --> <!-- and conditions set forth in the Open Publication License, v1.0 --> <!-- or later (the latest version is presently available at --> @@ -2804,7 +2804,7 @@ description of the associated modes.</pa <sect1 id="iq80310"> -<title>ARM/Xscale Cyclone IQ80310</title> +<title>ARM/XScale Cyclone IQ80310</title> <sect2> <title>Overview</title> <para><indexterm><primary>Cyclone IQ80310</primary><secondary>installing and @@ -3145,7 +3145,7 @@ for networking and XModem file transfers <?Pub _newpage> <sect1 id="iq80321"> -<title>ARM/Xscale Intel IQ80321</title> +<title>ARM/XScale Intel IQ80321</title> <sect2> <title>Overview</title> <para><indexterm><primary>Intel IQ80321</primary><secondary>installing and @@ -3627,6 +3627,374 @@ 0xfff00000 - 0xffffffff 0 0 0 Verde Me for networking and XModem file transfers.</para> </sect2></sect1> +<?Pub _newpage> +<sect1 id="IXDP425"> +<title>ARM/Intel XScale IXDP425 Network Processor Evaluation Board</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel IXDP425</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intel IXDP</secondary></indexterm>RedBoot supports +the builtin high-speed and console UARTs and a PCI based i82559 ethernet +card for communication and downloads. The default serial port settings are +115200,8,N,1. RedBoot also supports flash management for the 16MB boot flash +on the mainboard.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from flash + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method</title> +<para>The IXDP425 flash is socketed, so initial installation may be done using +an appropriate device programmer. JTAG based initial may also be used. In either +case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000. +</para> + +<para>After booting the initial installation of RedBoot, this warning may +be printed: <screen>flash configuration checksum error or invalid key +</screen>This is normal, and indicates that the flash should be configured +for use by RedBoot. See <xref linkend="Persistent-State-Flash"> for more +details. +</para></sect2> +<sect2> +<title>LED Codes</title> +<para>RedBoot uses the 4 digit LED display to indicate status during board +initialization. Possible codes are:</para> + +<literallayout width=72> +LED Actions +------------------------------------------------------------- + Power-On/Reset + Set the CPSR + Enable coprocessor access + Drain write and fill buffer + Setup expansion bus chip selects +1001 + Enable Icache +1002 + Initialize SDRAM controller +1003 + Switch flash (CS0) from 0x00000000 to 0x50000000 +1004 + Copy MMU table to RAM +1005 + Setup TTB and domain permissions +1006 + Enable MMU +1007 + Enable DCache +1008 + Enable branch target buffer +1009 + Drain write and fill buffer + Flush caches +100A + Start up the eCos kernel or RedBoot +0001 + +</literallayout> +</sect2> +<sect2> +<title>Rebuilding RedBoot </title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=ixdp425 +export ARCH_DIR=arm +export PLATFORM_DIR=xscale/ixdp425 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> + +<sect2> +<title>Interrupts</title> +<para>RedBoot uses an interrupt vector table which is located at address 0x8004. +Entries in this table are pointers to functions with this protoype:: <programlisting> +int irq_handler( unsigned vector, unsigned data )</programlisting>On the Mainstone +board, the vector argument is one of many interrupts defined in <computeroutput> +hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</computeroutput>: <programlisting> +#define CYGNUM_HAL_INTERRUPT_NPEA 0 +#define CYGNUM_HAL_INTERRUPT_NPEB 1 +#define CYGNUM_HAL_INTERRUPT_NPEC 2 +#define CYGNUM_HAL_INTERRUPT_QM1 3 +#define CYGNUM_HAL_INTERRUPT_QM2 4 +#define CYGNUM_HAL_INTERRUPT_TIMER0 5 +#define CYGNUM_HAL_INTERRUPT_GPIO0 6 +#define CYGNUM_HAL_INTERRUPT_GPIO1 7 +#define CYGNUM_HAL_INTERRUPT_PCI_INT 8 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 +#define CYGNUM_HAL_INTERRUPT_TIMER1 11 +#define CYGNUM_HAL_INTERRUPT_USB 12 +#define CYGNUM_HAL_INTERRUPT_UART2 13 +#define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_WDOG 16 +#define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 +#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 +#define CYGNUM_HAL_INTERRUPT_GPIO2 19 +#define CYGNUM_HAL_INTERRUPT_GPIO3 20 +#define CYGNUM_HAL_INTERRUPT_GPIO4 21 +#define CYGNUM_HAL_INTERRUPT_GPIO5 22 +#define CYGNUM_HAL_INTERRUPT_GPIO6 23 +#define CYGNUM_HAL_INTERRUPT_GPIO7 24 +#define CYGNUM_HAL_INTERRUPT_GPIO8 25 +#define CYGNUM_HAL_INTERRUPT_GPIO9 26 +#define CYGNUM_HAL_INTERRUPT_GPIO10 27 +#define CYGNUM_HAL_INTERRUPT_GPIO11 28 +#define CYGNUM_HAL_INTERRUPT_GPIO12 29 +#define CYGNUM_HAL_INTERRUPT_SW_INT1 30 +#define CYGNUM_HAL_INTERRUPT_SW_INT2 31 +</programlisting> +The data passed to the ISR is pulled from a data table <computeroutput>(hal_interrupt_data) +</computeroutput> which immediately follows the interrupt vector table. With +32 interrupts, the data table starts at address 0x8084. </para> +<para>An application may create a normal C function with the above prototype +to be an ISR. Just poke its address into the table at the correct index and +enable the interrupt at its source. The return value of the ISR is ignored +by RedBoot.</para> +</sect2> +<sect2> +<title>Memory Maps</title> +<para>The RAM based page table is located at RAM start + 0x4000. +<note><title>NOTE</title> +<para>The virtual memory maps in this section use a C, B, and X column to indicate +the caching policy for the region..</para> +</note></para> +<para><programlisting> +X C B Description +- - - --------------------------------------------- +0 0 0 Uncached/Unbuffered +0 0 1 Uncached/Buffered +0 1 0 Cached/Buffered Write Through, Read Allocate +0 1 1 Cached/Buffered Write Back, Read Allocate +1 0 0 Invalid -- not used +1 0 1 Uncached/Buffered No write buffer coalescing +1 1 0 Mini DCache - Policy set by Aux Ctl Register +1 1 1 Cached/Buffered Write Back, Read/Write Allocate + +Virtual Address Physical Address XCB Size (MB) Description +--------------- ---------------- --- --------- ----------- + 0x00000000 0x00000000 010 256 SDRAM (cached) + 0x10000000 0x10000000 010 256 SDRAM (alias) + 0x20000000 0x00000000 000 256 SDRAM (uncached) + 0x48000000 0x48000000 000 64 PCI Data + 0x50000000 0x50000000 010 16 Flash (CS0) + 0x51000000 0x51000000 000 112 CS1 - CS7 + 0x60000000 0x60000000 000 64 Queue Manager + 0xC0000000 0xC0000000 000 1 PCI Controller + 0xC4000000 0xC4000000 000 1 Exp. Bus Config + 0xC8000000 0xC8000000 000 1 Misc IXP425 IO + 0xCC000000 0xCC000000 000 1 SDRAM Config + +</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage</title> +<para>The IXP425 programmable OStimer0 is used for timeout support +for networking and XModem file transfers.</para> +</sect2></sect1> + +<?Pub _newpage> +<sect1 id="GRG"> +<title>ARM/Intel XScale Generic Residential Gateway</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel GRG</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intel GRG</secondary></indexterm>RedBoot supports +the console UART and a PCI based i82559 ethernet card for communication +and downloads. The default serial port settings are 115200,8,N,1. RedBoot +also supports flash management for the 16MB onboard flash.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from flash + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method</title> +<para>The GRG flash is socketed, so initial installation may be done using +an appropriate device programmer. JTAG based initial may also be used. In either +case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000. +</para> + +<para>After booting the initial installation of RedBoot, this warning may +be printed: <screen>flash configuration checksum error or invalid key +</screen>This is normal, and indicates that the flash should be configured +for use by RedBoot. See <xref linkend="Persistent-State-Flash"> for more +details. +</para></sect2> +<sect2> +<title>Rebuilding RedBoot </title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=grg +export ARCH_DIR=arm +export PLATFORM_DIR=xscale/grg +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> + +<sect2> +<title>Interrupts</title> +<para>RedBoot uses an interrupt vector table which is located at address 0x8004. +Entries in this table are pointers to functions with this protoype:: <programlisting> +int irq_handler( unsigned vector, unsigned data )</programlisting>On the Mainstone +board, the vector argument is one of many interrupts defined in <computeroutput> +hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</computeroutput>: <programlisting> +#define CYGNUM_HAL_INTERRUPT_NPEA 0 +#define CYGNUM_HAL_INTERRUPT_NPEB 1 +#define CYGNUM_HAL_INTERRUPT_NPEC 2 +#define CYGNUM_HAL_INTERRUPT_QM1 3 +#define CYGNUM_HAL_INTERRUPT_QM2 4 +#define CYGNUM_HAL_INTERRUPT_TIMER0 5 +#define CYGNUM_HAL_INTERRUPT_GPIO0 6 +#define CYGNUM_HAL_INTERRUPT_GPIO1 7 +#define CYGNUM_HAL_INTERRUPT_PCI_INT 8 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 +#define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 +#define CYGNUM_HAL_INTERRUPT_TIMER1 11 +#define CYGNUM_HAL_INTERRUPT_USB 12 +#define CYGNUM_HAL_INTERRUPT_UART2 13 +#define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_WDOG 16 +#define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 +#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 +#define CYGNUM_HAL_INTERRUPT_GPIO2 19 +#define CYGNUM_HAL_INTERRUPT_GPIO3 20 +#define CYGNUM_HAL_INTERRUPT_GPIO4 21 +#define CYGNUM_HAL_INTERRUPT_GPIO5 22 +#define CYGNUM_HAL_INTERRUPT_GPIO6 23 +#define CYGNUM_HAL_INTERRUPT_GPIO7 24 +#define CYGNUM_HAL_INTERRUPT_GPIO8 25 +#define CYGNUM_HAL_INTERRUPT_GPIO9 26 +#define CYGNUM_HAL_INTERRUPT_GPIO10 27 +#define CYGNUM_HAL_INTERRUPT_GPIO11 28 +#define CYGNUM_HAL_INTERRUPT_GPIO12 29 +#define CYGNUM_HAL_INTERRUPT_SW_INT1 30 +#define CYGNUM_HAL_INTERRUPT_SW_INT2 31 +</programlisting> +The data passed to the ISR is pulled from a data table <computeroutput>(hal_interrupt_data) +</computeroutput> which immediately follows the interrupt vector table. With +32 interrupts, the data table starts at address 0x8084. </para> +<para>An application may create a normal C function with the above prototype +to be an ISR. Just poke its address into the table at the correct index and +enable the interrupt at its source. The return value of the ISR is ignored +by RedBoot.</para> +</sect2> +<sect2> +<title>Memory Maps</title> +<para>The RAM based page table is located at RAM start + 0x4000. +<note><title>NOTE</title> +<para>The virtual memory maps in this section use a C, B, and X column to indicate +the caching policy for the region..</para> +</note></para> +<para><programlisting> +X C B Description +- - - --------------------------------------------- +0 0 0 Uncached/Unbuffered +0 0 1 Uncached/Buffered +0 1 0 Cached/Buffered Write Through, Read Allocate +0 1 1 Cached/Buffered Write Back, Read Allocate +1 0 0 Invalid -- not used +1 0 1 Uncached/Buffered No write buffer coalescing +1 1 0 Mini DCache - Policy set by Aux Ctl Register +1 1 1 Cached/Buffered Write Back, Read/Write Allocate + +Virtual Address Physical Address XCB Size (MB) Description +--------------- ---------------- --- --------- ----------- + 0x00000000 0x00000000 010 32 SDRAM (cached) + 0x10000000 0x00000000 010 32 SDRAM (alias) + 0x20000000 0x00000000 000 32 SDRAM (uncached) + 0x48000000 0x48000000 000 64 PCI Data + 0x50000000 0x50000000 010 16 Flash (CS0) + 0x51000000 0x51000000 000 112 CS1 - CS7 + 0x60000000 0x60000000 000 64 Queue Manager + 0xC0000000 0xC0000000 000 1 PCI Controller + 0xC4000000 0xC4000000 000 1 Exp. Bus Config + 0xC8000000 0xC8000000 000 1 Misc IXP425 IO + 0xCC000000 0xCC000000 000 1 SDRAM Config + +</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage</title> +<para>The IXP425 programmable OStimer0 is used for timeout support +for networking and XModem file transfers.</para> +</sect2></sect1> + + <!-- ********************** CalmRISC ********************** --> <?Pub _newpage> <sect1 id="CalmRISC16">