--- a/packages/hal/arm/xscale/uE250/current/ChangeLog
+++ b/packages/hal/arm/xscale/uE250/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-05-28  Gary Thomas  <gary@mind.be>
+
+	* src/xilinx-load.c: Improve feedback during FPGA downloads.
+
 2003-03-08  Gary Thomas  <gary@mind.be>
 
 	* include/pkgconf/mlt_arm_xscale_uE250_ram.mlt: 

--- a/packages/hal/arm/xscale/uE250/current/include/plf_io.h
+++ b/packages/hal/arm/xscale/uE250/current/include/plf_io.h
@@ -188,7 +188,7 @@ externC void pci_io_write_32(cyg_uint32 
 #define CYG_PCI_MAX_FN 1
 
 
-#define HAL_IDE_NUM_CONTROLLERS 1
+#define HAL_IDE_NUM_CONTROLLERS 1  // Default card has two controllers - maybe should be 2?
 
 #define HAL_IDE_READ_UINT8( __ctlr, __reg, __val) \
     __val = cyg_hal_plf_ide_read_uint8((__ctlr),  (__reg))

--- a/packages/hal/arm/xscale/uE250/current/src/xilinx-load.c
+++ b/packages/hal/arm/xscale/uE250/current/src/xilinx-load.c
@@ -133,6 +133,8 @@ static int
 {
     int err;
     struct _zchar_info *info = (struct _zchar_info *)stream.opaque;
+    static char spin[] = "|/-\\|-";
+    static int tick = 0;
 
     if (info->avail == 0) {
         stream.next_out = info->buf;
@@ -141,7 +143,10 @@ static int
         err = inflate(&stream, Z_SYNC_FLUSH);
         info->avail = (char *)stream.next_out - info->buf;
         if (--info->feedback == 0) {
-            diag_printf(".");
+            diag_printf("%c\b", spin[tick++]);
+            if (tick >= (sizeof(spin)-1)) {
+                tick = 0;
+            }
             info->feedback = FEEDBACK_COUNT;
         }
     }
@@ -216,11 +221,9 @@ bitfile_process_string_tag(char *descrip
 
     len = bitfile_get_len16(_bitfile);
     diag_printf(description);
-    diag_printf(": ");
     for (i = 0; i < len; i++) {
         diag_printf("%c", (*_bitfile)());
     }
-    diag_printf("\n");
 }
 
 /**
@@ -325,7 +328,7 @@ download_bitstream(char *title, _bitfile
 {
     int len, tag;
 
-    diag_printf("Loading %s Bitstream\n", title);
+    diag_printf("Load %s(", title);
 
     len = bitfile_get_len16(_bitfile);
     while (len-- > 0) {
@@ -339,19 +342,19 @@ download_bitstream(char *title, _bitfile
         tag = bitfile_get_tag(_bitfile);
         switch (tag) {
         case 'a':
-            bitfile_process_string_tag("Design name", _bitfile);
+            bitfile_process_string_tag("Design:", _bitfile);
             break;
 
         case 'b':
-            bitfile_process_string_tag("Part name", _bitfile);
+            bitfile_process_string_tag(", Part:", _bitfile);
             break;
 
         case 'c':
-            bitfile_process_string_tag("Date", _bitfile);
+            bitfile_process_string_tag(", Date:", _bitfile);
             break;
 
         case 'd':
-            bitfile_process_string_tag("Time", _bitfile);
+            bitfile_process_string_tag(" ", _bitfile);
             break;
 
         case 'e':
@@ -392,9 +395,9 @@ load_fpga(cyg_uint8 *compressed_bitfile,
     }
     // Set up to download FPGA bitstreap
     *PXA2X0_GPSR0 = FPGA_PROG;
-    download_bitstream("PCI Controller", _zchar, bitfile_process_tag_e);
+    download_bitstream("PCI ctlr", _zchar, bitfile_process_tag_e);
     inflateEnd(&stream);
-    diag_printf(" %x bytes processed\n", zchar_data.total);
+    diag_printf(") %x bytes\n", zchar_data.total);
 }
 
 /**
@@ -421,8 +424,8 @@ load_vga(cyg_uint8 *compressed_bitfile, 
         diag_printf("%s: Can't init stream\n", __FUNCTION__);
         return;
     }
-    download_bitstream("VGA Controller", _zchar, vga_bitfile_process_tag_e);
+    download_bitstream("VGA ctlr", _zchar, vga_bitfile_process_tag_e);
     inflateEnd(&stream);
-    diag_printf(" %x bytes processed\n", zchar_data.total);
+    diag_printf(") %x bytes\n", zchar_data.total);
 }