Mercurial > flash_v2
changeset 1637:eeaba976ebc6
New package for the ARM Industrial Module AIM 711 cloned from
SNDS package.
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new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/ChangeLog @@ -0,0 +1,102 @@ +2004-04-28 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * include/plf_aux.h: + * include/plf_io.h: + Removed plf_aux.h, instead put the prototypes of the functions + in plf_io.h. + +2004-04-28 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * src/aim711_misc.c: + * include/hal_platform_ints.h: + Removed unused RedBoot startup code. + +2004-04-28 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * cdl/hal_arm_aim711.cdl: + * include/hal_platform_ints.h: + Added cdl option to get delays between POST codes. + +2004-04-27 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * cdl/hal_arm_aim711.cdl: Fixed typos. + +2003-10-02 Roland Cassebohm <roland.cassebohm@visionsystems.de> + + * cdl/hal_arm_aim711.cdl: + Implement CYGINT_HAL_ARM_BIGENDIAN. + Use "-mno-short-load-words" in compiler flags to avoid unaligned + access, which would cause exceptions. + + * include/hal_cache.h: + * include/hal_diag.h: + + * include/hal_platform_ints.h: Set HAL_PLATFORM_RESET() to + hal_reset(). + + * include/hal_platform_setup.h: Changed for direct initial + SDRAM setup. External IO is maped to 0x3fd0000. Changed LED macros + to use only the first three bits of PIO. + + * include/plf_io.h: + + * include/plf_stub.h: Remove HAL_STUB_PLATFORM_RESET defines, + because they are not used anymore. + + * include/pkgconf/mlt_arm_aim711_ram.h: Moved FLASH to 0x2000000 + and changed the size to 0x200000. Changed size of RAM to 0x800000. + RedBoot is used as main bootloader. To be sure there is enough + space in future, the RAM version resevers RAM up to 0x30000. + * include/pkgconf/mlt_arm_aim711_ram.ldi: Same. + * include/pkgconf/mlt_arm_aim711_rom.h: Same. + * include/pkgconf/mlt_arm_aim711_rom.ldi: Same. + * include/pkgconf/mlt_arm_aim711_romram.h: Same. + * include/pkgconf/mlt_arm_aim711_romram.ldi: Same. + + * misc/redboot_RAM.ecm: + * misc/redboot_ROM.ecm: + * misc/redboot_ROMRAM.ecm: + + * src/hal_diag.c: Implement hal_diag_led() for the diagnostic board + of the AIM. + + * src/aim711_misc.c: + Implemented reset functionality of the AIM 711 board. + + New package for the ARM Industrial Module AIM 711 cloned from + SNDS package. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/cdl/hal_arm_aim711.cdl @@ -0,0 +1,380 @@ +#========================================================================== +# +# hal_arm_aim711.cdl +# +# +# +#========================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +#========================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Contributors: gthomas, jskov, r.cassebohm +# Grant Edwards <grante@visi.com> +# Date: 2001-07-31 +# Purpose: +# Description: +# +#####DESCRIPTIONEND#### +# +#========================================================================*/ + + +cdl_package CYGPKG_HAL_ARM_AIM711 { + display "ARM Industrial Module AIM 711" + parent CYGPKG_HAL_ARM + define_header hal_arm_aim711.h + include_dir cyg/hal + hardware + description " + The ARM Industrial Module AIM 711 HAL package provides the support + needed to run eCos on a ARM Industrial Module AIM 711 board from + Vision Systems GmbH" + + compile hal_diag.c aim711_misc.c + + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_ARM_ARCH_ARM7 + implements CYGINT_HAL_ARM_THUMB_ARCH + implements CYGINT_HAL_ARM_BIGENDIAN + + requires { CYGHWR_HAL_ARM_BIGENDIAN == 1 } + requires { is_active(CYGPKG_DEVS_ETH_ARM_KS32C5000) implies + CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_RTL8201 } + requires { is_active(CYGPKG_DEVS_ETH_ARM_KS32C5000) implies + (CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR == 2) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_aim711.h>" + puts $::cdl_header "" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM 7TDMI\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"AIM 711\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 140" + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x200000" + puts $::cdl_header "" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMRAM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the AIM 711 board it is possible to build + the system for either RAM, ROM or ROMRAM bootstrap. + RAM bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap typically + requires that the eCos application be blown into the FLASH. + The ROMRAM bootstrap is also stored in FLASH, but will be + executed in RAM." + } + + cdl_component CYG_HAL_CPUTYPE { + display "cpu type" + flavor data + calculated {"S3C4510A"} + no_define + define -file system.h CYG_HAL_CPUTYPE + description "Which version of processor is on board." + } + + cdl_component CYGNUM_HAL_CPUCLOCK { + display "cpu clock" + flavor data + calculated 50000000 + no_define + define -file system.h CYGNUM_HAL_CPUCLOCK + description "Frequency of cpu clock in Hz." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of diag/debug communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description "The AIM 711 board has two diag/debug + serial ports. This option chooses which port will + be used to connect to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The AIM 711 board has two diag/debug serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD { + display "Console/GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + Console/GDB connection." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value (CYGNUM_HAL_CPUCLOCK/CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + + default_value { (CYGHWR_THUMB ? "-mthumb " : "-mcpu=arm7tdmi ") . + (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . + (CYGHWR_HAL_ARM_BIGENDIAN ? "-mbig-endian " : "") . + "-mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "-mcpu=arm7tdmi ") . + (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . + (CYGHWR_HAL_ARM_BIGENDIAN ? "-mbig-endian " : "") . + "-mno-short-load-words -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_aim711_ram" : + (CYG_HAL_STARTUP == "ROMRAM") ? "arm_aim711_romram" : + "arm_aim711_rom" } + + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_aim711_ram.ldi>" : + (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_aim711_romram.ldi>" : + "<pkgconf/mlt_arm_aim711_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_aim711_ram.h>" : + (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_aim711_romram.h>" : + "<pkgconf/mlt_arm_aim711_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_component CYGPKG_REDBOOT_AIM711_EEPROM_RDWR { + display "Provide the eeprom commands in RedBoot" + flavor bool + default_value 1 + parent CYGPKG_REDBOOT_ARM_OPTIONS + #active_if CYGBLD_BUILD_REDBOOT_WITH_EXEC + description " + This option provides the eeprom_read and eeprom_write + commands." + compile -library=libextras.a redboot_eeprom.c + } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_option CYGSEM_HAL_LED_WITH_DELAY { + display "POST LED output with delays" + flavor bool + default_value 0 + description " + Enable this option to have delays between POST codes shown on the + service board LEDs." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/hal_cache.h @@ -0,0 +1,291 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/plf_io.h> + +//----------------------------------------------------------------------------- +// Cache dimensions - one unified cache + +#define HAL_CACHE_UNIFIED + +#define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes +#define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_UCACHE_WAYS 2 // Associativity of the cache + +#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of cache + +// Enable the cache +#define HAL_UCACHE_ENABLE() \ + CYG_MACRO_START \ + cyg_uint32 syscfg; \ + HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \ + syscfg |= KS32C_SYSCFG_CE; \ + HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \ + CYG_MACRO_END + +// Disable the cache +#define HAL_UCACHE_DISABLE() \ + CYG_MACRO_START \ + cyg_uint32 syscfg; \ + HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \ + syscfg &= ~KS32C_SYSCFG_CE; \ + HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \ + CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_UCACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + register cyg_uint32* tag = (cyg_uint32*)KS32C_CACHE_TAG_ADDR; \ + register int i; \ + for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \ + *tag++ = 0; \ + *tag++ = 0; \ + *tag++ = 0; \ + *tag++ = 0; \ + } \ + CYG_MACRO_END + +// Synchronize the contents of the cache with memory. +// No action necessary. Cache is write-through. +#define HAL_UCACHE_SYNC() + +// Query the state of the cache +#define HAL_UCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + cyg_uint32 syscfg; \ + HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \ + (_state_) = (syscfg & KS32C_SYSCFG_CE) ? 1 : 0; \ + CYG_MACRO_END + +// Purge contents of cache +#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Set the cache refill burst size +//#define HAL_UCACHE_BURST_SIZE(_size_) + +// Set the cache write mode +//#define HAL_UCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_UCACHE_WRITETHRU_MODE 0 +//#define HAL_UCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the cache +// and then lock the cache so that it stays there. +//#define HAL_UCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_UCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_UCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_UCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_UCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_UCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Data and instruction cache macros map onto the both-cache macros + +//----------------------------------------------------------------------------- +// Global control of data cache + +#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE +#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS +#define HAL_DCACHE_SETS HAL_UCACHE_SETS + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE +#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS +#define HAL_ICACHE_SETS HAL_UCACHE_SETS + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. + +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/hal_diag.h @@ -0,0 +1,87 @@ +//========================================================================== +// +// hal_diag.h +// +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Grant Edwards <grante@visi.com> +// Date: 2001-07-31 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +//// Not the best place for this, but ... +extern void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(n) hal_delay_us(n); + +#else // old way of doing diagnostic I/O + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +#define HAL_DIAG_INIT() hal_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +// LED only three bit +externC void hal_diag_led(int mask); + +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/hal_platform_ints.h @@ -0,0 +1,108 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Grant Edwards <grante@visi.com> +// Date: 2001-07-31 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#define CYGNUM_HAL_INTERRUPT_EXT0 0 +#define CYGNUM_HAL_INTERRUPT_EXT1 1 +#define CYGNUM_HAL_INTERRUPT_EXT2 2 +#define CYGNUM_HAL_INTERRUPT_EXT3 3 +#define CYGNUM_HAL_INTERRUPT_UART0_TX 4 +#define CYGNUM_HAL_INTERRUPT_UART0_RX 5 +#if !defined(CYG_HAL_CPUTYPE) +#error CYG_HAL_CPUTYPE not defined +#endif +#if defined(CYG_HAL_CPUTYPE_KS32C5000A) +#define CYGNUM_HAL_INTERRUPT_UART0_ERR 6 +#define CYGNUM_HAL_INTERRUPT_UART1_TX 7 +#define CYGNUM_HAL_INTERRUPT_UART1_RX 8 +#define CYGNUM_HAL_INTERRUPT_UART1_ERR 9 +#define CYGNUM_HAL_INTERRUPT_DMA0 10 +#define CYGNUM_HAL_INTERRUPT_DMA1 11 +#define CYGNUM_HAL_INTERRUPT_TIMER0 12 +#define CYGNUM_HAL_INTERRUPT_TIMER1 13 +#define CYGNUM_HAL_INTERRUPT_HDLCA 14 +#define CYGNUM_HAL_INTERRUPT_HDLCB 15 +#else +#define CYGNUM_HAL_INTERRUPT_UART1_TX 6 +#define CYGNUM_HAL_INTERRUPT_UART1_RX 7 +#define CYGNUM_HAL_INTERRUPT_DMA0 8 +#define CYGNUM_HAL_INTERRUPT_DMA1 9 +#define CYGNUM_HAL_INTERRUPT_TIMER0 10 +#define CYGNUM_HAL_INTERRUPT_TIMER1 11 +#define CYGNUM_HAL_INTERRUPT_HDLCA_TX 12 +#define CYGNUM_HAL_INTERRUPT_HDLCA_RX 13 +#define CYGNUM_HAL_INTERRUPT_HDLCB_TX 14 +#define CYGNUM_HAL_INTERRUPT_HDLCB_RX 15 +#endif +#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_TX 16 +#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_RX 17 +#define CYGNUM_HAL_INTERRUPT_ETH_MAC_TX 18 +#define CYGNUM_HAL_INTERRUPT_ETH_MAC_RX 19 +#define CYGNUM_HAL_INTERRUPT_I2C 20 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 20 +#define CYGNUM_HAL_ISR_COUNT 21 + +// The vector used by the Real time clock + +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 + +//---------------------------------------------------------------------------- +// Reset. +externC void hal_reset(void); +#define HAL_PLATFORM_RESET() hal_reset() +#define HAL_PLATFORM_RESET_ENTRY 0x2000000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/hal_platform_setup.h @@ -0,0 +1,261 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H +//========================================================================== +// +// hal_platform_setup.h +// +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, rcassebohm +// Grant Edwards <grante@visi.com> +// Date: 2001-07-31 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/hal/plf_io.h> + + .macro LED_MACRO x + + ldr r0,=KS32C_IOPDATA + ldr r1,[r0] + and r1,r1,#(~0x7) + orr r1,r1,#((0x7 & (~(\x)))) + str r1,[r0] +#ifdef CYGSEM_HAL_LED_WITH_DELAY + ldr r1,=0x80000 +1: sub r1,r1,#1 + cmp r1,#0 + bne 1b +#endif + .endm + +#define CYGHWR_LED_MACRO \ + LED_MACRO (\x) + + +// Use relative branch since we are going to switch the address space +// around. +#define CYGSEM_HAL_ROM_RESET_USES_JUMP + + .macro PLATFORM_RELOCATE + + ldr r1,=KS32C_IOPMOD + ldr r2,=0x07 /* set led display to output */ + str r2,[r1] + + LED 0x0 + + /* Check that it worked, otherwise try Sync DRAM setup */ + ldr r1,=0x00000000 + str r1,[r1] + ldr r2,[r1] + cmp r2,r1 + beq 99f + + /* Sync DRAM mode */ + LED 0x1 + + ldr r3, =0xe7ffff90 /* sdram c+wb disabled, regs @ 0x03ff0000 */ + ldr r0, =KS32C_SYSCFG + str r3,[r0] +1: mov r1,pc /* actual address */ + sub r1,r1,#8 /* + 8 */ + ldr r0,=1b /* address off 1: after remap */ + sub r1,r1,r0 + ldr r0,=40f + add r0,r0,r1 + +#ifdef CYG_HAL_STARTUP_ROMRAM + ldr lr,=4f + add lr,lr,r1 + ldr r1,=AIM711_ROM0_LA_START + add lr,lr,r1 +#else + ldr lr,=99f +#endif + + ldmia r0,{r1-r12} + ldr r0,=KS32C_EXTDBWTH + stmia r0,{r1-r12} + mov pc,lr + +#ifdef CYG_HAL_STARTUP_ROMRAM +4: + /* Relocate text segment */ + ldr r2,=__exception_handlers + ldr r3,=AIM711_ROM0_LA_START + cmp r2,r3 + beq 6f + ldr r4,=__rom_data_end +5: + ldr r0,[r3],#4 + str r0,[r2],#4 + cmp r2,r4 + bne 5b +6: + ldr lr,=99f + mov pc,lr + nop + nop + nop +#endif + + /* The below are set with a store-multiple instruction */ + + /* Sync DRAM setup */ + /* Flash is 8 bit, DRAM is 32 bit and EXTIO is 8 bit */ + /* .long KS32C_EXTDBWTH */ +40: .long ( (KS32C_EXTDBWTH_8BIT<<KS32C_EXTDBWTH_DSR0_shift) \ + |(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD0_shift) \ + |(KS32C_EXTDBWTH_8BIT<<KS32C_EXTDBWTH_DSX0_shift) \ + |(KS32C_EXTDBWTH_8BIT<<KS32C_EXTDBWTH_DSX2_shift) ) + /* Flash at 0x02000000-0x02100000, 5 cycles, 7 cycles */ + /* .long KS32C_ROMCON0 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_7C) \ + |((AIM711_ROM0_LA_START >> 16) << KS32C_ROMCON_BASE_shift) \ + |((AIM711_ROM0_LA_END >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_ROMCON1 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_5C) \ + |((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_ROMCON2 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_5C) \ + |((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_ROMCON3 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_5C) \ + |((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_ROMCON4 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_5C) \ + |((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_ROMCON5 */ + .long ( (KS32C_ROMCON_PMC_ROM) \ + |(KS32C_ROMCON_TPA_5C) \ + |(KS32C_ROMCON_TACC_5C) \ + |((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) + /* .long KS32C_DRAMCON0 */ + .long ( (KS32C_DRAMCON_RESERVED) \ + |(KS32C_DRAMCON_CAN_8) \ + |(KS32C_DRAMCON_TRP_4C) \ + |(KS32C_DRAMCON_TRC_2C) \ + |((AIM711_DRAM_LA_START >> 16) << KS32C_DRAMCON_BASE_shift) \ + |((AIM711_DRAM_LA_END >> 16) << KS32C_DRAMCON_NEXT_shift)) + /* .long KS32C_DRAMCON1 */ + .long ( (KS32C_DRAMCON_RESERVED) \ + |(KS32C_DRAMCON_CAN_8) \ + |(KS32C_DRAMCON_TRP_2C) \ + |(KS32C_DRAMCON_TRC_2C) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) + /* .long KS32C_DRAMCON2 */ + .long ( (KS32C_DRAMCON_RESERVED) \ + |(KS32C_DRAMCON_CAN_8) \ + |(KS32C_DRAMCON_TRP_2C) \ + |(KS32C_DRAMCON_TRC_2C) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) + /* .long KS32C_DRAMCON3 */ + .long ( (KS32C_DRAMCON_RESERVED) \ + |(KS32C_DRAMCON_CAN_8) \ + |(KS32C_DRAMCON_TRP_2C) \ + |(KS32C_DRAMCON_TRC_2C) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \ + |((0x00000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) + /* .long KS32C_REFEXTCON */ + .long (((2048+1-(8*CYGNUM_HAL_CPUCLOCK/1000000)) << KS32C_REFEXTCON_RCV_shift) \ + |(KS32C_REFEXTCON_TRC_4C) \ + |(KS32C_REFEXTCON_REN) \ + |(KS32C_REFEXTCON_VSF) \ + |(AIM711_EXT0_LA_START >> 16) ) +#if 0 +50: + .long 0x07113001 /* ROM half-word, RAM word, EXT-IO */ + .long 0x21080060 /* ROM 32 - 33 MByte */ + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0x0800038e /* RAM 0 - 8 MByte */ + .long 0 + .long 0 + .long 0 + .long 0xc01583fd /* Reactivate external Bus */ +#endif + +99: LED 0x2 + ldr r3,=0x00000000 + str r3,[r3] + ldr r4,[r3] + cmp r4,r3 + beq 15f +11: LED 0x3 + b 11b +15: LED 0x4 + + .endm + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 \ + PLATFORM_RELOCATE +#else +#define PLATFORM_SETUP1 +#endif + +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h +#endif // CYGONCE_HAL_PLATFORM_SETUP_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_ram.h @@ -0,0 +1,15 @@ +// eCos memory layout - Tue Feb 29 14:11:30 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x00800000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x00800000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Tue Feb 29 14:11:30 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x000000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x00040000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x800000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x2000000) +#define CYGMEM_REGION_rom_SIZE (0x200000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_rom.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Wed Apr 11 13:49:55 2001 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x0000000, LENGTH = 0x0800000 + rom : ORIGIN = 0x2000000, LENGTH = 0x0200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x2000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_romram.h @@ -0,0 +1,15 @@ +// eCos memory layout - Tue Feb 29 14:11:30 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x00800000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x00800000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/pkgconf/mlt_arm_aim711_romram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Tue Feb 29 14:11:30 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x000000, LENGTH = 0x00800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x1000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/plf_io.h @@ -0,0 +1,503 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-03-16 +// Purpose: ARM/KS32C platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Platform doesn't need address munging even if configures as big-endian + +#define HAL_IO_MACROS_NO_ADDRESS_MUNGING + +// non-caching by accessing addr|0x04000000 + +#define KS32C_REG_BASE 0x07ff0000 + +// ----------------------------------------------------------------------------- +// System config (register bases and caching) +#define KS32C_SYSCFG (KS32C_REG_BASE + 0x0000) + +#define KS32C_SYSCFG_SDM 0x80000000 +#define KS32C_SYSCFG_PD_ID_MASK 0x3c000000 +#define KS32C_SYSCFG_SRBBP_MASK 0x03ff0000 // address/64k +#define KS32C_SYSCFG_ISBBP_MASK 0x0000ffc0 // a25-a16 +#define KS32C_SYSCFG_CM_MASK 0x00000030 +#define KS32C_SYSCFG_CM_4R_4C 0x00000000 +#define KS32C_SYSCFG_CM_0R_8C 0x00000010 +#define KS32C_SYSCFG_CM_8R_0C 0x00000020 +#define KS32C_SYSCFG_WE 0x00000004 // only KS32C50100? +#define KS32C_SYSCFG_CE 0x00000002 +#define KS32C_SYSCFG_SE 0x00000001 + +#define KS32C_CLKCON (KS32C_REG_BASE + 0x3000) + +#define KS32C_EXTACON0 (KS32C_REG_BASE + 0x3008) +#define KS32C_EXTACON1 (KS32C_REG_BASE + 0x300c) + +#define KS32C_EXTACON0_EXT0_shift 0 +#define KS32C_EXTACON0_EXT1_shift 16 +#define KS32C_EXTACON1_EXT2_shift 0 +#define KS32C_EXTACON1_EXT3_shift 16 + +#define KS32C_EXTACON_TCOS_shift 0 +#define KS32C_EXTACON_TACS_shift 3 +#define KS32C_EXTACON_TCOH_shift 6 +#define KS32C_EXTACON_TACC_shift 9 + +#define KS32C_EXTACON_INIT(_tacs_,_tcos_,_tacc_,_tcoh_) \ + ( ((_tacs_)<<KS32C_EXTACON_TACS_shift) \ + | ((_tcos_)<<KS32C_EXTACON_TCOS_shift) \ + | ((_tacc_)<<KS32C_EXTACON_TACC_shift) \ + | ((_tcoh_)<<KS32C_EXTACON_TCOH_shift) ) + +// Memory banks data width +#define KS32C_EXTDBWTH (KS32C_REG_BASE + 0x3010) + +#define KS32C_EXTDBWTH_MASK 3 +#define KS32C_EXTDBWTH_8BIT 1 +#define KS32C_EXTDBWTH_16BIT 2 +#define KS32C_EXTDBWTH_32BIT 3 + +#define KS32C_EXTDBWTH_DSR0_shift 0 +#define KS32C_EXTDBWTH_DSR1_shift 2 +#define KS32C_EXTDBWTH_DSR2_shift 4 +#define KS32C_EXTDBWTH_DSR3_shift 6 +#define KS32C_EXTDBWTH_DSR4_shift 8 +#define KS32C_EXTDBWTH_DSR5_shift 10 +#define KS32C_EXTDBWTH_DSD0_shift 12 +#define KS32C_EXTDBWTH_DSD1_shift 14 +#define KS32C_EXTDBWTH_DSD2_shift 16 +#define KS32C_EXTDBWTH_DSD3_shift 18 +#define KS32C_EXTDBWTH_DSX0_shift 20 +#define KS32C_EXTDBWTH_DSX1_shift 22 +#define KS32C_EXTDBWTH_DSX2_shift 24 +#define KS32C_EXTDBWTH_DSX3_shift 26 + +// ----------------------------------------------------------------------------- +// Bank locations and timing +#define KS32C_ROMCON0 (KS32C_REG_BASE + 0x3014) +#define KS32C_ROMCON1 (KS32C_REG_BASE + 0x3018) +#define KS32C_ROMCON2 (KS32C_REG_BASE + 0x301c) +#define KS32C_ROMCON3 (KS32C_REG_BASE + 0x3020) +#define KS32C_ROMCON4 (KS32C_REG_BASE + 0x3024) +#define KS32C_ROMCON5 (KS32C_REG_BASE + 0x3028) + +#define KS32C_ROMCON_PMC_MASK 0x00000003 +#define KS32C_ROMCON_PMC_ROM 0x00000000 +#define KS32C_ROMCON_PMC_4W_PAGE 0x00000001 +#define KS32C_ROMCON_PMC_8W_PAGE 0x00000002 +#define KS32C_ROMCON_PMC_16W_PAGE 0x00000003 + +#define KS32C_ROMCON_TPA_MASK 0x0000000c +#define KS32C_ROMCON_TPA_5C 0x00000000 +#define KS32C_ROMCON_TPA_2C 0x00000004 +#define KS32C_ROMCON_TPA_3C 0x00000008 +#define KS32C_ROMCON_TPA_4C 0x0000000c + +#define KS32C_ROMCON_TACC_MASK 0x00000070 +#define KS32C_ROMCON_TACC_DISABLE 0x00000000 +#define KS32C_ROMCON_TACC_2C 0x00000010 +#define KS32C_ROMCON_TACC_3C 0x00000020 +#define KS32C_ROMCON_TACC_4C 0x00000030 +#define KS32C_ROMCON_TACC_5C 0x00000040 +#define KS32C_ROMCON_TACC_6C 0x00000050 +#define KS32C_ROMCON_TACC_7C 0x00000060 + +#define KS32C_ROMCON_BASE_MASK 0x000ffc00 +#define KS32C_ROMCON_BASE_shift 10 + +#define KS32C_ROMCON_NEXT_MASK 0x3ff00000 +#define KS32C_ROMCON_NEXT_shift 20 + + + +#define KS32C_DRAMCON0 (KS32C_REG_BASE + 0x302c) +#define KS32C_DRAMCON1 (KS32C_REG_BASE + 0x3030) +#define KS32C_DRAMCON2 (KS32C_REG_BASE + 0x3034) +#define KS32C_DRAMCON3 (KS32C_REG_BASE + 0x3038) + +#define KS32C_DRAMCON_CAN_8 0x00000000 +#define KS32C_DRAMCON_CAN_9 0x40000000 +#define KS32C_DRAMCON_CAN_10 0x80000000 +#define KS32C_DRAMCON_CAN_11 0xc0000000 +#define KS32C_DRAMCON_TRP_1C 0x00000000 +#define KS32C_DRAMCON_TRP_2C 0x00000100 +#define KS32C_DRAMCON_TRP_3C 0x00000200 +#define KS32C_DRAMCON_TRP_4C 0x00000300 +#define KS32C_DRAMCON_TRC_1C 0x00000000 +#define KS32C_DRAMCON_TRC_2C 0x00000080 +#define KS32C_DRAMCON_RESERVED 0x00000010 +#define KS32C_DRAMCON_TCP_1C 0x00000000 +#define KS32C_DRAMCON_TCP_2C 0x00000008 +#define KS32C_DRAMCON_TCS_1C 0x00000000 +#define KS32C_DRAMCON_TCS_2C 0x00000002 +#define KS32C_DRAMCON_TCS_3C 0x00000004 +#define KS32C_DRAMCON_TCS_4C 0x00000006 +#define KS32C_DRAMCON_EDO 0x00000001 + +#define KS32C_DRAMCON_BASE_MASK 0x000ffc00 +#define KS32C_DRAMCON_BASE_shift 10 + +#define KS32C_DRAMCON_NEXT_MASK 0x3ff00000 +#define KS32C_DRAMCON_NEXT_shift 20 + + +#define KS32C_REFEXTCON (KS32C_REG_BASE + 0x303c) + +// DRAM +#define KS32C_REFEXTCON_TCSR_1C 0x00000000 +#define KS32C_REFEXTCON_TCHR_1C 0x00000000 +// SDRAM +#define KS32C_REFEXTCON_TRC_4C 0x00060000 +// DRAM+SDRAM +#define KS32C_REFEXTCON_REN 0x00010000 +#define KS32C_REFEXTCON_VSF 0x00008000 +#define KS32C_REFEXTCON_BASE 0x00000360 + +#define KS32C_REFEXTCON_RCV_shift 21 + +//----------------------------------------------------------------------------- +// INTC + +#define KS32C_INTMOD (KS32C_REG_BASE + 0x4000) +#define KS32C_INTPND (KS32C_REG_BASE + 0x4004) +#define KS32C_INTMSK (KS32C_REG_BASE + 0x4008) +#define KS32C_INTPRI0 (KS32C_REG_BASE + 0x400c) +#define KS32C_INTPRI1 (KS32C_REG_BASE + 0x4010) +#define KS32C_INTPRI2 (KS32C_REG_BASE + 0x4014) +#define KS32C_INTPRI3 (KS32C_REG_BASE + 0x4018) +#define KS32C_INTPRI4 (KS32C_REG_BASE + 0x401c) +#define KS32C_INTPRI5 (KS32C_REG_BASE + 0x4020) +#define KS32C_INTOFFSET (KS32C_REG_BASE + 0x4024) +#define KS32C_PNDPRI (KS32C_REG_BASE + 0x4028) +#define KS32C_PNDTEST (KS32C_REG_BASE + 0x402c) +#define KS32C_INTOFFSET_FIQ (KS32C_REG_BASE + 0x4030) +#define KS32C_INTOFFSET_IRQ (KS32C_REG_BASE + 0x4034) + +#define KS32C_INTMSK_GLOBAL (1<<21) + +//----------------------------------------------------------------------------- +// PIO + +#define KS32C_IOPMOD (KS32C_REG_BASE + 0x5000) +#define KS32C_IOPCON (KS32C_REG_BASE + 0x5004) + +#define KS32C_IOPCON_XIRQ_MASK 0x1f +#define KS32C_IOPCON_XIRQ_LEVEL 0x00 +#define KS32C_IOPCON_XIRQ_RISING 0x01 +#define KS32C_IOPCON_XIRQ_FALLING 0x02 +#define KS32C_IOPCON_XIRQ_BOTH_EDGE 0x03 +#define KS32C_IOPCON_XIRQ_FILTERING 0x04 +#define KS32C_IOPCON_XIRQ_AKTIV_LOW 0x00 +#define KS32C_IOPCON_XIRQ_AKTIV_HI 0x08 +#define KS32C_IOPCON_XIRQ_ENABLE 0x10 + +#define KS32C_IOPCON_XIRQ0_shift 0 +#define KS32C_IOPCON_XIRQ1_shift 5 +#define KS32C_IOPCON_XIRQ2_shift 10 +#define KS32C_IOPCON_XIRQ3_shift 15 + +#define KS32C_IOPCON_DRQ_MASK 0x07 +#define KS32C_IOPCON_DRQ_AKTIV_LOW 0x00 +#define KS32C_IOPCON_DRQ_AKTIV_HI 0x01 +#define KS32C_IOPCON_DRQ_FILTERING 0x02 +#define KS32C_IOPCON_DRQ_ENABLE 0x04 + +#define KS32C_IOPCON_DRQ0_shift 20 +#define KS32C_IOPCON_DRQ1_shift 23 + +#define KS32C_IOPCON_DAK_MASK 0x03 +#define KS32C_IOPCON_DAK_AKTIV_LOW 0x00 +#define KS32C_IOPCON_DAK_AKTIV_HI 0x01 +#define KS32C_IOPCON_DAK_ENABLE 0x02 + +#define KS32C_IOPCON_DAK0_shift 26 +#define KS32C_IOPCON_DAK1_shift 28 + +#define KS32C_IOPCON_TOEN_ENABLE 0x01 + +#define KS32C_IOPCON_TO0_shift 30 +#define KS32C_IOPCON_TO1_shift 31 + +#define KS32C_IOPDATA (KS32C_REG_BASE + 0x5008) + +#define KS32C_IOPDATA_P0 (1<<0) +#define KS32C_IOPDATA_P1 (1<<1) +#define KS32C_IOPDATA_P2 (1<<2) +#define KS32C_IOPDATA_P3 (1<<3) +#define KS32C_IOPDATA_P4 (1<<4) +#define KS32C_IOPDATA_P5 (1<<5) +#define KS32C_IOPDATA_P6 (1<<6) +#define KS32C_IOPDATA_P7 (1<<7) +#define KS32C_IOPDATA_P8_XIRQ0 (1<<8) +#define KS32C_IOPDATA_P9_XIRQ1 (1<<9) +#define KS32C_IOPDATA_P10_XIRQ2 (1<<10) +#define KS32C_IOPDATA_P11_XIRQ3 (1<<11) +#define KS32C_IOPDATA_P12_DRQ0 (1<<12) +#define KS32C_IOPDATA_P13_DRQ1 (1<<13) +#define KS32C_IOPDATA_P14_DAK0 (1<<14) +#define KS32C_IOPDATA_P15_DAK1 (1<<15) +#define KS32C_IOPDATA_P16_TO0 (1<<16) +#define KS32C_IOPDATA_P17_TO1 (1<<17) + +//----------------------------------------------------------------------------- +// Timers + +#define KS32C_TMOD (KS32C_REG_BASE + 0x6000) +#define KS32C_TDATA0 (KS32C_REG_BASE + 0x6004) +#define KS32C_TDATA1 (KS32C_REG_BASE + 0x6008) +#define KS32C_TCNT0 (KS32C_REG_BASE + 0x600c) +#define KS32C_TCNT1 (KS32C_REG_BASE + 0x6010) + +#define KS32C_TMOD_TE0 0x00000001 +#define KS32C_TMOD_TMD0 0x00000002 +#define KS32C_TMOD_TCLR0 0x00000004 +#define KS32C_TMOD_TE1 0x00000008 +#define KS32C_TMOD_TMD1 0x00000010 +#define KS32C_TMOD_TCLR1 0x00000020 + + +//----------------------------------------------------------------------------- +// UART + +#define KS32C_UART0_BASE (KS32C_REG_BASE + 0xd000) +#define KS32C_UART1_BASE (KS32C_REG_BASE + 0xe000) + +#define KS32C_UART_LCON 0x0000 +#define KS32C_UART_CON 0x0004 +#define KS32C_UART_STAT 0x0008 +#define KS32C_UART_TXBUF 0x000c +#define KS32C_UART_RXBUF 0x0010 +#define KS32C_UART_BRDIV 0x0014 +#define KS32C_UART_BRDCNT 0x0018 +#define KS32C_UART_BRDCLK 0x001c + +#define KS32C_UART_LCON_5_DBITS 0x00 +#define KS32C_UART_LCON_6_DBITS 0x01 +#define KS32C_UART_LCON_7_DBITS 0x02 +#define KS32C_UART_LCON_8_DBITS 0x03 +#define KS32C_UART_LCON_1_SBITS 0x00 +#define KS32C_UART_LCON_2_SBITS 0x04 +#define KS32C_UART_LCON_NO_PARITY 0x00 +#define KS32C_UART_LCON_EVEN_PARITY 0x00 +#define KS32C_UART_LCON_ODD_PARITY 0x28 +#define KS32C_UART_LCON_1_PARITY 0x30 +#define KS32C_UART_LCON_0_PARITY 0x38 +#define KS32C_UART_LCON_SCS 0x40 +#define KS32C_UART_LCON_IR 0x80 + +#define KS32C_UART_CON_RXM_MASK 0x03 +#define KS32C_UART_CON_RXM_INT 0x01 +#define KS32C_UART_CON_TXM_MASK 0x0c +#define KS32C_UART_CON_TXM_INT 0x08 +#define KS32C_UART_CON_RX_ERR_INT 0x04 + + +#define KS32C_UART_STAT_DTR 0x10 +#define KS32C_UART_STAT_RDR 0x20 +#define KS32C_UART_STAT_TXE 0x40 // tx empty +#define KS32C_UART_STAT_TC 0x80 // tx complete + +//----------------------------------------------------------------------------- +// Cache +#define KS32C_CACHE_SET0_ADDR 0x10000000 +#define KS32C_CACHE_SET1_ADDR 0x10800000 +#define KS32C_CACHE_TAG_ADDR 0x11000000 + +//----------------------------------------------------------------------------- +// GDMA +#define KS32C_GDMA_CON0 (KS32C_REG_BASE + 0xb000) +#define KS32C_GDMA_SRC0 (KS32C_REG_BASE + 0xb004) +#define KS32C_GDMA_DST0 (KS32C_REG_BASE + 0xb008) +#define KS32C_GDMA_CNT0 (KS32C_REG_BASE + 0xb00c) +#define KS32C_GDMA_CON1 (KS32C_REG_BASE + 0xc000) +#define KS32C_GDMA_SRC1 (KS32C_REG_BASE + 0xc004) +#define KS32C_GDMA_DST1 (KS32C_REG_BASE + 0xc008) +#define KS32C_GDMA_CNT1 (KS32C_REG_BASE + 0xc00c) + +//----------------------------------------------------------------------------- +// I2C +#define KS32C_I2CCON (KS32C_REG_BASE + 0xf000) +#define KS32C_I2C_CON_BF (1<<0) +#define KS32C_I2C_CON_IEN (1<<1) +#define KS32C_I2C_CON_LRB (1<<2) +#define KS32C_I2C_CON_ACK (1<<3) +#define KS32C_I2C_CON_START (1<<4) +#define KS32C_I2C_CON_STOP (2<<4) +#define KS32C_I2C_CON_RESTART (3<<4) +#define KS32C_I2C_CON_BUSY (1<<6) +#define KS32C_I2C_CON_RESET (1<<7) +#define KS32C_I2CBUF (KS32C_REG_BASE +0xf004) +#define KS32C_I2CPS (KS32C_REG_BASE +0xf008) + +#define KS32C_I2C_FREQ(freq) ((CYGNUM_HAL_CPUCLOCK/(freq) - 3)/16) +#define KS32C_I2C_RD (0x01) +#define KS32C_I2C_WR (0x00) + +#ifndef __ASSEMBLER__ +typedef struct hal_ks32c_i2c_msg_s +{ + cyg_uint8 devaddr; + cyg_int8 status; + cyg_uint8* pbuf; + cyg_uint32 bufsize; +} hal_ks32c_i2c_msg_t; + +// Transfer the I2C messages. +externC int +hal_ks32c_i2c_transfer(cyg_uint32 nmsg, hal_ks32c_i2c_msg_t* pmsgs); +#endif + +//----------------------------------------------------------------------------- +// Memory map is 1-1 + +#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_) + +//----------------------------------------------------------------------------- +// AIM 711 specific + +// Mamory maping +#define AIM711_ROM0_LA_START 0x02000000 +#define AIM711_ROM0_LA_END 0x02200000 +#define AIM711_DRAM_LA_START 0x00000000 +#define AIM711_DRAM_LA_END 0x00800000 +#define AIM711_EXT0_LA_START 0x03fd0000 +#define AIM711_EXT0_LA_END 0x03fd4000 +#define AIM711_EXT1_LA_START 0x03fd4000 +#define AIM711_EXT1_LA_END 0x03fd8000 +#define AIM711_EXT2_LA_START 0x03fd8000 +#define AIM711_EXT2_LA_END 0x03fdc000 +#define AIM711_EXT3_LA_START 0x03fdc000 +#define AIM711_EXT3_LA_END 0x03fc0000 + +#define AIM711_COM0_DEBUG_BASE KS32C_UART0_BASE +#define AIM711_COM1_BASE (AIM711_EXT0_LA_START|0x04000000 + 8) +#define AIM711_COM2_BASE KS32C_UART1_BASE +#define AIM711_EXTBUS_BASE (AIM711_EXT2_LA_START|0x04000000) + +// I2C address of RTC (wallclock) +#define AIM711_RTC_ADDR 0xd0 + +// I2C address and size of EEPROM +#define AIM711_EEPROM_ADDR 0xa0 +#define AIM711_EEPROM_SIZE 256 +#define AIM711_EEPROM_PAGESIZE 8 + +// Interrupt vectors with AIM 711 naming +#define AIM711_INTERRUPT_COM1 CYGNUM_HAL_INTERRUPT_EXT0 +#define AIM711_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_EXT1 +#define AIM711_INTERRUPT_IRQ0 CYGNUM_HAL_INTERRUPT_EXT2 +#define AIM711_INTERRUPT_IRQ1 CYGNUM_HAL_INTERRUPT_EXT3 + +// GPIO bits with AIM 711 naming +#define AIM711_GPIO_LED0 KS32C_IOPDATA_P0 +#define AIM711_GPIO_LED1 KS32C_IOPDATA_P1 +#define AIM711_GPIO_LED2 KS32C_IOPDATA_P2 +#define AIM711_GPIO_RESET KS32C_IOPDATA_P3 +#define AIM711_GPIO_POWERLED KS32C_IOPDATA_P4 +#define AIM711_GPIO_UARTIRQ KS32C_IOPDATA_P8_XIRQ0 +#define AIM711_GPIO_RTCIRQ KS32C_IOPDATA_P9_XIRQ1 +#define AIM711_GPIO_DIN0_DRQ0 KS32C_IOPDATA_P12_DRQ0 +#define AIM711_GPIO_DIN1_DRQ1 KS32C_IOPDATA_P13_DRQ1 +#define AIM711_GPIO_DIN2_IRQ0 KS32C_IOPDATA_P10_XIRQ2 +#define AIM711_GPIO_DIN3_IRQ1 KS32C_IOPDATA_P11_XIRQ3 +#define AIM711_GPIO_DOUT0_DAK0 KS32C_IOPDATA_P14_DAK0 +#define AIM711_GPIO_DOUT1_DAK1 KS32C_IOPDATA_P15_DAK1 +#define AIM711_GPIO_DOUT2_TO0 KS32C_IOPDATA_P16_TO0 +#define AIM711_GPIO_DOUT3_TO1 KS32C_IOPDATA_P17_TO1 + +// Macros for usage of GPIO +#define AIM711_GPIO(_which_,_value_) \ +do { \ + cyg_uint32 val; \ + HAL_READ_UINT32(KS32C_IOPDATA, val); \ + val &= ~(_which_); \ + val |= (_which_)&(_value_); \ + HAL_WRITE_UINT32(KS32C_IOPDATA, val); \ +} while (0) + +#define AIM711_GPIO_SET(_x_) \ +do { \ + cyg_uint32 val; \ + HAL_READ_UINT32(KS32C_IOPDATA, val); \ + val |= (_x_); \ + HAL_WRITE_UINT32(KS32C_IOPDATA, val); \ +} while (0) + +#define AIM711_GPIO_CLR(_x_) \ +do { \ + cyg_uint32 val; \ + HAL_READ_UINT32(KS32C_IOPDATA, val); \ + val &= ~(_x_); \ + HAL_WRITE_UINT32(KS32C_IOPDATA, val); \ +} while (0) + +#define AIM711_GPIO_GET(_x_) \ +do { \ + cyg_uint32 _val; \ + HAL_READ_UINT32(KS32C_IOPDATA, _val); \ + (_x_) = _val; \ +} while (0) + +//----------------------------------------------------------------------------- +// AIM 711 specific EEPROM support + +#ifndef __ASSEMBLER__ +externC int +hal_aim711_eeprom_read(cyg_uint8 *buf, int offset, int len); + +externC int +hal_aim711_eeprom_write(cyg_uint8 *buf, int offset, int len); +#endif + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/include/plf_stub.h @@ -0,0 +1,72 @@ +//========================================================================== +// +// plf_stub.h +// +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov +// Grant Edwards <grante@visi.com> +// Date: 2001-07-31 +// Purpose: +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM +#include <cyg/hal/arm_stub.h> // architecture stub support +// Define serial stuff. +externC void cyg_hal_plf_comms_init(void); +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#endif // CYGONCE_HAL_PLF_STUB_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/misc/redboot_ROMRAM.ecm @@ -0,0 +1,146 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware aim711 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AIM711 current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_AIM711 current ; + package -hardware CYGPKG_DEVS_FLASH_SST_39VFXXX current ; + package -hardware CYGPKG_DEVS_ETH_ARM_KS32C5000 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_S3C4510 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510 current ; + package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711_16X5X current ; + package -hardware CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711 current ; + package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_NS_DNS current ; + package CYGPKG_COMPRESS_ZLIB current ; + package CYGPKG_IO_WALLCLOCK current ; +}; + +cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_REDBOOT_HOLDS_ESA { + user_value 1 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + user_value 0 0 +}; + +cdl_option CYGHWR_HAL_ARM_BIGENDIAN { + user_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS { + user_value 1 +}; + +cdl_option CYGPKG_REDBOOT_ANY_CONSOLE { + user_value 0 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00025000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +cdl_component CYGPKG_REDBOOT_DISK { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT { + user_value 10 +}; + +cdl_component CYGPKG_REDBOOT_AIM711_EEPROM_RDWR { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + user_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGNUM_DEVS_FLASH_ARM_AIM711_SIZE { + user_value 2 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/misc/redboot_ROMRAM_visionsystems.ecm @@ -0,0 +1,239 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware aim711 ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AIM711 current ; + package -hardware CYGPKG_DEVS_FLASH_ARM_AIM711 current ; + package -hardware CYGPKG_DEVS_FLASH_SST_39VFXXX current ; + package -hardware CYGPKG_DEVS_ETH_ARM_KS32C5000 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_S3C4510 current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711_S3C4510 current ; + package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ; + package -hardware CYGPKG_IO_SERIAL_ARM_AIM711_16X5X current ; + package -hardware CYGPKG_DEVICES_WALLCLOCK_ARM_AIM711 current ; + package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_NS_DNS current ; + package CYGPKG_COMPRESS_ZLIB current ; + package CYGPKG_IO_WALLCLOCK current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY { + user_value 0 +}; + +cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_DEBUG_LEVEL { + user_value 0 +}; + +cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 { + user_value 0 +}; + +cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_RTL8201 { + user_value 1 +}; + +cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR { + user_value 2 +}; + +cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_REDBOOT_HOLDS_ESA { + user_value 1 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_INIT_WHOLE_TABLE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_RESET { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_VERSION { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DELAY_US { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_CACHE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_DATA { + user_value 1 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS { + user_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + user_value 0 0 +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_option CYGPKG_HAL_BUILD_COMPILER_TESTS { + user_value 0 +}; + +cdl_option CYGHWR_HAL_ARM_BIGENDIAN { + user_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS { + user_value 1 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "VS 1.1.0" +}; + +cdl_option CYGNUM_REDBOOT_CMD_LINE_EDITING { + user_value 16 +}; + +cdl_component CYGDAT_REDBOOT_DEFAULT_IP_ADDR { + user_value 1 192,168,1,254 +}; + +cdl_option CYGSEM_REDBOOT_DEFAULT_NO_BOOTP { + user_value 1 +}; + +cdl_component CYGPKG_REDBOOT_NETWORKING_DNS { + user_value 1 +}; + +cdl_option CYGPKG_REDBOOT_ANY_CONSOLE { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_PLF_STARTUP { + user_value 0 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00025000 +}; + +cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +cdl_component CYGPKG_REDBOOT_DISK { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT { + user_value 10 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + +cdl_component CYGPKG_REDBOOT_AIM711_EEPROM_RDWR { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + user_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGNUM_DEVS_FLASH_ARM_AIM711_SIZE { + user_value 2 +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + user_value 0 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/src/aim711_misc.c @@ -0,0 +1,600 @@ +//========================================================================== +// +// aim711_misc.c +// +// HAL misc board support code for ARM Industrial Module AIM 711 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, r.cassebohm +// Michael Checky <Michael_Checky@ThermoKing.com> +// Grant Edwards <grante@visi.com> +// Date: 2001-07-31 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> // diag_printf() + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_intr.h> // necessary? +#include <cyg/hal/hal_if.h> // calling interface +#include <cyg/hal/hal_misc.h> // helper functions +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/drv_api.h> // HAL ISR support +#endif + +#include <pkgconf/system.h> + +#ifndef MIN +#define MIN(_x_,_y_) ((_x_) < (_y_) ? (_x_) : (_y_)) +#endif +#ifndef MAX +#define MAX(_x_,_y_) ((_x_) > (_y_) ? (_x_) : (_y_)) +#endif + +//====================================================================== +// Use Timer0 for kernel clock + +static cyg_uint32 _period; + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#if 0 // Not supported yet +static cyg_interrupt abort_interrupt; +static cyg_handle_t abort_interrupt_handle; + +// This ISR is called only for the Abort button interrupt +static int +ks32c_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) +{ + cyg_hal_user_break((CYG_ADDRWORD*)regs); + cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT2); + return 0; // No need to run DSR +} +#endif +#endif + +void hal_clock_initialize(cyg_uint32 period) +{ + cyg_uint32 tmod, clkcon; + + // Disable timer 0 + HAL_READ_UINT32(KS32C_TMOD, tmod); + tmod &= ~(KS32C_TMOD_TE0); + HAL_WRITE_UINT32(KS32C_TMOD, 0); + + tmod &= ~(KS32C_TMOD_TMD0 | KS32C_TMOD_TCLR0); + tmod |= KS32C_TMOD_TE0; + + // Set counter + HAL_READ_UINT32(KS32C_CLKCON, clkcon); + period = period/((clkcon & 0xffff) + 1); + HAL_WRITE_UINT32(KS32C_TDATA0, period); + + // And enable timer + HAL_WRITE_UINT32(KS32C_TMOD, tmod); + + _period = period; + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#if 0 // Not supported yet + cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT2, + 99, // Priority + 0, // Data item passed to interrupt handler + ks32c_abort_isr, + 0, + &abort_interrupt_handle, + &abort_interrupt); + cyg_drv_interrupt_attach(abort_interrupt_handle); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT2); +#endif +#endif +} + +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + _period = period; +} + +void hal_clock_read(cyg_uint32 *pvalue) +{ + cyg_uint32 value; + + HAL_READ_UINT32(KS32C_TCNT0, value); + *pvalue = _period - value; +} + +static void +hal_ks32c_i2c_init(void); + +//====================================================================== +// Interrupt controller stuff + +void hal_hardware_init(void) +{ + cyg_uint32 intmask, syscfg, val; + + // Setup external IO timing + // Timing for Ext0 is for external 16550 UART, all other are default values + val = ( KS32C_EXTACON_INIT(1,1,3,0) << KS32C_EXTACON0_EXT0_shift ) \ + | ( KS32C_EXTACON_INIT(1,1,3,1) << KS32C_EXTACON0_EXT1_shift ); + HAL_WRITE_UINT32(KS32C_EXTACON0, val); + val = ( KS32C_EXTACON_INIT(1,1,3,1) << KS32C_EXTACON1_EXT2_shift ) \ + | ( KS32C_EXTACON_INIT(1,1,3,1) << KS32C_EXTACON1_EXT3_shift ); + HAL_WRITE_UINT32(KS32C_EXTACON1, val); + + // Setup GPIO ports + HAL_READ_UINT32(KS32C_IOPMOD, val); + val |= (AIM711_GPIO_DOUT0_DAK0|AIM711_GPIO_DOUT1_DAK1 \ + |AIM711_GPIO_DOUT2_TO0|AIM711_GPIO_DOUT3_TO1 \ + |AIM711_GPIO_POWERLED); + HAL_WRITE_UINT32(KS32C_IOPMOD, val); + + // Make Power LED on + AIM711_GPIO_SET(AIM711_GPIO_POWERLED); + + // Enable XIRQ0 for external 16550 UART + HAL_READ_UINT32(KS32C_IOPCON, val); + val &= ~( KS32C_IOPCON_XIRQ_MASK << KS32C_IOPCON_XIRQ0_shift ); + val |= ( KS32C_IOPCON_XIRQ_LEVEL|KS32C_IOPCON_XIRQ_AKTIV_HI| \ + KS32C_IOPCON_XIRQ_ENABLE ) << KS32C_IOPCON_XIRQ0_shift ; + HAL_WRITE_UINT32(KS32C_IOPCON, val); + + // Set up eCos/ROM interfaces + hal_if_init(); + + // Enable cache + HAL_READ_UINT32(KS32C_SYSCFG, syscfg); + syscfg &= ~KS32C_SYSCFG_CM_MASK; + syscfg |= KS32C_SYSCFG_CM_0R_8C|KS32C_SYSCFG_WE; + HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); + HAL_UCACHE_INVALIDATE_ALL(); + HAL_UCACHE_ENABLE(); + + // Setup I2C bus + hal_ks32c_i2c_init(); + + // Clear global interrupt mask bit + HAL_READ_UINT32(KS32C_INTMSK, intmask); + intmask &= ~KS32C_INTMSK_GLOBAL; + HAL_WRITE_UINT32(KS32C_INTMSK, intmask); +} + +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. + +int hal_IRQ_handler(void) +{ + // Do hardware-level IRQ handling + cyg_uint32 irq_status; + HAL_READ_UINT32(KS32C_INTOFFSET_IRQ, irq_status); + irq_status = irq_status / 4; + if (CYGNUM_HAL_ISR_MAX >= irq_status) + return irq_status; + // It's a bit bogus to test for FIQs after IRQs, but we use the + // latter more, so don't impose the overhead of checking for FIQs + HAL_READ_UINT32(KS32C_INTOFFSET_FIQ, irq_status); + irq_status = irq_status / 4; + if (CYGNUM_HAL_ISR_MAX >= irq_status) + return irq_status; + return CYGNUM_HAL_INTERRUPT_NONE; +} + +// ------------------------------------------------------------------------- +// +// Interrupt control +// + +void hal_interrupt_mask(int vector) +{ + cyg_uint32 mask, old_mask; + HAL_READ_UINT32(KS32C_INTMSK, mask); + old_mask = mask; + mask |= (1<<vector); + HAL_WRITE_UINT32(KS32C_INTMSK, mask); +} + +void hal_interrupt_unmask(int vector) +{ + cyg_uint32 mask, old_mask; + HAL_READ_UINT32(KS32C_INTMSK, mask); + old_mask = mask; + mask &= ~(1<<vector); + HAL_WRITE_UINT32(KS32C_INTMSK, mask); +} + +void hal_interrupt_acknowledge(int vector) +{ + HAL_WRITE_UINT32(KS32C_INTPND, (1<<vector)); +} + +void hal_interrupt_configure(int vector, int level, int up) +{ +} + +void hal_interrupt_set_level(int vector, int level) +{ +} + +void hal_show_IRQ(int vector, int data, int handler) +{ +} + +// ------------------------------------------------------------------------- +// +// Delay for some number of micro-seconds +// +void hal_delay_us(cyg_int32 usecs) +{ + cyg_uint32 count; + cyg_uint32 ticks = ((CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000) * usecs; + cyg_uint32 tmod; + + // Disable timer 1 + HAL_READ_UINT32(KS32C_TMOD, tmod); + tmod &= ~(KS32C_TMOD_TE1); + HAL_WRITE_UINT32(KS32C_TMOD, tmod); + + tmod &= ~(KS32C_TMOD_TMD1 | KS32C_TMOD_TCLR1); + tmod |= KS32C_TMOD_TE1; + + // Clear pending flag + HAL_WRITE_UINT32(KS32C_INTPND, (1 << CYGNUM_HAL_INTERRUPT_TIMER1)); + + // Set counter + HAL_WRITE_UINT32(KS32C_TDATA1, ticks); + + // And enable timer + HAL_WRITE_UINT32(KS32C_TMOD, tmod); + + // Wait for timer to underflow. Can't test the timer completion + // bit without actually enabling the interrupt. So instead watch + // the counter. + ticks /= 2; // wait for this threshold + + // Wait till timer counts below threshold + do { + HAL_READ_UINT32(KS32C_TCNT1, count); + } while (count >= ticks); + // then wait for it to be reloaded + do { + HAL_READ_UINT32(KS32C_TCNT1, count); + } while (count < ticks); + + // Then disable timer 1 again + tmod &= ~KS32C_TMOD_TE1; + HAL_WRITE_UINT32(KS32C_TMOD, tmod); +} + +// ------------------------------------------------------------------------- +// +// To reset the AIM 711, set P3 to low, which is connected to the reset +// logic +// +void hal_reset(void) +{ + cyg_uint32 value; + CYG_INTERRUPT_STATE old; + + CYGACC_CALL_IF_DELAY_US(100000); + + // Set P3 to output + HAL_READ_UINT32(KS32C_IOPMOD, value); + value |= AIM711_GPIO_RESET; + HAL_WRITE_UINT32(KS32C_IOPMOD, value); + + // Set P3 to low + AIM711_GPIO_CLR(AIM711_GPIO_RESET); + + HAL_DISABLE_INTERRUPTS(old); + while (1) + ; +} + +//---------------------------------------------------------------------- +// +// I2C Support +// + +#include <string.h> +#include <cyg/hal/drv_api.h> + +#ifdef CYGPKG_ERROR +#include <errno.h> +#define I2C_STATUS_SUCCESS (ENOERR) +#define I2C_STATUS_MUTEX (-EINTR) +#define I2C_STATUS_BUSY (-EBUSY) +#define I2C_STATUS_ADDR_NAK (-1000) +#define I2C_STATUS_DATA_NAK (-1001) +#else +#define I2C_STATUS_SUCCESS (0) +#define I2C_STATUS_MUTEX (-1) +#define I2C_STATUS_BUSY (-1) +#define I2C_STATUS_ADDR_NAK (-1) +#define I2C_STATUS_DATA_NAK (-1) +#endif + +static cyg_drv_mutex_t i2c_mutex; + +// Initialize the I2C bus controller. +static void +hal_ks32c_i2c_init(void) +{ + cyg_uint32 prescale = KS32C_I2C_FREQ(100000); + + // reset the bus controller + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_RESET); + + // set the bus frequency + HAL_WRITE_UINT32(KS32C_I2CPS, prescale); + + cyg_drv_mutex_init(&i2c_mutex); +} + +#define RETURN(_x_) \ + CYG_MACRO_START \ + diag_printf("%s: line %d error=%d\n",__FUNCTION__,__LINE__,(_x_)); \ + return (_x_); \ + CYG_MACRO_END + +// Transfer the I2C messages. +int +hal_ks32c_i2c_transfer(cyg_uint32 nmsg, hal_ks32c_i2c_msg_t* pmsgs) +{ + cyg_uint32 i2ccon; + + // serialize access to the I2C bus + if (!cyg_drv_mutex_lock(&i2c_mutex)) + { + RETURN(I2C_STATUS_MUTEX); + } + + // is the bus free ? + HAL_READ_UINT32(KS32C_I2CCON, i2ccon); + if (i2ccon & KS32C_I2C_CON_BUSY) + { + cyg_drv_mutex_unlock(&i2c_mutex); + RETURN(I2C_STATUS_BUSY); + } + + // transfer the messages + for (; nmsg > 0; --nmsg, ++pmsgs) + { + // generate the start condition + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_START); + + // send the device address + HAL_WRITE_UINT32(KS32C_I2CBUF, pmsgs->devaddr); + do + { + HAL_READ_UINT32(KS32C_I2CCON, i2ccon); + } while ((i2ccon & KS32C_I2C_CON_BF) == 0); + + // check if the slave ACK'ed the device address + if (i2ccon & KS32C_I2C_CON_LRB) + { + // generate the stop condition + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_STOP); + cyg_drv_mutex_unlock(&i2c_mutex); + RETURN(I2C_STATUS_ADDR_NAK); + } + + // read the message ? + if (pmsgs->devaddr & KS32C_I2C_RD) + { + cyg_uint8* pbuf = pmsgs->pbuf; + cyg_uint32 bufsize = pmsgs->bufsize; + cyg_uint32 i2cbuf; + + // read more than one byte ? + if (--bufsize > 0) + { + // enable ACK + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_ACK); + + while (bufsize-- > 0) + { + do + { + HAL_READ_UINT32(KS32C_I2CCON, i2ccon); + } while ((i2ccon & KS32C_I2C_CON_BF) == 0); + + // read the data byte + HAL_READ_UINT32(KS32C_I2CBUF, i2cbuf); + *pbuf++ = i2cbuf; + } + } + + // disable ACK + HAL_WRITE_UINT32(KS32C_I2CCON, 0); + do + { + HAL_READ_UINT32(KS32C_I2CCON, i2ccon); + } while ((i2ccon & KS32C_I2C_CON_BF) == 0); + + // read the data byte + HAL_READ_UINT32(KS32C_I2CBUF, i2cbuf); + *pbuf++ = i2cbuf; + } + + // write the message + else + { + cyg_uint32 i; + + for (i = 0; i < pmsgs->bufsize; ++i) + { + HAL_WRITE_UINT32(KS32C_I2CBUF, pmsgs->pbuf[i]); + do + { + HAL_READ_UINT32(KS32C_I2CCON, i2ccon); + } while ((i2ccon & KS32C_I2C_CON_BF) == 0); + + // check if the slave ACK'ed the data byte + if (i2ccon & KS32C_I2C_CON_LRB) + { + // generate the stop condition + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_STOP); + cyg_drv_mutex_unlock(&i2c_mutex); + RETURN(I2C_STATUS_DATA_NAK); + } + } + } + + // generate a restart condition ? + if (nmsg > 1) + { + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_RESTART); + } + } + + // generate the stop condition + HAL_WRITE_UINT32(KS32C_I2CCON, KS32C_I2C_CON_STOP); + + cyg_drv_mutex_unlock(&i2c_mutex); + return I2C_STATUS_SUCCESS; +} + +//---------------------------------------------------------------------- +// +// EEPROM Support +// + +int hal_aim711_eeprom_write(cyg_uint8 *buf, int offset, int len) +{ + cyg_uint8 addr_page[1 + AIM711_EEPROM_PAGESIZE]; + cyg_uint8 const* pbufbyte = (cyg_uint8 const*)buf; + hal_ks32c_i2c_msg_t msg; + cyg_uint8 addr; + cyg_uint32 bufsize; + + if (offset > AIM711_EEPROM_SIZE) + RETURN(-1); + + if (len > (AIM711_EEPROM_SIZE - offset)) + len = (AIM711_EEPROM_SIZE - offset); + + addr = offset; + bufsize = len; + + msg.devaddr = AIM711_EEPROM_ADDR | KS32C_I2C_WR; + msg.pbuf = addr_page; + + while (bufsize > 0) + { + cyg_uint32 nbytes; + int status; + + // write at most a page at a time + nbytes = MIN(bufsize, AIM711_EEPROM_PAGESIZE); + + // don't cross a page boundary + if (addr%AIM711_EEPROM_PAGESIZE) + { + nbytes = MIN(nbytes, AIM711_EEPROM_PAGESIZE - addr%AIM711_EEPROM_PAGESIZE); + } + + // build the write message + addr_page[0] = addr; + memcpy(&addr_page[1], pbufbyte, nbytes); + msg.bufsize = nbytes + 1; + addr += nbytes; + pbufbyte += nbytes; + bufsize -= nbytes; + + // transfer the message + status = hal_ks32c_i2c_transfer(1, &msg); + if (status != I2C_STATUS_SUCCESS) + { + RETURN(status); + } + + // delay 10 msec + CYGACC_CALL_IF_DELAY_US(10000); + } + + return len; +} + +int hal_aim711_eeprom_read(cyg_uint8 *buf, int offset, int len) +{ + hal_ks32c_i2c_msg_t msgs[2]; + int status; + cyg_uint8 toffset; + + if (offset > AIM711_EEPROM_SIZE) + RETURN(-1); + + if (len > (AIM711_EEPROM_SIZE - offset)) + len = (AIM711_EEPROM_SIZE - offset); + + toffset = offset; + + // write message to set the address + msgs[0].devaddr = AIM711_EEPROM_ADDR | KS32C_I2C_WR; + msgs[0].pbuf = &toffset; + msgs[0].bufsize = sizeof(toffset); + + // read message + msgs[1].devaddr = AIM711_EEPROM_ADDR | KS32C_I2C_RD; + msgs[1].pbuf = buf; + msgs[1].bufsize = len; + + // transfer the messages + status = hal_ks32c_i2c_transfer(2, msgs); + + if (status < 0) + RETURN(status); + + return len; +} + +//----------------------------------------------------------------------------- +// +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/src/hal_diag.c @@ -0,0 +1,376 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2001-03-16 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/plf_io.h> // SIO registers + +#define SIO_BRDDIV (((CYGNUM_HAL_CPUCLOCK/2/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)<<4)) + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector_rx; + int isr_vector_tx; +} channel_data_t; + +//----------------------------------------------------------------------------- + +char hextab[] = "0123456789ABCDEF"; + +void putc_ser(int c) +{ + cyg_uint8* base = (cyg_uint8*)KS32C_UART1_BASE; + cyg_uint32 status; + do { + HAL_READ_UINT32(base+KS32C_UART_STAT, status); + } while ((status & KS32C_UART_STAT_TXE) == 0); + + HAL_WRITE_UINT32(base+KS32C_UART_TXBUF, c); +} + +void putint(int a) +{ + int i; + putc_ser('0'); + putc_ser('x'); + for (i = 0; i < 8; i++) { + putc_ser(hextab[(a>>(28-(4*i))) & 0x0f]); + } + putc_ser('\r'); + putc_ser('\n'); +} + +void +init_ser(void) +{ + cyg_uint8* base = (cyg_uint8*)KS32C_UART1_BASE; + + // 8-1-no parity. + HAL_WRITE_UINT32(base+KS32C_UART_LCON, + KS32C_UART_LCON_8_DBITS|KS32C_UART_LCON_1_SBITS|KS32C_UART_LCON_NO_PARITY); + + // Mask interrupts. + HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX); + HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX); + + HAL_WRITE_UINT32(base+KS32C_UART_BRDIV, SIO_BRDDIV); +} + +//----------------------------------------------------------------------------- + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + + // 8-1-no parity. + HAL_WRITE_UINT32(base+KS32C_UART_LCON, + KS32C_UART_LCON_8_DBITS|KS32C_UART_LCON_1_SBITS|KS32C_UART_LCON_NO_PARITY); + + HAL_WRITE_UINT32(base+KS32C_UART_BRDIV, SIO_BRDDIV); + + // Mask interrupts + HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx); + HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx); + + // Enable RX and TX + HAL_WRITE_UINT32(base+KS32C_UART_CON, KS32C_UART_CON_RXM_INT|KS32C_UART_CON_TXM_INT); +} + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c) +{ + cyg_uint8* base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 status, ch; + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT32(base+KS32C_UART_STAT, status); + } while ((status & KS32C_UART_STAT_TXE) == 0); + + ch = (cyg_uint32)c; + HAL_WRITE_UINT32(base+KS32C_UART_TXBUF, ch); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8* base = chan->base; + cyg_uint32 stat; + cyg_uint32 c; + + HAL_READ_UINT32(base+KS32C_UART_STAT, stat); + if ((stat & KS32C_UART_STAT_RDR) == 0) + return false; + + HAL_READ_UINT32(base+KS32C_UART_RXBUF, c); + *ch = (cyg_uint8)(c & 0xff); + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx); + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx); + HAL_INTERRUPT_UNMASK(chan->isr_vector_rx); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector_rx); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector_rx; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint32 c; + cyg_uint8 ch; + cyg_uint32 stat; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + HAL_READ_UINT32(chan->base+KS32C_UART_STAT, stat); + if ( (stat & KS32C_UART_STAT_RDR) != 0 ) { + + HAL_READ_UINT32(chan->base+KS32C_UART_RXBUF, c); + ch = (cyg_uint8)(c & 0xff); + if( cyg_hal_is_break( &ch , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx); + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static channel_data_t ks32c_ser_channels[2] = { + { (cyg_uint8*)KS32C_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX, CYGNUM_HAL_INTERRUPT_UART0_TX }, + { (cyg_uint8*)KS32C_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, CYGNUM_HAL_INTERRUPT_UART1_TX } +}; + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channels + cyg_hal_plf_serial_init_channel(&ks32c_ser_channels[0]); + cyg_hal_plf_serial_init_channel(&ks32c_ser_channels[1]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &ks32c_ser_channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Set channel 1 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &ks32c_ser_channels[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// LED +void +hal_diag_led(int mask) +{ + cyg_uint32 l; + + HAL_READ_UINT32(KS32C_IOPDATA, l); + l &= ~(AIM711_GPIO_LED0|AIM711_GPIO_LED1|AIM711_GPIO_LED2); + l |= (~mask & (AIM711_GPIO_LED0|AIM711_GPIO_LED1|AIM711_GPIO_LED2)); + HAL_WRITE_UINT32(KS32C_IOPDATA, l); +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/aim711/current/src/redboot_eeprom.c @@ -0,0 +1,161 @@ +//========================================================================== +// +// redboot_eeprom.c +// +// RedBoot command to read and write eeprom content of the +// ARM Industrial Module AIM 711 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): rcassebohm +// Contributors: rcassebohm +// Date: 2003-11-10 +// Purpose: +// Description: +// +// RedBoot command to read and write eeprom content of the +// ARM Industrial Module AIM 711 +// This code is part of RedBoot (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <redboot.h> + +#include <cyg/hal/hal_io.h> + +// Exported CLI function(s) +static void do_eeprom_read(int argc, char *argv[]); +RedBoot_cmd("eeprom_read", + "Read eeprom content", + "-b <location> -o <eeprom offset> -l <length> [-d dump]", + do_eeprom_read + ); + +static void do_eeprom_write(int argc, char *argv[]); +RedBoot_cmd("eeprom_write", + "Write eeprom content", + "[-b <location>] -o <eeprom offset> [-l <length>]", + do_eeprom_write + ); + +static void +do_eeprom_read(int argc, char *argv[]) +{ + bool base_addr_set, offset_set, length_set, dump; + unsigned long base_addr, offset, length; + struct option_info opts[4]; + cyg_uint8 *buf; + int ret; + + init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, + (void **)&base_addr, (bool *)&base_addr_set, "location"); + init_opts(&opts[1], 'o', true, OPTION_ARG_TYPE_NUM, + (void **)&offset, (bool *)&offset_set, "eeprom offset"); + init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, + (void **)&length, (bool *)&length_set, "length"); + init_opts(&opts[3], 'd', true, OPTION_ARG_TYPE_FLG, + (void **)&dump, 0, "dump data"); + if (!scan_opts(argc, argv, 1, opts, 4, 0, 0, "")) { + return; + } + + if (!base_addr_set || !offset_set || !length_set) + { + diag_printf("usage: eeprom_read -b <location> -o <eeprom offset>" + " -l <length> [-d dump]\n"); + return; + } + + buf = (cyg_uint8 *)base_addr; + ret = hal_aim711_eeprom_read(buf, offset, length); + if (ret < 0) + { + diag_printf("Error while trying to read eeprom content\n"); + return; + } + + diag_printf("Read %d bytes of eeprom content\n", ret); + + if (dump) + diag_dump_buf((void *)buf, ret); +} + +static void +do_eeprom_write(int argc, char *argv[]) +{ + bool base_addr_set, offset_set, length_set; + unsigned long base_addr, offset, length; + struct option_info opts[3]; + cyg_uint8 *buf; + int ret; + + base_addr = load_address; + length = load_address_end - load_address; + + init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, + (void **)&base_addr, (bool *)&base_addr_set, "location"); + init_opts(&opts[1], 'o', true, OPTION_ARG_TYPE_NUM, + (void **)&offset, (bool *)&offset_set, "eeprom offset"); + init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, + (void **)&length, (bool *)&length_set, "length"); + if (!scan_opts(argc, argv, 1, opts, 3, 0, 0, "")) { + return; + } + + if (!offset_set) + { + diag_printf("usage: eeprom_write [-b <location>] -o <eeprom offset>" + " [-l <length>]\n"); + return; + } + + buf = (cyg_uint8 *)base_addr; + ret = hal_aim711_eeprom_write(buf, offset, length); + if (ret < 0) + { + diag_printf("Error while trying to write eeprom content\n"); + return; + } + + diag_printf("Written %d bytes of eeprom content\n", ret); +} + +// EOF redboot_eeprom.c