Mercurial > nand-ecoscentric

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 0:3111d98ba7b3 ecos-v1_1-release

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
parents
children 443894e2e912
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
3
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
5 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
6 // hal_cache.h
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
7 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
8 // HAL cache control API
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
9 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
11 //####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
12 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
13 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
14 // The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
15 // Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
16 // compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
17 // http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
18 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
19 // Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
21 // License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
22 // the License.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
23 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
25 // September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
26 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
27 // The Initial Developer of the Original Code is Cygnus. Portions created
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
29 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
30 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
31 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
32 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
33 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
34 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
35 // Author(s): nickg
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
36 // Contributors: nickg
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
37 // Date: 1998-02-17
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
38 // Purpose: Cache control API
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
39 // Description: The macros defined here provide the HAL APIs for handling
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
40 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
41 // Usage:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
42 // #include <cyg/hal/hal_cache.h>
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
43 // ...
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
44 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
45 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
46 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
47 //
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
48 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
49
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
50 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
51
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
52 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
53 // MIPS simulator
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
54
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
55 #ifdef CYG_HAL_MIPS_SIM
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
56
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
57 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
58 // Cache dimensions
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
59
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
60 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
61 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
62 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
63 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
64
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
65 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
66 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
67 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
68 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
69
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
70 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
71 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
72
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
73 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
74 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
75
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
76 // Enable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
77 #define HAL_DCACHE_ENABLE()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
78
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
79 // Disable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
80 #define HAL_DCACHE_DISABLE()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
81
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
82 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
83 #define HAL_DCACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
84
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
85 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
86 #define HAL_DCACHE_SYNC()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
87
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
88 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
89 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
90
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
91 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
92 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
93
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
94 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
95 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
96
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
97 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
98 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
99 //#define HAL_DCACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
100
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
101 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
102 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
103
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
104 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
105 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
106
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
107 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
108 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
109 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
110
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
111 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
112 // for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
113 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
114
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
115 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
116 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
117
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
118 // Write dirty cache lines to memory for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
119 //#define HAL_DCACHE_STORE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
120
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
121 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
122 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
123 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
124
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
125 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
126 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
127 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
128
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
129 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
130 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
131
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
132 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
133 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
134
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
135 // Enable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
136 #define HAL_ICACHE_ENABLE()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
137
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
138 // Disable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
139 #define HAL_ICACHE_DISABLE()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
140
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
141 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
142 #define HAL_ICACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
143
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
144 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
145 #define HAL_ICACHE_SYNC()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
146
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
147 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
148 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
149
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
150 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
151 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
152 //#define HAL_ICACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
153
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
154 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
155 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
156
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
157 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
158 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
159
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
160 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
161 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
162
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
163 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
164
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
165
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
166 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
167 // Toshiba TX3904
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
168
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
169 #ifdef CYG_HAL_MIPS_TX3904
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
170
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
171 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
172 // Cache dimensions
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
173
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
174 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
175 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
176 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
177 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
178
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
179 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
180 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
181 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
182 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
183
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
184 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
185 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
186
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
187 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
188 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
189
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
190 // Enable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
191 #define HAL_DCACHE_ENABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
192 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
193 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
194 "ori $2,$2,0x0010;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
195 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
196 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
197 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
198 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
199 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
200 \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
201 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
202
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
203 // Disable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
204 #define HAL_DCACHE_DISABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
205 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
206 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
207 "la $3,0xFFFFFFEF;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
208 "and $2,$2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
209 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
210 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
211 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
212 : "$2", "$3" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
213 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
214 \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
215 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
216
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
217 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
218 // We do this by reading a word from each line to invalidate the current
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
219 // cache contents.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
220 #define HAL_DCACHE_INVALIDATE_ALL() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
221 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
222 extern char __ram_data_start; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
223 CYG_WORD *addr = (CYG_WORD *)&__ram_data_start; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
224 CYG_WORD sum = 0; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
225 int i; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
226 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
227 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
228 sum += addr[i]; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
229 } \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
230 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
231
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
232 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
233 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
234
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
235 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
236 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
237
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
238 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
239 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
240
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
241 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
242 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
243
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
244 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
245 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
246 #define HAL_DCACHE_LOCK(_base_, _size_) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
247 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
248 asm volatile ("mfc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
249 "ori $2,$2,0x0100;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
250 "mtc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
251 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
252 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
253 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
254 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
255 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
256
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
257 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
258 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
259 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
260 asm volatile ("mfc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
261 "la $3,0xFFFFFEFF;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
262 "and $2,$2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
263 "mtc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
264 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
265 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
266 : "$2", "$3" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
267 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
268 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
269
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
270 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
271 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
272
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
273 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
274 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
275 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
276
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
277 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
278 // for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
279 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
280
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
281 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
282 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
283 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
285 register CYG_WORD _size_ = (_asize_); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
286 HAL_DCACHE_DISABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
287 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
288 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
289 asm volatile ("cache 17,0(%0)" : : "r"(addr) ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
290 } \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
291 HAL_DCACHE_ENABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
292 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
293
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
294 // Write dirty cache lines to memory for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
295 //#define HAL_DCACHE_STORE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
296
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
297 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
298 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
299 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
300
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
301 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
302 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
303 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
304
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
305 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
306 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
307
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
308 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
309 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
310
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
311 // Enable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
312 #define HAL_ICACHE_ENABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
313 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
314 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
315 "ori $2,$2,0x0020;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
316 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
317 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
318 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
319 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
320 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
321 \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
322 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
323
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
324 // Disable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
325 #define HAL_ICACHE_DISABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
326 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
327 asm volatile ("mfc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
328 "la $3,0xFFFFFFDF;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
329 "and $2,$2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
330 "mtc0 $2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
331 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
332 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
333 : "$2", "$3" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
334 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
335 \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
336 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
337
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
338 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
339 #define HAL_ICACHE_INVALIDATE_ALL() \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
340 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
341 register CYG_ADDRESS addr; \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
342 HAL_ICACHE_DISABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
343 for( addr = 0; addr < HAL_ICACHE_SIZE; addr += HAL_ICACHE_LINE_SIZE ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
344 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
345 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
346 } \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
347 HAL_ICACHE_ENABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
348 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
349
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
350 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
351 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
352
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
353 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
354 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
355
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
356 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
357 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
358 #define HAL_ICACHE_LOCK(_base_, _size_) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
359 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
360 asm volatile ("mfc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
361 "ori $2,$2,0x0200;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
362 "mtc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
363 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
364 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
365 : "$2" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
366 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
367 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
368
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
369 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
370 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
371 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
372 asm volatile ("mfc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
373 "la $3,0xFFFFFDFF;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
374 "and $2,$2,$3;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
375 "mtc0 $2,$7;" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
376 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
377 : \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
378 : "$2", "$3" \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
379 ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
380 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
381
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
382 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
383 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
384
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
385 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
386 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
387 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
388 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
389 register CYG_WORD _size_ = (_asize_); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
390 HAL_ICACHE_DISABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
391 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
392 { \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
393 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
394 } \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
395 HAL_ICACHE_ENABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
396 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
397
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
398 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
399
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
400 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
401 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
402 // End of hal_cache.h