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annotate packages/hal/mn10300/arch/current/include/hal_intr.h @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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1 #ifndef CYGONCE_HAL_HAL_INTR_H
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2 #define CYGONCE_HAL_HAL_INTR_H
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3
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4 //=============================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Define Interrupt support
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // interrupts and the clock.
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41 //
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42 // Usage:
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43 // #include <cyg/hal/hal_intr.h>
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44 // ...
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45 //
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46 //
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47 //####DESCRIPTIONEND####
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48 //
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49 //=============================================================================
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50
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51 #include <cyg/infra/cyg_type.h>
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52
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53 #include <pkgconf/hal.h>
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54
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55 //-----------------------------------------------------------------------------
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56
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57 // The MN10300 has a somewhat complex interrupt structure. Besides the
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58 // reset and NMI vectors there are seven maskable interrupt vectors
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59 // which must point to code in the 64k starting at 0x40000000. There
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60 // are also 25 Interrupt control groups, each of which can have 4
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61 // interrupt lines attached, for a theoretical total of 100 interrupts
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62 // (!). Some of these are dedicated to specific devices, other to
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63 // external pins, and others are not connected to anything, resulting
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64 // in only 45 that can actually be delivered. Each control group may
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65 // be assigned one of seven interrupt levels, and is delivered to the
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66 // corresponding vector. Software can then use a register to determine
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67 // the delivering group and detect from there which interrupt has been
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68 // delivered.
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69 //
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70 // The approach we will adopt at present is for the code attached to
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71 // each vector to save state and jump via a table to a VSR. The
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72 // default VSR will fully decode the delivered interrupt into a table
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73 // of isr/data/object entries. VSR replacement will operate on the
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74 // first level indirection table rather than the hardware
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75 // vectors. This is the fastest mechanism, however it needs 100*3*4 +
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76 // 7*4 = 1228 bytes for the tables.
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77 //
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78
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79 //-----------------------------------------------------------------------------
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80 // Interrupt vectors.
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81
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82 // The level-specific hardware vectors
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83 #define CYG_VECTOR_0 0
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84 #define CYG_VECTOR_1 1
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85 #define CYG_VECTOR_2 2
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86 #define CYG_VECTOR_3 3
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87 #define CYG_VECTOR_4 4
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88 #define CYG_VECTOR_5 5
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89 #define CYG_VECTOR_6 6
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90 #define CYG_VECTOR_NMI 7
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91 #define CYG_VECTOR_TRAP 8
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92
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93 #define CYG_VSR_MIN 0
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94 #define CYG_VSR_MAX 8
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95 #define CYG_VSR_COUNT 9
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96
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97 #define CYG_EXCEPTION_MIN 0
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98 #define CYG_EXCEPTION_MAX 3
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99 #define CYG_EXCEPTION_COUNT 4
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100
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101
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102 #if defined(CYG_HAL_MN10300_MN103000)
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103
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104 // The decoded interrupts
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105
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106 #define CYG_VECTOR_NMIRQ 0
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107 #define CYG_VECTOR_WATCHDOG 1
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108 #define CYG_VECTOR_SYSTEM_ERROR 2
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109 #define CYG_VECTOR_RESERVED_3 3
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110
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111 #define CYG_VECTOR_RESERVED_4 4
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112 #define CYG_VECTOR_RESERVED_5 5
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113 #define CYG_VECTOR_RESERVED_6 6
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114 #define CYG_VECTOR_RESERVED_7 7
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115
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116 #define CYG_VECTOR_TIMER_0 8
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117 #define CYG_VECTOR_TIMER_1 9
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118 #define CYG_VECTOR_TIMER_2 10
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119 #define CYG_VECTOR_TIMER_3 11
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120
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121 #define CYG_VECTOR_TIMER_4 12
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122 #define CYG_VECTOR_TIMER_5 13
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123 #define CYG_VECTOR_TIMER_6 14
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124 #define CYG_VECTOR_TIMER_7 15
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125
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126 #define CYG_VECTOR_TIMER_8 16
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127 #define CYG_VECTOR_TIMER_8_COMPARE_A 17
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128 #define CYG_VECTOR_TIMER_8_COMPARE_B 18
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129 #define CYG_VECTOR_RESERVED_19 19
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130
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131 #define CYG_VECTOR_TIMER_9 20
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132 #define CYG_VECTOR_TIMER_9_COMPARE_A 21
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133 #define CYG_VECTOR_TIMER_9_COMPARE_B 22
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134 #define CYG_VECTOR_RESERVED_23 23
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135
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136 #define CYG_VECTOR_TIMER_10 24
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137 #define CYG_VECTOR_TIMER_10_COMPARE_A 25
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138 #define CYG_VECTOR_TIMER_10_COMPARE_B 26
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139 #define CYG_VECTOR_TIMER_10_COMPARE_C 27
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140
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141 #define CYG_VECTOR_TIMER_11 28
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142 #define CYG_VECTOR_TIMER_11_COMPARE_A 29
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143 #define CYG_VECTOR_TIMER_11_COMPARE_B 30
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144 #define CYG_VECTOR_TIMER_11_COMPARE_C 31
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145
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146 #define CYG_VECTOR_TIMER_12 32
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147 #define CYG_VECTOR_TIMER_12_COMPARE_A 33
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148 #define CYG_VECTOR_TIMER_12_COMPARE_B 34
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149 #define CYG_VECTOR_TIMER_12_COMPARE_C 35
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150
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151 #define CYG_VECTOR_TIMER_11_COMPARE_D 36
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152 #define CYG_VECTOR_TIMER_12_COMPARE_D 37
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153 #define CYG_VECTOR_RESERVED_38 38
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154 #define CYG_VECTOR_RESERVED_39 39
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155
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156 #define CYG_VECTOR_DMA0 40
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157 #define CYG_VECTOR_RESERVED_41 41
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158 #define CYG_VECTOR_RESERVED_42 42
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159 #define CYG_VECTOR_RESERVED_43 43
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160
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161 #define CYG_VECTOR_DMA1 44
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162 #define CYG_VECTOR_RESERVED_45 45
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163 #define CYG_VECTOR_RESERVED_46 46
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164 #define CYG_VECTOR_RESERVED_47 47
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165
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166 #define CYG_VECTOR_DMA2 48
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167 #define CYG_VECTOR_RESERVED_49 49
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168 #define CYG_VECTOR_RESERVED_50 50
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169 #define CYG_VECTOR_RESERVED_51 51
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170
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171 #define CYG_VECTOR_DMA3 52
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172 #define CYG_VECTOR_RESERVED_53 53
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173 #define CYG_VECTOR_RESERVED_54 54
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174 #define CYG_VECTOR_RESERVED_55 55
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175
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176 #define CYG_VECTOR_SERIAL_0_RX 56
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177 #define CYG_VECTOR_SERIAL_0_TX 57
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178 #define CYG_VECTOR_RESERVED_58 58
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179 #define CYG_VECTOR_RESERVED_59 59
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180
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181 #define CYG_VECTOR_SERIAL_1_RX 60
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182 #define CYG_VECTOR_SERIAL_1_TX 61
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183 #define CYG_VECTOR_RESERVED_62 62
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184 #define CYG_VECTOR_RESERVED_63 63
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185
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186 #define CYG_VECTOR_EXTERNAL_0 64
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187 #define CYG_VECTOR_RESERVED_65 65
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188 #define CYG_VECTOR_RESERVED_66 66
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189 #define CYG_VECTOR_RESERVED_67 67
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190
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191 #define CYG_VECTOR_EXTERNAL_1 68
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192 #define CYG_VECTOR_RESERVED_69 69
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193 #define CYG_VECTOR_RESERVED_70 70
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194 #define CYG_VECTOR_RESERVED_71 71
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195
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196 #define CYG_VECTOR_EXTERNAL_2 72
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197 #define CYG_VECTOR_RESERVED_73 73
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198 #define CYG_VECTOR_RESERVED_74 74
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199 #define CYG_VECTOR_RESERVED_75 75
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200
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201 #define CYG_VECTOR_EXTERNAL_3 76
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202 #define CYG_VECTOR_RESERVED_77 77
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203 #define CYG_VECTOR_RESERVED_78 78
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204 #define CYG_VECTOR_RESERVED_79 79
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205
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206 #define CYG_VECTOR_EXTERNAL_4 80
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207 #define CYG_VECTOR_RESERVED_81 81
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208 #define CYG_VECTOR_RESERVED_82 82
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209 #define CYG_VECTOR_RESERVED_83 83
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210
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211 #define CYG_VECTOR_EXTERNAL_5 84
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212 #define CYG_VECTOR_RESERVED_85 85
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213 #define CYG_VECTOR_RESERVED_86 86
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214 #define CYG_VECTOR_RESERVED_87 87
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215
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216 #define CYG_VECTOR_EXTERNAL_6 88
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217 #define CYG_VECTOR_RESERVED_89 89
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218 #define CYG_VECTOR_RESERVED_90 90
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219 #define CYG_VECTOR_RESERVED_91 91
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220
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221 #define CYG_VECTOR_EXTERNAL_7 92
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222 #define CYG_VECTOR_RESERVED_93 93
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223 #define CYG_VECTOR_RESERVED_94 94
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224 #define CYG_VECTOR_RESERVED_95 95
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225
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226 #define CYG_VECTOR_AD_CONVERSION 96
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227 #define CYG_VECTOR_RESERVED_97 97
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228 #define CYG_VECTOR_RESERVED_98 98
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229 #define CYG_VECTOR_RESERVED_99 99
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230
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231 #define CYG_ISR_MIN 0
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232 #define CYG_ISR_MAX 99
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233
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234 #define CYG_ISR_COUNT 100
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235
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236 #elif defined(CYG_HAL_MN10300_MN103002)
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237
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238 // The decoded interrupts
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239
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240 #define CYG_VECTOR_NMIRQ 0
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241 #define CYG_VECTOR_WATCHDOG 1
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242 #define CYG_VECTOR_SYSTEM_ERROR 2
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243 #define CYG_VECTOR_RESERVED_3 3
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244
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245 #define CYG_VECTOR_RESERVED_4 4
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246 #define CYG_VECTOR_RESERVED_5 5
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247 #define CYG_VECTOR_RESERVED_6 6
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248 #define CYG_VECTOR_RESERVED_7 7
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249
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250 #define CYG_VECTOR_TIMER_0 8
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251 #define CYG_VECTOR_RESERVED_9 9
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252 #define CYG_VECTOR_RESERVED_10 10
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253 #define CYG_VECTOR_RESERVED_11 11
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254
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255 #define CYG_VECTOR_TIMER_1 12
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256 #define CYG_VECTOR_RESERVED_13 13
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257 #define CYG_VECTOR_RESERVED_14 14
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258 #define CYG_VECTOR_RESERVED_15 15
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259
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260 #define CYG_VECTOR_TIMER_2 16
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261 #define CYG_VECTOR_RESERVED_17 17
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262 #define CYG_VECTOR_RESERVED_18 18
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263 #define CYG_VECTOR_RESERVED_19 19
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264
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265 #define CYG_VECTOR_TIMER_3 20
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266 #define CYG_VECTOR_RESERVED_21 21
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267 #define CYG_VECTOR_RESERVED_22 22
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268 #define CYG_VECTOR_RESERVED_23 23
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269
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270 #define CYG_VECTOR_TIMER_4 24
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271 #define CYG_VECTOR_RESERVED_25 25
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272 #define CYG_VECTOR_RESERVED_26 26
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273 #define CYG_VECTOR_RESERVED_27 27
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274
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275 #define CYG_VECTOR_TIMER_5 28
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276 #define CYG_VECTOR_RESERVED_29 29
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277 #define CYG_VECTOR_RESERVED_30 30
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278 #define CYG_VECTOR_RESERVED_31 31
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279
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280 #define CYG_VECTOR_TIMER_6 32
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281 #define CYG_VECTOR_RESERVED_33 33
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282 #define CYG_VECTOR_RESERVED_34 34
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283 #define CYG_VECTOR_RESERVED_35 35
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284
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285 #define CYG_VECTOR_TIMER_6_COMPARE_A 36
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286 #define CYG_VECTOR_RESERVED_37 37
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287 #define CYG_VECTOR_RESERVED_38 38
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288 #define CYG_VECTOR_RESERVED_39 39
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289
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290 #define CYG_VECTOR_TIMER_6_COMPARE_B 40
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291 #define CYG_VECTOR_RESERVED_41 41
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292 #define CYG_VECTOR_RESERVED_42 42
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293 #define CYG_VECTOR_RESERVED_43 43
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294
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295 #define CYG_VECTOR_RESERVED_44 44
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296 #define CYG_VECTOR_RESERVED_45 45
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297 #define CYG_VECTOR_RESERVED_46 46
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298 #define CYG_VECTOR_RESERVED_47 47
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299
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300 #define CYG_VECTOR_DMA0 48
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301 #define CYG_VECTOR_RESERVED_49 49
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302 #define CYG_VECTOR_RESERVED_50 50
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303 #define CYG_VECTOR_RESERVED_51 51
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304
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305 #define CYG_VECTOR_DMA1 52
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306 #define CYG_VECTOR_RESERVED_53 53
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307 #define CYG_VECTOR_RESERVED_54 54
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308 #define CYG_VECTOR_RESERVED_55 55
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309
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310 #define CYG_VECTOR_DMA2 56
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311 #define CYG_VECTOR_RESERVED_57 57
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312 #define CYG_VECTOR_RESERVED_58 58
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313 #define CYG_VECTOR_RESERVED_59 59
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314
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315 #define CYG_VECTOR_DMA3 60
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316 #define CYG_VECTOR_RESERVED_61 61
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317 #define CYG_VECTOR_RESERVED_62 62
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318 #define CYG_VECTOR_RESERVED_63 63
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319
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320 #define CYG_VECTOR_SERIAL_0_RX 64
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321 #define CYG_VECTOR_RESERVED_65 65
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322 #define CYG_VECTOR_RESERVED_66 66
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323 #define CYG_VECTOR_RESERVED_67 67
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324
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325 #define CYG_VECTOR_SERIAL_0_TX 68
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326 #define CYG_VECTOR_RESERVED_69 69
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327 #define CYG_VECTOR_RESERVED_70 70
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328 #define CYG_VECTOR_RESERVED_71 71
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329
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330 #define CYG_VECTOR_SERIAL_1_RX 72
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331 #define CYG_VECTOR_RESERVED_73 73
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332 #define CYG_VECTOR_RESERVED_74 74
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333 #define CYG_VECTOR_RESERVED_75 75
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334
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335 #define CYG_VECTOR_SERIAL_1_TX 76
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336 #define CYG_VECTOR_RESERVED_77 77
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337 #define CYG_VECTOR_RESERVED_78 78
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338 #define CYG_VECTOR_RESERVED_79 79
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339
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340 #define CYG_VECTOR_SERIAL_2_RX 80
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341 #define CYG_VECTOR_RESERVED_81 81
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342 #define CYG_VECTOR_RESERVED_82 82
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343 #define CYG_VECTOR_RESERVED_83 83
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344
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345 #define CYG_VECTOR_SERIAL_2_TX 84
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346 #define CYG_VECTOR_RESERVED_85 85
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347 #define CYG_VECTOR_RESERVED_86 86
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348 #define CYG_VECTOR_RESERVED_87 87
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349
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350 #define CYG_VECTOR_RESERVED_88 88
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351 #define CYG_VECTOR_RESERVED_89 89
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352 #define CYG_VECTOR_RESERVED_90 90
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353 #define CYG_VECTOR_RESERVED_91 91
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354
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355 #define CYG_VECTOR_EXTERNAL_0 92
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356 #define CYG_VECTOR_RESERVED_93 93
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357 #define CYG_VECTOR_RESERVED_94 94
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358 #define CYG_VECTOR_RESERVED_95 95
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359
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360 #define CYG_VECTOR_EXTERNAL_1 96
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361 #define CYG_VECTOR_RESERVED_97 97
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362 #define CYG_VECTOR_RESERVED_98 98
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363 #define CYG_VECTOR_RESERVED_99 99
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364
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365 #define CYG_VECTOR_EXTERNAL_2 100
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366 #define CYG_VECTOR_RESERVED_101 101
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367 #define CYG_VECTOR_RESERVED_102 102
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368 #define CYG_VECTOR_RESERVED_103 103
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369
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370 #define CYG_VECTOR_EXTERNAL_3 104
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371 #define CYG_VECTOR_RESERVED_105 105
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372 #define CYG_VECTOR_RESERVED_106 106
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373 #define CYG_VECTOR_RESERVED_107 107
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374
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375 #define CYG_VECTOR_EXTERNAL_4 108
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376 #define CYG_VECTOR_RESERVED_109 109
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377 #define CYG_VECTOR_RESERVED_110 110
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378 #define CYG_VECTOR_RESERVED_111 111
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379
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380 #define CYG_VECTOR_EXTERNAL_5 112
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381 #define CYG_VECTOR_RESERVED_113 113
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382 #define CYG_VECTOR_RESERVED_114 114
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383 #define CYG_VECTOR_RESERVED_115 115
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384
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385 #define CYG_VECTOR_EXTERNAL_6 116
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386 #define CYG_VECTOR_RESERVED_117 117
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387 #define CYG_VECTOR_RESERVED_118 118
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388 #define CYG_VECTOR_RESERVED_119 119
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389
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390 #define CYG_VECTOR_EXTERNAL_7 120
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391 #define CYG_VECTOR_RESERVED_121 121
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392 #define CYG_VECTOR_RESERVED_122 122
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393 #define CYG_VECTOR_RESERVED_123 123
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394
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395 #define CYG_ISR_MIN 0
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396 #define CYG_ISR_MAX 123
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397
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398 #define CYG_ISR_COUNT (3+((CYG_ISR_MAX+1)/4))
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399
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400 #endif
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401
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402 // The vector used by the Real time clock
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403
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404 #ifdef CYG_HAL_MN10300_SIM
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405 # define CYG_VECTOR_RTC CYG_VECTOR_TIMER_5
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406 //# define CYG_VECTOR_RTC CYG_VECTOR_EXTERNAL_1
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407 #else
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408 # ifdef CYG_HAL_MN10300_MN103000
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409 # define CYG_VECTOR_RTC CYG_VECTOR_TIMER_8
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410 # endif
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411 # ifdef CYG_HAL_MN10300_MN103002
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412 # define CYG_VECTOR_RTC CYG_VECTOR_TIMER_5
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413 # endif
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414 #endif
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415
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416 //-----------------------------------------------------------------------------
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417 // Timer control registers.
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418
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419 // On simulator we use simulated external interrupt
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420
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421 #if defined(CYG_HAL_MN10300_MN103002)
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422
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423 // On the mn103002 we use timers 4 and 5
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424
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425 #define TIMER4_CR 0x340010a0
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426 #define TIMER4_BR 0x34001090
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427 #define TIMER4_MD 0x34001080
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428
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429 #define TIMER5_CR 0x340010a2
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430 #define TIMER5_BR 0x34001092
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431 #define TIMER5_MD 0x34001082
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432
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433 #define TIMER_CR TIMER5_CR
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434 #define TIMER_BR TIMER5_BR
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435 #define TIMER_MD TIMER5_MD
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436
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437 #define TIMER0_MD 0x34001000
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438 #define TIMER0_BR 0x34001010
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439 #define TIMER0_CR 0x34001020
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440
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441 #elif defined(CYG_HAL_MN10300_MN103000)
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442
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443 // on the mn103000 we use timers 4 and 5
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444 #define TIMER4_CR 0x340010a0
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445 #define TIMER4_BR 0x34001090
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446 #define TIMER4_MD 0x34001080
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447
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448 #define TIMER5_CR 0x340010a2
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449 #define TIMER5_BR 0x34001092
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450 #define TIMER5_MD 0x34001082
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451
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452 #define TIMER_CR TIMER5_CR
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453 #define TIMER_BR TIMER5_BR
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454 #define TIMER_MD TIMER5_MD
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455
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456 #define TIMER0_MD 0x34001000
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457 #define TIMER0_BR 0x34001010
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458 #define TIMER0_CR 0x34001020
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459
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460 #endif
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461
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462 //-----------------------------------------------------------------------------
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463 // Static data used by HAL
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464
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465 // ISR tables
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466 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYG_ISR_COUNT];
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467 externC volatile CYG_ADDRWORD hal_interrupt_data[CYG_ISR_COUNT];
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468 externC volatile CYG_ADDRESS hal_interrupt_objects[CYG_ISR_COUNT];
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469
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470 // VSR table
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471 externC volatile CYG_ADDRESS hal_vsr_table[CYG_VSR_COUNT];
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472
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473 // MN10300 interrupt control registers, mapped by linker script.
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474 externC volatile cyg_uint16 mn10300_interrupt_control[0x300/2];
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475
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476 //-----------------------------------------------------------------------------
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477 // Interrupt state storage
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478
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479 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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480
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481 //-----------------------------------------------------------------------------
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482 // Interrupt control macros
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483
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484 #define HAL_DISABLE_INTERRUPTS(_old_) \
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485 asm volatile ( \
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486 "mov psw,%0;" \
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diff changeset
487 "mov 0xF7FF,d0;" \
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diff changeset
488 "and %0,d0;" \
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diff changeset
489 "mov d0,psw;" \
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490 "and 0x0800,%0;" \
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491 : "=d"(_old_) \
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492 : \
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493 : "d0" \
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494 );
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495
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496 #define HAL_ENABLE_INTERRUPTS() \
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497 asm volatile ( \
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498 "mov psw,d0;" \
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diff changeset
499 "or 0x0800,d0;" \
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diff changeset
500 "mov d0,psw;" \
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501 : \
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jlarmour
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502 : \
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503 : "d0" \
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504 );
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505
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506 #define HAL_RESTORE_INTERRUPTS(_old_) \
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507 asm volatile ( \
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508 "mov psw,d1;" \
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diff changeset
509 "or %0,d1;" \
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
510 "mov d1,psw;" \
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511 : \
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512 : "d"(_old_) \
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513 : "d1" \
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514 );
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515
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516 #define HAL_QUERY_INTERRUPTS(_old_) \
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517 asm volatile ( \
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518 "mov psw,%0;" \
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519 "and 0x0800,%0;" \
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520 : "=d"(_old_) \
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521 );
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522
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523 //-----------------------------------------------------------------------------
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524 // Translate a vector number into an ISR table index.
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525 // If we have chained interrupts we have just a single ISR per priority
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526 // level. On the MN103000 there are several interrupts per controller,
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527 // so we have to decode to one of 100 vectors. On the MN103002 there is
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528 // only one interrupt per controller, so we can have just one ISR per
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529 // controller, except for the NMI vectors which occupy the first 3 slots.
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530
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531 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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532
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533 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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534 { \
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535 /* ICRs are 16 bit regs at 32 bit spacing */ \
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536 cyg_ucount16 _ix_ = ((_vector_)>>2)<<1; \
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537 \
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538 /* read the appropriate interrupt control register */ \
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539 cyg_uint16 _icr_ = mn10300_interrupt_control[_ix_]; \
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540 \
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541 /* extract interrupt priority level */ \
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542 _index_ = (_icr_ >> 12) & 0x7; \
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543 }
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544
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545 #else
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546
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547 #if defined(CYG_HAL_MN10300_MN103000)
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548
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549 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
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550
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551 #elif defined(CYG_HAL_MN10300_MN103002)
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552
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553 //#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = ((_vector_)>>2)
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554
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555 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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556 _index_ = (((_vector_)<=CYG_VECTOR_SYSTEM_ERROR) ? \
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557 (_vector_) : \
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558 (((_vector_)>>2)+CYG_VECTOR_RESERVED_3))
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559
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560 #endif
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561
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562 #endif
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563
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564
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565 //-----------------------------------------------------------------------------
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566 // Interrupt and VSR attachment macros
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567
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568 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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569 { \
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570 cyg_uint32 _index_; \
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571 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
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572 \
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573 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)NULL ) \
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574 { \
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575 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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576 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
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577 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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578 } \
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579 }
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580
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581 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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582 { \
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583 cyg_uint32 _index_; \
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584 HAL_TRANSLATE_VECTOR(_vector_,_index_); \
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585 \
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586 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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587 { \
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588 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)NULL; \
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589 hal_interrupt_data[_index_] = 0; \
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590 hal_interrupt_objects[_index_] = 0; \
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591 } \
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592 }
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593
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594 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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595 *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
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596
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597
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598 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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599 if( _poldvsr_ != NULL ) \
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600 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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601 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;
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602
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603
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604 //-----------------------------------------------------------------------------
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605 // Interrupt controller access
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606 // Read interrupt control registers back after writing to them. This
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607 // ensures that the written value is not sitting in the store buffers
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608 // when interrupts are re-enabled.
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609 #define HAL_INTERRUPT_MASK( _vector_ ) \
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610 { \
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611 /* ICRs are 16 bit regs at 32 bit spacing */ \
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612 cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \
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613 \
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614 /* read the appropriate interrupt control register */ \
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615 cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \
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616 \
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617 /* clear interrupt enable bit for this vector */ \
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618 _icr_ &= ~(0x0100<<((_vector_)&3)); \
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619 \
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620 /* restore the interrupt control register */ \
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621 mn10300_interrupt_control[_index_] = _icr_; \
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622 _icr_ = mn10300_interrupt_control[_index_]; \
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623 }
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624
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625 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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626 { \
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627 /* ICRs are 16 bit regs at 32 bit spacing */ \
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628 cyg_ucount16 _index_ = (_vector_>>2)<<1; \
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629 \
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630 /* read the appropriate interrupt control register */ \
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631 cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \
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632 \
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633 /* set interrupt enable bit for this vector */ \
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634 _icr_ |= (0x0100<<(_vector_&3)); \
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635 \
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636 /* restore the interrupt control register */ \
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637 mn10300_interrupt_control[_index_] = _icr_; \
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638 _icr_ = mn10300_interrupt_control[_index_]; \
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639 }
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640
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641 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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642 { \
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643 /* ICRs are 16 bit regs at 32 bit spacing */ \
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644 cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \
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645 \
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646 /* read the appropriate interrupt control register */ \
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647 cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \
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648 \
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649 /* clear interrupt request bit for this vector */ \
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650 _icr_ &= ~(0x0010<<((_vector_)&3)); \
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651 \
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652 /* set interrupt detect bit for this vector */ \
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653 _icr_ |= (0x0001<<((_vector_)&3)); \
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654 \
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655 /* restore the interrupt control register */ \
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656 mn10300_interrupt_control[_index_] = _icr_; \
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657 _icr_ = mn10300_interrupt_control[_index_]; \
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658 }
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659
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660 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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661 { \
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662 cyg_vector _v_ = _vector_; \
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663 /* adjust vector to bit offset in EXTMD */ \
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664 _v_ -= CYG_VECTOR_EXTERNAL_0; \
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665 _v_ >>= 1; \
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666 \
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667 cyg_uint16 _val_ = 0; \
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668 \
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669 /* set bits according to requirements */ \
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670 if( _up_ ) _val_ |= 1; \
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671 if( !(_level_) ) _val_ |= 2; \
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672 \
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673 /* get EXTMD */ \
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674 cyg_uint16 _reg_ = mn10300_interrupt_control[0x180>>1]; \
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675 \
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676 /* clear old value and set new */ \
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677 _reg_ &= ~(3<<_v_); \
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678 _reg_ |= _val_<<_v_; \
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679 \
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680 /* restore EXTMD */ \
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681 mn10300_interrupt_control[0x180>>1] = _reg_; \
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682 }
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683
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684 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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685 { \
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686 /* ICRs are 16 bit regs at 32 bit spacing */ \
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687 cyg_ucount16 _index_ = (_vector_>>2)<<1; \
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688 \
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689 /* read the appropriate interrupt control register */ \
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690 cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \
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691 \
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692 /* set interrupt level for this group of vectors */ \
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693 _icr_ &= 0x0FFF; \
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694 _icr_ |= (_level_)<<12; \
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695 \
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696 /* restore the interrupt control register */ \
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697 mn10300_interrupt_control[_index_] = _icr_; \
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698 _icr_ = mn10300_interrupt_control[_index_]; \
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699 }
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700
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701 //-----------------------------------------------------------------------------
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702 // Clock control
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703
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704
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705 #if 0 // defined(CYG_HAL_MN10300_SIM)
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706
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707 #define OEA_DEV 0x31000000
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708
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709 #define HAL_SWAP(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)| \
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710 (((x)&0xff0000)>>8)|(((x)&0xff000000)>>24))
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711
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712 #define PAL_COUNTDOWN_TIMER 0x20 // one shot on IR0
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713 #define PAL_COUNTDOWN_VALUE 0x24
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714 #define PAL_PERIODIC_TIMER 0x28 // repeating on IR1
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715 #define PAL_PERIODIC_VALUE 0x2c
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716
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717
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718 // IRQ1 set to receive clock intrs
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719 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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720 { \
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721 volatile cyg_uint32 *timer = (cyg_uint32 *) \
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722 (OEA_DEV + PAL_PERIODIC_TIMER); \
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723 cyg_uint32 p = _period_; \
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724 \
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725 *timer = HAL_SWAP(p); \
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726 }
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727
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728 #elif defined(CYG_HAL_MN10300_MN103000)
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729
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730 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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731 { \
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732 volatile cyg_uint16 *timer_ctr = (cyg_uint16 *)TIMER_BR; \
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733 volatile cyg_uint16 *timer_mode = (cyg_uint16 *)TIMER_MD; \
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734 volatile cyg_uint8 *timer_a_mode = (cyg_uint8 *)0x34001084; \
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735 \
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736 *timer_a_mode = 0x04; \
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737 \
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738 *timer_ctr = 0xf000; \
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739 \
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740 *timer_mode = 0x0013; \
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741 *timer_mode = 0x4013; \
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742 *timer_mode = 0x0013; \
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743 *timer_mode = 0x8013; \
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744 }
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745
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746 #elif defined(CYG_HAL_MN10300_MN103002)
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747
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748 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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749 { \
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750 volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \
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751 volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \
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752 volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \
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753 volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \
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754 \
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755 /* Set timers 4 and 5 into cascade mode */ \
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756 \
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757 *timer5_br = (_period_)>>16; \
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758 \
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759 *timer5_md = 0x40; \
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760 *timer5_md = 0x83; \
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761 \
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762 *timer4_br = (_period_)&0x0000FFFF; \
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763 \
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764 *timer4_md = 0x40; \
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765 *timer4_md = 0x80; \
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766 }
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767
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768 #else
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769
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770 #error Undefined MN10300 model
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771
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772 #endif
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773
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774 #define HAL_CLOCK_RESET( _vector_, _period_ )
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775
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776 #if 0 //def CYG_HAL_MN10300_SIM
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777
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778 // This timer counts down, so subtract from set value.
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779 #define HAL_CLOCK_READ( _pvalue_ ) \
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780 { \
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781 volatile cyg_uint32 *timer = (cyg_uint32 *) \
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782 (OEA_DEV + PAL_PERIODIC_TIMER); \
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783 volatile cyg_uint32 *value = (cyg_uint32 *) \
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784 (OEA_DEV + PAL_PERIODIC_VALUE); \
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785 cyg_uint32 t,v; \
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786 t = *timer; \
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787 v = *value; \
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788 *(_pvalue_) = HAL_SWAP(t) - HAL_SWAP(v); \
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789 }
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790
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791 #else // CYG_HAL_MN10300_SIM not
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792 #define HAL_CLOCK_READ( _pvalue_ ) \
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793 { \
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794 volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \
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795 volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \
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796 \
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797 cyg_uint16 t5; \
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798 cyg_uint16 t4; \
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799 \
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800 /* Loop reading the two timers until we can read t5 twice */ \
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801 /* with the same value. This avoids getting silly times if */ \
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802 /* the timers carry between reading the two regs. */ \
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803 do { \
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804 t5 = *timer5_cr; \
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805 t4 = *timer4_cr; \
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806 } while( t5 != *timer5_cr ); \
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807 \
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808 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \
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809 }
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810 #endif // CYG_HAL_MN10300_SIM
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811 //-----------------------------------------------------------------------------
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812 #endif // ifndef CYGONCE_HAL_HAL_INTR_H
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813 // End of hal_intr.h