|
0
|
1 #ifndef CYGONCE_HAL_HAL_IO_H |
|
|
2 #define CYGONCE_HAL_HAL_IO_H |
|
|
3 |
|
|
4 //============================================================================= |
|
|
5 // |
|
|
6 // hal_io.h |
|
|
7 // |
|
|
8 // HAL device IO register support. |
|
|
9 // |
|
|
10 //============================================================================= |
|
|
11 //####COPYRIGHTBEGIN#### |
|
|
12 // |
|
|
13 // ------------------------------------------- |
|
|
14 // The contents of this file are subject to the Cygnus eCos Public License |
|
|
15 // Version 1.0 (the "License"); you may not use this file except in |
|
|
16 // compliance with the License. You may obtain a copy of the License at |
|
|
17 // http://sourceware.cygnus.com/ecos |
|
|
18 // |
|
|
19 // Software distributed under the License is distributed on an "AS IS" |
|
|
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
|
|
21 // License for the specific language governing rights and limitations under |
|
|
22 // the License. |
|
|
23 // |
|
|
24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
|
|
25 // September 30, 1998. |
|
|
26 // |
|
|
27 // The Initial Developer of the Original Code is Cygnus. Portions created |
|
|
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
|
|
29 // ------------------------------------------- |
|
|
30 // |
|
|
31 //####COPYRIGHTEND#### |
|
|
32 //============================================================================= |
|
|
33 //#####DESCRIPTIONBEGIN#### |
|
|
34 // |
|
|
35 // Author(s): nickg |
|
|
36 // Contributors: nickg |
|
|
37 // Date: 1998-02-17 |
|
|
38 // Purpose: Define IO register support |
|
|
39 // Description: The macros defined here provide the HAL APIs for handling |
|
|
40 // device IO control registers. |
|
|
41 // |
|
|
42 // Usage: |
|
|
43 // #include <cyg/hal/hal_io.h> |
|
|
44 // ... |
|
|
45 // |
|
|
46 // |
|
|
47 //####DESCRIPTIONEND#### |
|
|
48 // |
|
|
49 //============================================================================= |
|
|
50 |
|
|
51 #include <cyg/infra/cyg_type.h> |
|
|
52 |
|
|
53 //----------------------------------------------------------------------------- |
|
|
54 // IO Register address. |
|
|
55 // This type is for recording the address of an IO register. |
|
|
56 |
|
|
57 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; |
|
|
58 |
|
|
59 //----------------------------------------------------------------------------- |
|
|
60 // BYTE Register access. |
|
|
61 // Individual and vectorized access to 8 bit registers. |
|
|
62 |
|
|
63 #define HAL_READ_UINT8( _register_, _value_ ) \ |
|
|
64 ((_value_) = *((volatile CYG_BYTE *)(_register_))) |
|
|
65 |
|
|
66 #define HAL_WRITE_UINT8( _register_, _value_ ) \ |
|
|
67 (*((volatile CYG_BYTE *)(_register_)) = (_value_)) |
|
|
68 |
|
|
69 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
70 { \ |
|
|
71 cyg_count32 _i_,_j_; \ |
|
|
72 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
73 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ |
|
|
74 } |
|
|
75 |
|
|
76 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
77 { \ |
|
|
78 cyg_count32 _i_,_j_; \ |
|
|
79 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
80 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ |
|
|
81 } |
|
|
82 |
|
|
83 |
|
|
84 //----------------------------------------------------------------------------- |
|
|
85 // 16 bit access. |
|
|
86 // Individual and vectorized access to 16 bit registers. |
|
|
87 |
|
|
88 #define HAL_READ_UINT16( _register_, _value_ ) \ |
|
|
89 ((_value_) = *((volatile CYG_WORD16 *)(_register_))) |
|
|
90 |
|
|
91 #define HAL_WRITE_UINT16( _register_, _value_ ) \ |
|
|
92 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) |
|
|
93 |
|
|
94 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
95 { \ |
|
|
96 cyg_count32 _i_,_j_; \ |
|
|
97 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
98 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ |
|
|
99 } |
|
|
100 |
|
|
101 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
102 { \ |
|
|
103 cyg_count32 _i_,_j_; \ |
|
|
104 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
105 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
|
|
106 } |
|
|
107 |
|
|
108 //----------------------------------------------------------------------------- |
|
|
109 // 32 bit access. |
|
|
110 // Individual and vectorized access to 32 bit registers. |
|
|
111 |
|
|
112 #define HAL_READ_UINT32( _register_, _value_ ) \ |
|
|
113 ((_value_) = *((volatile CYG_WORD32 *)(_register_))) |
|
|
114 |
|
|
115 #define HAL_WRITE_UINT32( _register_, _value_ ) \ |
|
|
116 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) |
|
|
117 |
|
|
118 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
119 { \ |
|
|
120 cyg_count32 _i_,_j_; \ |
|
|
121 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
122 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ |
|
|
123 } |
|
|
124 |
|
|
125 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
|
|
126 { \ |
|
|
127 cyg_count32 _i_,_j_; \ |
|
|
128 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
|
|
129 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
|
|
130 } |
|
|
131 |
|
|
132 //----------------------------------------------------------------------------- |
|
|
133 #endif // ifndef CYGONCE_HAL_HAL_IO_H |
|
|
134 // End of hal_io.h |
