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1 #ifndef CYGONCE_KERNEL_INTR_HXX |
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2 #define CYGONCE_KERNEL_INTR_HXX |
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3 |
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4 //========================================================================== |
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5 // |
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6 // intr.hxx |
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7 // |
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8 // Interrupt class declaration(s) |
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9 // |
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10 //========================================================================== |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //========================================================================== |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1997-09-09 |
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38 // Purpose: Define Interrupt class interfaces |
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39 // Description: The classes defined here provide the APIs for handling |
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40 // interrupts. |
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41 // Usage: #include "intr.hxx" |
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42 // |
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43 // |
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44 //####DESCRIPTIONEND#### |
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45 // |
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46 //========================================================================== |
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47 |
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48 #include <cyg/kernel/ktypes.h> |
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49 |
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50 // ------------------------------------------------------------------------- |
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51 // Function prototype typedefs |
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52 |
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53 |
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54 // VSR = Vector Service Routine. This is the code attached directly to an |
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55 // interrupt vector. It is very architecture/platform specific and usually |
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56 // must be written in assembler. |
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57 |
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58 typedef void cyg_VSR(); |
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59 |
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60 // ISR = Interrupt Service Routine. This is called from the default |
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61 // VSR in response to an interrupt. It may access shared data but may |
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62 // not call kernel routines. The return value may be |
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63 // Cyg_Interrupt::HANDLED and/or Cyg_Interrupt::CALL_DSR. |
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64 |
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65 typedef cyg_uint32 cyg_ISR(cyg_vector vector, CYG_ADDRWORD data); |
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66 |
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67 // DSR = Deferred Service Routine. This is called if the ISR returns |
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68 // the Cyg_Interrupt::CALL_DSR bit. It is called at a "safe" point in |
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69 // the kernel where it may make calls on kernel routines. The count |
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70 // argument indicates how many times the ISR has asked for the DSR to |
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71 // be posted since the last time the DSR ran. |
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72 |
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73 typedef void cyg_DSR(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data); |
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74 |
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75 // ------------------------------------------------------------------------- |
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76 // Include HAL definitions |
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77 |
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78 class Cyg_Interrupt; |
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79 |
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80 #include <cyg/hal/hal_arch.h> |
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81 |
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82 #include <cyg/hal/hal_intr.h> |
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83 |
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84 externC void interrupt_end( |
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85 cyg_uint32 isr_ret, |
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86 Cyg_Interrupt *intr, |
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87 HAL_SavedRegisters *ctx |
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88 ); |
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89 |
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90 // ------------------------------------------------------------------------- |
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91 // Interrupt class. This both represents each interrupt and provides a static |
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92 // interface for controlling the interrupt hardware. |
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93 |
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94 class Cyg_Interrupt |
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95 { |
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96 |
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97 friend class Cyg_Scheduler; |
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98 friend void interrupt_end( cyg_uint32, |
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99 Cyg_Interrupt *, |
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100 HAL_SavedRegisters *); |
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101 |
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102 cyg_vector vector; // Interrupt vector |
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103 |
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104 cyg_priority priority; // Queuing priority |
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105 |
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106 cyg_ISR *isr; // Pointer to ISR |
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107 |
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108 cyg_DSR *dsr; // Pointer to DSR |
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109 |
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110 CYG_ADDRWORD data; // Data pointer |
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111 |
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112 |
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113 |
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114 // DSR handling interface called by the scheduler |
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115 |
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116 // Check for pending DSRs |
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117 static cyg_bool DSRs_pending(); |
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118 |
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119 // Call any pending DSRs |
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120 static void call_pending_DSRs(); |
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121 |
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122 void post_dsr(); // Post the DSR for this interrupt |
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123 |
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124 // Data structures for handling DSR calls. We implement two DSR |
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125 // handling mechanisms, a list based one and a table based |
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126 // one. The list based mechanism is safe with respect to temporary |
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127 // overloads and will not run out of resource. However it requires |
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128 // extra data per interrupt object, and interrupts must be turned |
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129 // off briefly when delivering the DSR. The table based mechanism |
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130 // does not need unnecessary interrupt switching, but may be prone |
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131 // to overflow on overload. However, since a correctly programmed |
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132 // real time application should not experience such a condition, |
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133 // the table based mechanism is more efficient for real use. The |
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134 // list based mechainsm is enabled by default since it is safer to |
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135 // use during development. |
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136 |
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137 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
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138 |
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139 static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; |
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140 |
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141 static cyg_ucount32 dsr_table_head; |
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142 |
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143 static cyg_ucount32 dsr_table_tail; |
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144 |
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145 #endif |
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146 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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147 |
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148 cyg_ucount32 dsr_count; // Number of DSR posts made |
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149 |
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150 Cyg_Interrupt *next_dsr; // next DSR in list |
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151 |
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152 static Cyg_Interrupt *dsr_list; // static list of pending DSRs |
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153 |
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154 #endif |
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155 |
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156 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
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157 |
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158 // The default mechanism for handling interrupts is to attach just |
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159 // one Interrupt object to each vector. In some cases, and on some |
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160 // hardware, this is not possible, and each vector must carry a chain |
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161 // of interrupts. |
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162 |
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163 Cyg_Interrupt *next; // Next Interrupt in list |
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164 |
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165 // Chaining ISR inserted in HAL vector |
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166 static cyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data); |
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167 |
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168 // Table of interrupt chains |
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169 static Cyg_Interrupt *chain_list[CYG_ISR_COUNT]; |
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170 |
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171 #endif |
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172 |
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173 public: |
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174 |
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175 Cyg_Interrupt // Initialize interrupt |
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176 ( |
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177 cyg_vector vector, // Vector to attach to |
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178 cyg_priority priority, // Queue priority |
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179 CYG_ADDRWORD data, // Data pointer |
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180 cyg_ISR *isr, // Interrupt Service Routine |
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181 cyg_DSR *dsr // Deferred Service Routine |
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182 ); |
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183 |
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184 ~Cyg_Interrupt(); |
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185 |
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186 // ISR return values |
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187 enum { |
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188 HANDLED = 1, // Interrupt was handled |
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189 CALL_DSR = 2 // Schedule DSR |
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190 }; |
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191 |
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192 // Interrupt management |
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193 |
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194 void attach(); // Attach to vector |
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195 |
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196 |
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197 void detach(); // Detach from vector |
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198 |
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199 |
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200 // Static Interrupt management functions |
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201 |
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202 // Get the current service routine |
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203 static void get_vsr(cyg_vector vector, cyg_VSR **vsr); |
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204 |
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205 // Install a vector service routine |
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206 static void set_vsr( |
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207 cyg_vector vector, // hardware vector to replace |
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208 cyg_VSR *vsr, // my new service routine |
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209 cyg_VSR **old = NULL // pointer to old vsr, if required |
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210 ); |
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211 |
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212 |
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213 // Static interrupt masking functions |
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214 |
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215 // Disable interrupts at the CPU |
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216 static void disable_interrupts(); |
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217 |
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218 // Re-enable CPU interrupts |
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219 static void enable_interrupts(); |
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220 |
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221 // Are interrupts enabled at the CPU? |
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222 static inline cyg_bool interrupts_enabled() |
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223 { |
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224 CYG_WORD result; // needs to be register sized |
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225 HAL_QUERY_INTERRUPTS( result ); |
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226 return (0 != result); |
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227 } |
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228 |
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229 // Get the vector for the following calls |
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230 inline cyg_vector get_vector() |
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231 { |
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232 return vector; |
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233 } |
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234 |
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235 // Static PIC control functions |
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236 |
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237 // Mask a specific interrupt in a PIC |
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238 static void mask_interrupt(cyg_vector vector); |
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239 |
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240 // Clear PIC mask |
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241 static void unmask_interrupt(cyg_vector vector); |
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242 |
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243 // Acknowledge interrupt at PIC |
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244 static void acknowledge_interrupt(cyg_vector vector); |
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245 |
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246 // Change interrupt detection at PIC |
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247 static void configure_interrupt( |
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248 cyg_vector vector, // vector to control |
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249 cyg_bool level, // level or edge triggered |
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250 cyg_bool up // hi/lo level, rising/falling edge |
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251 ); |
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252 |
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253 }; |
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254 |
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255 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS |
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256 // ------------------------------------------------------------------------- |
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257 // Check for pending DSRs |
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258 |
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259 inline cyg_bool Cyg_Interrupt::DSRs_pending() |
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260 { |
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261 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
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262 |
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263 return dsr_table_head != dsr_table_tail; |
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264 |
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265 #endif |
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266 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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267 |
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268 return dsr_list != NULL; |
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269 |
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270 #endif |
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271 }; |
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272 #endif // CYGIMP_KERNEL_INTERRUPTS_DSRS |
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273 |
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274 // ------------------------------------------------------------------------- |
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275 #endif // ifndef CYGONCE_KERNEL_INTR_HXX |
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276 // EOF intr.hxx |
