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annotate packages/hal/arm/cl7211/current/include/hal_platform_setup.h @ 32:5af43b635655 ecos-sw-1999-08-18

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Merge from eCos master repository on 1999-08-18-15:20:01-BST
author jlarmour
date Wed, 18 Aug 1999 15:33:44 +0000
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children e97d78785e2d
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1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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2 #define CYGONCE_HAL_PLATFORM_SETUP_H
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3
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4 /*=============================================================================
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5 //
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6 // hal_platform_setup.h
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7 //
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8 // Platform specific support for HAL (assembly code)
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): gthomas
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36 // Contributors: gthomas
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37 // Date: 1999-04-21
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38 // Purpose: Cirrus CL7211 platform specific support routines
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39 // Description:
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40 // Usage: #include <cyg/hal/hal_platform_setup.h>
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41 //
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42 //####DESCRIPTIONEND####
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43 //
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44 //===========================================================================*/
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45
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46 #include <pkgconf/system.h> // System-wide configuration info
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47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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48 #include <cyg/hal/hal_cl7211.h> // Platform specific hardware definitions
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49 #include <cyg/hal/hal_mmu.h> // MMU definitions
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50
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51 #define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU
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52
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53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS)
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54
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55 //
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56 // Memory map - set up by ROM (GDB stubs)
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57 //
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58 // Region Logical Address Physical Address
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59 // DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below)
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60 // Expansion 2 0x20000000 0x20000000
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61 // Expansion 3 0x30000000 0x30000000
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62 // PCMCIA 0 0x40000000 0x40000000
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63 // PCMCIA 1 0x50000000 0x50000000
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64 // SRAM 0x60000000..0x600007FF 0x60000000
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65 // I/O 0x80000000 0x80000000
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66 // MMU Tables 0xC00y0000
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67 // LCD buffer 0xC0000000..0xC001FFFF 0xC0000000
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68 // ROM 0xE0000000..0xEFFFFFFF 0x00000000
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69 // ROM 0xF0000000..0xFFFFFFFF 0x10000000
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70
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71 #ifdef CYGHWR_HAL_ARM_CL7211_LCD_INSTALLED
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72 #define MMU_BASE 0xC0020000
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73 #define PTE_BASE 0xC0024000
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74 #define LCD_BUFFER_SIZE 0x00020000
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75 #else
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76 #define MMU_BASE 0xC0000000
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77 #define PTE_BASE 0xC0004000
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78 #define LCD_BUFFER_SIZE 0x00000000
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79 #endif
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80 #if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2)
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81 #define MMU_TABLES_SIZE 0x4000+0x1000+0x1000 // RAM used for PTE entries
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82 #define DRAM_LA_END 0x00200000-MMU_TABLES_SIZE
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83 #elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16)
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84 #define MMU_TABLES_SIZE 0x4000+0x4000+0x1000 // RAM used for PTE entries
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85 #define DRAM_LA_END 0x01000000-MMU_TABLES_SIZE
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86 #endif
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87 #define DRAM_LA_START 0x00000000
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88 #define DRAM_PA MMU_BASE+MMU_TABLES_SIZE
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89 #define LCD_LA_START 0xC0000000
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90 #define LCD_LA_END 0xC0020000
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91 #define LCD_PA 0xC0000000
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92 #define ROM0_LA_START 0xE0000000
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93 #define ROM0_PA 0x00000000
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94 #define ROM1_LA_START 0xF0000000
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95 #define ROM1_LA_END 0x00000000
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96 #define ROM1_PA 0x10000000
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97 #define EXPANSION2_LA_START 0x20000000
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98 #define EXPANSION2_PA 0x20000000
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99 #define EXPANSION3_LA_START 0x30000000
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100 #define EXPANSION3_PA 0x30000000
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101 #define PCMCIA0_LA_START 0x40000000
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102 #define PCMCIA0_PA 0x40000000
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103 #define PCMCIA1_LA_START 0x50000000
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104 #define PCMCIA1_PA 0x50000000
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105 #define SRAM_LA_START 0x60000000
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106 #define SRAM_LA_END 0x60001000
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107 #define SRAM_PA 0x60000000
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108 #define IO_LA_START 0x80000000
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109 #define IO_LA_END 0x80003000
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110 #define IO_PA 0x80000000
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111
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112 #if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2)
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113 // Note: The DRAM on this board is very irregular in that every
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114 // other 256K piece is missing. E.g. only these [physical]
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115 // addresses are valid:
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116 // 0xC0000000..0xC003FFFF
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117 // 0xC0080000..0xC00BFFFF
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118 // 0xC0200000..0xC023FFFF Note the additional GAP!
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119 // etc.
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120 // 0xC0800000..0xC083FFFF Note the additional GAP!
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121 // 0xC0880000..0xC08CFFFF
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122 // 0xC0A00000..0xC0A3FFFF
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123 // etc.
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124 // The MMU mapping code takes this into consideration and creates
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125 // a continuous logical map for the DRAM.
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126 #define MAP_DRAM \
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127 /* Map DRAM */ ;\
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128 ldr r3,=DRAM_LA_START ;\
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129 ldr r4,=DRAM_LA_END ;\
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130 ldr r5,=DRAM_PA ;\
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131 /* 0x00000000..0x000FFFFF */ ;\
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132 mov r6,r2 /* Set up page table descriptor */ ;\
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133 ldr r7,=MMU_L1_TYPE_Page ;\
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134 orr r6,r6,r7 ;\
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135 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
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136 10: mov r6,r5 /* Build page table entry */ ;\
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137 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
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138 orr r6,r6,r7 ;\
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diff changeset
139 ldr r7,=MMU_PAGE_SIZE ;\
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jlarmour
parents:
diff changeset
140 str r6,[r2],#4 /* Next page */ ;\
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jlarmour
parents:
diff changeset
141 add r3,r3,r7 ;\
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jlarmour
parents:
diff changeset
142 add r5,r5,r7 ;\
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jlarmour
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diff changeset
143 ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE ;\
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parents:
diff changeset
144 cmp r3,r8 /* Done with first 1M? */ ;\
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jlarmour
parents:
diff changeset
145 beq 20f ;\
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jlarmour
parents:
diff changeset
146 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
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jlarmour
parents:
diff changeset
147 and r7,r7,r5 ;\
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jlarmour
parents:
diff changeset
148 cmp r7,#0 ;\
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jlarmour
parents:
diff changeset
149 beq 10b ;\
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jlarmour
parents:
diff changeset
150 add r5,r5,r7 /* Skip 256K hole */ ;\
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jlarmour
parents:
diff changeset
151 ldr r7,=0x100000 ;\
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jlarmour
parents:
diff changeset
152 and r7,r5,r7 ;\
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jlarmour
parents:
diff changeset
153 beq 10b ;\
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parents:
diff changeset
154 add r5,r5,r7 /* Nothing at 0xC0100000 */ ;\
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jlarmour
parents:
diff changeset
155 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
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parents:
diff changeset
156 and r7,r5,r7 ;\
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jlarmour
parents:
diff changeset
157 beq 10b ;\
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jlarmour
parents:
diff changeset
158 add r5,r5,r7 ;\
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parents:
diff changeset
159 b 10b ;\
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diff changeset
160 20: ;\
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jlarmour
parents:
diff changeset
161 /* 0x00100000..0x001FFFFF */ ;\
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diff changeset
162 mov r6,r2 /* Set up page table descriptor */ ;\
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diff changeset
163 ldr r7,=MMU_L1_TYPE_Page ;\
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diff changeset
164 orr r6,r6,r7 ;\
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165 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
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166 10: mov r6,r5 /* Build page table entry */ ;\
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167 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
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168 orr r6,r6,r7 ;\
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diff changeset
169 ldr r7,=MMU_PAGE_SIZE ;\
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jlarmour
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diff changeset
170 str r6,[r2],#4 /* Next page */ ;\
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parents:
diff changeset
171 add r3,r3,r7 ;\
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parents:
diff changeset
172 cmp r3,r4 /* Done with first DRAM? */ ;\
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diff changeset
173 beq 20f ;\
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parents:
diff changeset
174 add r5,r5,r7 ;\
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diff changeset
175 ldr r7,=0x40000 /* Special check for 256K boundary */ ;\
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parents:
diff changeset
176 and r7,r7,r5 ;\
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diff changeset
177 cmp r7,#0 ;\
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parents:
diff changeset
178 beq 10b ;\
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jlarmour
parents:
diff changeset
179 add r5,r5,r7 /* Skip 256K hole */ ;\
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parents:
diff changeset
180 ldr r7,=0x100000 ;\
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diff changeset
181 and r7,r5,r7 ;\
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diff changeset
182 beq 10b ;\
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diff changeset
183 add r5,r5,r7 /* Nothing at 0xC0300000 */ ;\
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184 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\
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diff changeset
185 and r7,r5,r7 ;\
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diff changeset
186 beq 10b ;\
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diff changeset
187 add r5,r5,r7 ;\
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diff changeset
188 b 10b ;\
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189 20: ;
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190 #elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16)
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191 // The 16M board is arranged as:
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192 // 0xC0000000..0xC07FFFFF
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193 // 0xC1000000..0xC17FFFFF
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194 #define MAP_DRAM \
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195 /* Map DRAM */ ;\
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196 ldr r3,=DRAM_LA_START ;\
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diff changeset
197 ldr r4,=DRAM_LA_END ;\
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diff changeset
198 ldr r5,=DRAM_PA ;\
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diff changeset
199 /* 0xXXX00000..0xXXXFFFFF */ ;\
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diff changeset
200 10: mov r6,r2 /* Set up page table descriptor */ ;\
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diff changeset
201 ldr r7,=MMU_L1_TYPE_Page ;\
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diff changeset
202 orr r6,r6,r7 ;\
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203 str r6,[r1],#4 /* Store PTE, update pointer */ ;\
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204 ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE ;\
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diff changeset
205 ldr r6,=DRAM_PA+0x00800000 /* Need to skip at 8M boundary */ ;\
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diff changeset
206 cmp r5,r6 ;\
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diff changeset
207 bne 15f ;\
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diff changeset
208 ldr r5,=DRAM_PA+0x01000000 /* Next chunk of DRAM */ ;\
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diff changeset
209 15: mov r6,r5 /* Build page table entry */ ;\
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diff changeset
210 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
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diff changeset
211 orr r6,r6,r7 ;\
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jlarmour
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diff changeset
212 ldr r7,=MMU_PAGE_SIZE ;\
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jlarmour
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diff changeset
213 str r6,[r2],#4 /* Next page */ ;\
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parents:
diff changeset
214 add r3,r3,r7 ;\
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parents:
diff changeset
215 add r5,r5,r7 ;\
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diff changeset
216 cmp r3,r4 /* End of DRAM? */ ;\
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diff changeset
217 beq 20f ;\
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diff changeset
218 sub r8,r8,#1 /* End of 1M section? */ ;\
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diff changeset
219 cmp r8,#0 ;\
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jlarmour
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diff changeset
220 bne 15b /* Next page */ ;\
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diff changeset
221 b 10b /* Next section */ ;\
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diff changeset
222 20:
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jlarmour
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diff changeset
223 #else
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224 #err Invalid DRAM size selected
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diff changeset
225 #endif
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diff changeset
226
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diff changeset
227 #ifdef CYG_HAL_ARM_CL7111 // CL7111, 710 processor
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diff changeset
228 #define MMU_INITIALIZE \
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diff changeset
229 ldr r1,=MMU_Control_Init ;\
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diff changeset
230 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
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diff changeset
231 ldr r1,=MMU_BASE ;\
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diff changeset
232 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
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diff changeset
233 mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */ ;\
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jlarmour
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diff changeset
234 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
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diff changeset
235 ldr r1,=0xFFFFFFFF ;\
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jlarmour
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diff changeset
236 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
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diff changeset
237 ldr r2,=10f ;\
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diff changeset
238 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
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jlarmour
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diff changeset
239 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
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diff changeset
240 mov pc,r2 /* Change address spaces */ ;\
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diff changeset
241 nop ;\
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jlarmour
parents:
diff changeset
242 nop ;\
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parents:
diff changeset
243 nop ;\
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jlarmour
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diff changeset
244 10:
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jlarmour
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diff changeset
245 #else // EP7211, 720T processor
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jlarmour
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diff changeset
246 #define MMU_INITIALIZE \
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diff changeset
247 ldr r1,=MMU_Control_Init ;\
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jlarmour
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diff changeset
248 mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\
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diff changeset
249 ldr r1,=MMU_BASE ;\
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diff changeset
250 mcr MMU_CP,0,r1,MMU_Base,c0 ;\
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diff changeset
251 mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB - 720 style */ ;\
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diff changeset
252 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\
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diff changeset
253 ldr r1,=0xFFFFFFFF ;\
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diff changeset
254 mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\
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diff changeset
255 ldr r2,=10f ;\
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jlarmour
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diff changeset
256 ldr r1,=MMU_Control_Init|MMU_Control_M ;\
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jlarmour
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diff changeset
257 mcr MMU_CP,0,r1,MMU_Control,c0 ;\
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parents:
diff changeset
258 mov pc,r2 /* Change address spaces */ ;\
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jlarmour
parents:
diff changeset
259 nop ;\
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jlarmour
parents:
diff changeset
260 nop ;\
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jlarmour
parents:
diff changeset
261 nop ;\
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jlarmour
parents:
diff changeset
262 10:
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jlarmour
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diff changeset
263 #endif
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jlarmour
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diff changeset
264
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jlarmour
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diff changeset
265 #define PLATFORM_SETUP1 \
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jlarmour
parents:
diff changeset
266 /* Initialize memory configuration */ ;\
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jlarmour
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diff changeset
267 ldr r1,=MEMCFG1 ;\
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jlarmour
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diff changeset
268 ldr r2,=0x8200A080 /* FIXME - what is this? */ ;\
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jlarmour
parents:
diff changeset
269 str r2,[r1] ;\
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jlarmour
parents:
diff changeset
270 ldr r1,=MEMCFG2 ;\
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jlarmour
parents:
diff changeset
271 ldr r2,=0xFEFC0000 ;\
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jlarmour
parents:
diff changeset
272 str r2,[r1] ;\
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jlarmour
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diff changeset
273 ldr r1,=DRFPR ;\
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jlarmour
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diff changeset
274 ldr r2,=0x81 /* DRAM refresh = 64KHz */ ;\
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jlarmour
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diff changeset
275 strb r2,[r1] ;\
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diff changeset
276 /* Initialize MMU to create new memory map */ ;\
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277 ldr r1,=MMU_BASE ;\
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278 ldr r2,=PTE_BASE ;\
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279 MAP_DRAM ;\
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280 /* Nothing until PCMCIA0 */ ;\
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281 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
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282 add r2,r2,r3 ;\
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jlarmour
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diff changeset
283 ldr r3,=~0x3FF ;\
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284 and r2,r2,r3 ;\
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285 ldr r3,=(DRAM_LA_END+0x000FFFFF)&0xFFF00000 ;\
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286 ldr r4,=EXPANSION2_LA_START ;\
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287 ldr r5,=MMU_L1_TYPE_Fault ;\
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288 ldr r7,=MMU_SECTION_SIZE ;\
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289 10: str r5,[r1],#4 ;\
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290 add r3,r3,r7 ;\
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291 cmp r3,r4 ;\
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292 bne 10b ;\
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293 /* EXPANSION2, EXNAPSION3, PCMCIA0, PCMCIA1 */ ;\
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294 ldr r3,=EXPANSION2_LA_START ;\
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295 ldr r4,=SRAM_LA_START ;\
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296 ldr r5,=EXPANSION2_PA ;\
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297 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any ;\
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298 ldr r7,=MMU_SECTION_SIZE ;\
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299 10: orr r0,r5,r6 ;\
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300 str r0,[r1],#4 ;\
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301 add r5,r5,r7 ;\
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302 add r3,r3,r7 ;\
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diff changeset
303 cmp r3,r4 ;\
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304 bne 10b ;\
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305 /* SRAM */ ;\
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306 ldr r3,=SRAM_LA_START ;\
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307 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
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diff changeset
308 orr r4,r4,r2 ;\
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309 str r4,[r1],#4 ;\
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310 ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
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311 orr r4,r3,r4 ;\
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312 str r4,[r2],#4 ;\
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313 ldr r3,=SRAM_LA_START+MMU_PAGE_SIZE ;\
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314 ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE ;\
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315 ldr r5,=MMU_L2_TYPE_Fault ;\
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316 ldr r7,=MMU_PAGE_SIZE ;\
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317 10: str r5,[r2],#4 ;\
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318 add r3,r3,r7 ;\
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319 cmp r3,r4 ;\
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320 bne 10b ;\
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321 ldr r4,=IO_LA_START ;\
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322 ldr r5,=MMU_L1_TYPE_Fault ;\
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323 ldr r7,=MMU_SECTION_SIZE ;\
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324 20: str r5,[r1],#4 ;\
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325 add r3,r3,r7 ;\
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326 cmp r3,r4 ;\
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327 bne 20b ;\
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328 /* I/O */ ;\
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329 ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\
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330 add r2,r2,r3 ;\
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331 ldr r3,=~0x3FF ;\
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332 and r2,r2,r3 ;\
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333 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
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334 orr r4,r4,r2 ;\
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335 str r4,[r1],#4 ;\
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336 ldr r3,=IO_LA_START ;\
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337 ldr r4,=IO_LA_END ;\
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338 ldr r7,=MMU_PAGE_SIZE ;\
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339 ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All ;\
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340 10: str r5,[r2],#4 ;\
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341 add r5,r5,r7 ;\
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342 add r3,r3,r7 ;\
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343 cmp r3,r4 ;\
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344 bne 10b ;\
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345 ldr r4,=IO_LA_START+MMU_SECTION_SIZE ;\
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346 ldr r5,=MMU_L2_TYPE_Fault ;\
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347 ldr r7,=MMU_PAGE_SIZE ;\
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348 10: str r5,[r2],#4 ;\
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349 add r3,r3,r7 ;\
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350 cmp r3,r4 ;\
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351 bne 10b ;\
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352 ldr r4,=LCD_LA_START ;\
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353 ldr r5,=MMU_L1_TYPE_Fault ;\
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354 ldr r7,=MMU_SECTION_SIZE ;\
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355 20: str r5,[r1],#4 ;\
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356 add r3,r3,r7 ;\
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diff changeset
357 cmp r3,r4 ;\
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diff changeset
358 bne 20b ;\
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diff changeset
359 /* LCD Buffer & Unmapped DRAM (holes and all) */ ;\
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360 ldr r3,=LCD_LA_START ;\
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361 ldr r4,=ROM0_LA_START ;\
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362 ldr r5,=LCD_PA ;\
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363 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\
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364 ldr r7,=MMU_SECTION_SIZE ;\
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365 10: orr r0,r5,r6 ;\
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366 str r0,[r1],#4 ;\
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367 add r5,r5,r7 ;\
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368 add r3,r3,r7 ;\
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diff changeset
369 cmp r3,r4 ;\
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370 bne 10b ;\
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diff changeset
371 /* ROM0, ROM1 */ ;\
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372 ldr r3,=ROM0_LA_START ;\
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373 ldr r4,=ROM1_LA_END ;\
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374 ldr r5,=ROM0_PA ;\
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375 ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Cacheable ;\
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376 ldr r7,=MMU_SECTION_SIZE ;\
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diff changeset
377 10: orr r0,r5,r6 ;\
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diff changeset
378 str r0,[r1],#4 ;\
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diff changeset
379 add r5,r5,r7 ;\
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diff changeset
380 add r3,r3,r7 ;\
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diff changeset
381 cmp r3,r4 ;\
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diff changeset
382 bne 10b ;\
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diff changeset
383 /* Now initialize the MMU to use this new page table */ ;\
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384 MMU_INITIALIZE
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385
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386 #else
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387
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388 #define PLATFORM_SETUP1
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389 #endif
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390
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391
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392 /*---------------------------------------------------------------------------*/
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393 /* end of hal_platform_setup.h */
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394 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */