annotate packages/hal/cortexm/arch/current/src/hal_misc.c @ 3285:614e724c4b7a

Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
author vae
date Sat, 09 Mar 2013 17:13:06 +0000
parents abf5be1b8582
children
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1 /*==========================================================================
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2 //
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3 // hal_misc.c
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4 //
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5 // Cortex-M exception vectors
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 2008, 2012 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): nickg
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43 // Contributor(s): ilijak
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44 // Date: 2008-07-30
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //========================================================================
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49 */
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50
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51 #include <pkgconf/hal.h>
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52 #include <pkgconf/hal_cortexm.h>
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53 #ifdef CYGPKG_KERNEL
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54 #include <pkgconf/kernel.h>
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55 #endif
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56
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57 #include <cyg/infra/diag.h>
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58 #include <cyg/infra/cyg_type.h>
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59 #include <cyg/infra/cyg_trac.h> // tracing macros
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60 #include <cyg/infra/cyg_ass.h> // assertion macros
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61
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62 #include <cyg/hal/hal_arch.h> // HAL header
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63 #include <cyg/hal/hal_intr.h> // HAL header
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64 #include <cyg/hal/cortexm_regs.h> // Special Cortex-M asm instructions
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65 #include <cyg/hal/drv_api.h>
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66
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67 #ifdef CYGHWR_HAL_CORTEXM_FPU
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68 #include <cyg/hal/cortexm_fpu.h> // Optional Floating Point Unit
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69 #endif
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70
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71 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
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72 defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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73 #include <cyg/kernel/instrmnt.h>
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74 #endif
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75
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76 //==========================================================================
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77
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78 typedef cyg_uint32 cyg_isr(cyg_uint32 vector, CYG_ADDRWORD data);
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79
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80 //==========================================================================
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81 // External references
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82
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83 // VSRs in vectors.S
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84 __externC void hal_default_exception_vsr( void );
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85 __externC void hal_default_interrupt_vsr( void );
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86 __externC void hal_default_svc_vsr( void );
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87 __externC void hal_pendable_svc_vsr( void );
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88 __externC void hal_switch_state_vsr( void );
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89 #ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
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90 __externC void hal_usagefault_exception_vsr( void );
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91 #endif
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92
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93 // HAL and eCos functions
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94 __externC void hal_system_init( void );
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95 __externC void hal_variant_init( void );
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96 __externC void hal_platform_init( void );
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97 __externC void hal_ctrlc_isr_init( void );
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98 __externC void initialize_stub( void );
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99 __externC void cyg_hal_invoke_constructors( void );
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100 __externC void cyg_start( void );
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101 __externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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102 __externC void interrupt_end(cyg_uint32 isr_ret, CYG_ADDRWORD intr, HAL_SavedRegisters *regs );
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103
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104 // DATA and BSS locations
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105 __externC cyg_uint32 __ram_data_start;
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106 __externC cyg_uint32 __ram_data_end;
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107 __externC cyg_uint32 __rom_data_start;
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108 __externC cyg_uint32 __sram_data_start;
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109 __externC cyg_uint32 __sram_data_end;
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110 __externC cyg_uint32 __srom_data_start;
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111 __externC cyg_uint32 __bss_start;
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112 __externC cyg_uint32 __bss_end;
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113
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114 // Scheduler lock
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115 __externC volatile cyg_uint32 cyg_scheduler_sched_lock;
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116
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117 //==========================================================================
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118 // Interrupt tables
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119
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120 volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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121 volatile CYG_ADDRWORD hal_interrupt_data [CYGNUM_HAL_ISR_COUNT];
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122 volatile CYG_ADDRESS hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
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123
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124 //==========================================================================
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125 // Main entry point
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126 //
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127 // Enter here from reset via slot 1 of VSR table. The stack pointer is
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128 // already set to the value in VSR slot 0, usually the top of internal
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129 // SRAM.
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130
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131 void hal_reset_vsr( void )
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132 {
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133 // Call system init routine. This should do the minimum necessary
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134 // for the rest of the initialization to complete. For example set
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135 // up GPIO, the SRAM, power management etc. This routine is
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136 // usually supplied by the platform HAL. Calls to
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137 // hal_variant_init() and hal_platform_init() later will perform
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138 // the main initialization.
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139
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140 hal_system_init();
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141 #if defined CYGHWR_HAL_CORTEXM_FPU
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142 // Floating Point Unit is disabled after reset.
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143 // Enable it unless for LAZY context switching scheme.
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144 hal_init_fpu();
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
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145 #endif
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146
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147 // Initialize vector table in base of SRAM.
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148 {
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149 register int i;
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150
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151 #if !defined(CYG_HAL_STARTUP_RAM)
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152
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153 // Only install the exception vectors for non-RAM startup. For
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154 // RAM startup we want these to continue to point to the original
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155 // VSRs, which will belong to RedBoot or GDB stubs.
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diff changeset
156
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157 for( i = 2; i < 15; i++ )
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158 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
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diff changeset
159 #endif // !defined(CYG_HAL_STARTUP_RAM)
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160 // Always point SVC and PENDSVC vectors to our local versions
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161
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162 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
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163 hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
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164 #ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
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165 // Install UsageFault and HardFault to trap the FPU usage exceptions.
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diff changeset
166 HAL_VSR_SET(CYGNUM_HAL_VECTOR_USAGE_FAULT, hal_usagefault_exception_vsr, NULL);
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
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167 HAL_VSR_SET(CYGNUM_HAL_VECTOR_HARD_FAULT, hal_usagefault_exception_vsr, NULL);
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
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diff changeset
168 #endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
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169
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170 // For all startup type, redirect interrupt vectors to our VSR.
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171 for( i = CYGNUM_HAL_VECTOR_SYS_TICK ;
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9dd3ea41e5b6 * src/hal_misc.c (hal_reset_vsr): Ensure we only init intr vectors
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172 i < CYGNUM_HAL_VSR_MAX;
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173 i++ )
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174 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr;
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175 }
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176
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177 #if !defined(CYG_HAL_STARTUP_RAM)
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178
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179 // Ensure that the CPU will use the vector table we have just set
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180 // up.
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181
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182 # if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
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183
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184 // On M3 and M4 parts, the NVIC contains a vector table base register.
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185 // We program this to relocate the vector table base to the base of SRAM.
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186
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187 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
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188 CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
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189 CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
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190
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191 # else
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192
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193 # error Unknown SRAM/VECTAB remap mechanism
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194
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195 # endif
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196
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197 // Use SVC to switch our state to thread mode running on the PSP.
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198 // We don't need to do this for RAM startup since the ROM code
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199 // will have already done it.
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200
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201 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
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202
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996c69429643 * include/hal_intr.h (HAL_INTERRUPT_STACK_CALL_PENDING_DSRS):
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203 __asm__ volatile( "swi 0" );
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204
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205 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
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206
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207 #endif // !defined(CYG_HAL_STARTUP_RAM)
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208
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209 #if defined(CYG_HAL_STARTUP_ROM)
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210 // Relocate data from ROM to RAM
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211 {
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212 register cyg_uint32 *p, *q;
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213 for( p = &__ram_data_start, q = &__rom_data_start;
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214 p < &__ram_data_end;
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215 p++, q++ )
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216 *p = *q;
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217 }
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1a58c9c41c50 Apply patch to support SRAM initialization.
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218
1a58c9c41c50 Apply patch to support SRAM initialization.
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219 // Relocate data from ROM to SRAM
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220 {
1a58c9c41c50 Apply patch to support SRAM initialization.
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221 register cyg_uint32 *p, *q;
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222 for( p = &__sram_data_start, q = &__srom_data_start;
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223 p < &__sram_data_end;
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224 p++, q++ )
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225 *p = *q;
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226 }
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227 #endif
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228
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229 // Clear BSS
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230 {
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231 register cyg_uint32 *p;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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232 for( p = &__bss_start; p < &__bss_end; p++ )
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233 *p = 0;
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234 }
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235
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236 // Initialize interrupt vectors. Set the levels for all interrupts
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237 // to default values. Also set the default priorities of the
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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238 // system handlers: all exceptions maximum priority except SVC and
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239 // PendSVC which are lowest priority.
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240 {
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241 register int i;
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242
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243 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
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244 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
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245 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
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diff changeset
246
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247 hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
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diff changeset
248
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249 for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
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250 {
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251 hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
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252 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 );
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253 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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254 }
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255
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256 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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257 // Enable DebugMonitor exceptions. This is needed to enable single
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258 // step. This only has an effect if no external JTAG device is
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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259 // attached.
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260 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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261 CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
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262 cyg_uint32 demcr;
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263
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264 HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
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265 demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN;
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266 HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
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267 }
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268 #endif
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269
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diff changeset
270 #if !defined(CYG_HAL_STARTUP_RAM)
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271 // Enable Usage, Bus and Mem fault handlers. Do this for ROM and
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272 // JTAG startups. For RAM startups, this will have already been
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273 // done by the ROM monitor.
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274 {
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275 CYG_ADDRESS base = CYGARC_REG_NVIC_BASE;
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276 cyg_uint32 shcsr;
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277
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278 HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
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279 shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA;
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280 shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA;
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281 shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA;
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282 HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
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283 }
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284 #endif
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285
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286 // Call variant and platform init routines
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287 hal_variant_init();
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288 hal_platform_init();
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289
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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290 // Start up the system clock
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291 HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
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292
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293 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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294
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295 initialize_stub();
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296
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297 #endif
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298
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299 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
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300 defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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301
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302 hal_ctrlc_isr_init();
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303
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304 #endif
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305
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306 // Run through static constructors
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307 cyg_hal_invoke_constructors();
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308
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309 // Finally call into application
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310 cyg_start();
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311 for(;;);
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312 }
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313
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314 //==========================================================================
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315 // Handle Exceptions
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316 //
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317 // Exceptions are passed here from the initial VSR. We pass the
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318 // exception on to GDB stubs or the kernel as appropriate.
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319
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320 __externC void __handle_exception (void);
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321
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322 __externC HAL_SavedRegisters *_hal_registers;
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323 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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324 __externC void* volatile __mem_fault_handler;
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325 #endif
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326
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327 void hal_deliver_exception( HAL_SavedRegisters *regs )
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328 {
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329 // Special case handler for code which has chosen to take care
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330 // of data exceptions (i.e. code which expects them to happen)
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331 // This is common in discovery code, e.g. checking for a particular
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332 // device which may generate an exception when probing if the
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333 // device is not present
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334
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335 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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336 if (__mem_fault_handler )
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337 {
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338 regs->u.exception.pc = (unsigned long)__mem_fault_handler;
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339 return; // Caught an exception inside stubs
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340 }
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341 #endif
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342
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343 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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344
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345 _hal_registers = regs;
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346 __handle_exception();
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347
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348 #elif defined(CYGPKG_KERNEL_EXCEPTIONS)
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349
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350 cyg_hal_deliver_exception( regs->u.exception.vector, (CYG_ADDRWORD)regs );
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351
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352 #else
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353
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354 CYG_FAIL("Exception!!!");
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355
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356 #endif
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357 }
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358
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359 //==========================================================================
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360 // Handle Interrupts
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361 //
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362 // Interrupts are passed here from the low-level VSR in vectors.S. We
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363 // look up the ISR in the interrupt table, call it and if it requests
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364 // it, post a DSR. If necessary we also then cause the pendable SVC to
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365 // be requested.
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366 //
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367 // This function is also callable from ISR springboards that decode
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368 // additional interrupts via external controllers to deliver an
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369 // interrupt to a secondary vector.
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370
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371 void hal_deliver_interrupt( cyg_uint32 vector )
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372 {
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373 register cyg_uint32 isr_result;
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374 register cyg_isr *isr;
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375 cyg_bool pendsvc = false;
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376
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377 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
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378 defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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379 CYG_INSTRUMENT_INTR(RAISE, vector, 0);
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380 #endif
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381 isr = (cyg_isr *)hal_interrupt_handlers[vector];
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382
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383 // Call the ISR
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384 isr_result = isr( vector, hal_interrupt_data[vector] );
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385
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386
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387 #if !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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388 // If the ISR has returned the CALL_DSR bit, post the DSR and set
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389 // the pendable SVC exception pending.
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390 if( isr_result & CYG_ISR_CALL_DSR )
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391 {
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392 cyg_interrupt_post_dsr( hal_interrupt_objects[vector] );
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393
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394 // Post the pendable SVC to call interrupt_end(). But only if
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395 // the scheduler lock is currently zero. If it is non zero
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396 // then interrupt_end will do nothing useful, so avoid calling
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397 // it.
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398 if( cyg_scheduler_sched_lock == 0 )
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399 pendsvc = true;
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400 }
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401 #else
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402 // When chaining we don't know here whether the nested interrupt
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403 // has posted a DSR, so we have to run interrupt_end() regardless.
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404 // However, the same considerations as above regarding the
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405 // scheduler lock still apply.
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406 if( cyg_scheduler_sched_lock == 0 )
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407 pendsvc = true;
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408 #endif
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409
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410 // Post the pendable SVC if required.
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411 if( pendsvc )
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412 {
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413 cyg_uint32 icsr;
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414 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
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415 icsr |= CYGARC_REG_NVIC_ICSR_PENDSVSET;
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416 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
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417 }
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418 }
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419
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420 //==========================================================================
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421 // Call interrupt_end()
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422 //
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423 // This is called on the thread stack as a result of the pendable
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424 // SVC. interrupt_end() decrements the scheduler lock, calls DSRs and
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425 // optionally switches thread context. So before calling, we must
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426 // increment the lock. The actual interrupt end processing has already
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427 // been done above in hal_default_interrupt_vsr1(), so the arguments
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428 // are zero.
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429
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430 __externC void hal_interrupt_end( void )
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431 {
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432 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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433 cyg_scheduler_sched_lock++;
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434 #endif
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435
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436 interrupt_end(0,0,0);
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437 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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438
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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439 //==========================================================================
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440 // Interrupt masking and configuration
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441
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442 #ifndef HAL_VAR_INTERRUPT_MASK
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443 #define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT
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444 #define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT
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445 #define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT
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diff changeset
446 #define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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447 #define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) CYG_EMPTY_STATEMENT
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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448 #endif
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
449
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
450 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
451
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
452 __externC void hal_interrupt_mask( cyg_uint32 vector )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
453 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
diff changeset
454 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
diff changeset
455 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
diff changeset
456 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_CER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
457 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
458 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
459 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
460 cyg_uint32 csr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
461 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
462 csr &= ~CYGARC_REG_SYSTICK_CSR_TICKINT;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
diff changeset
463 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
464 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
465 HAL_VAR_INTERRUPT_MASK( vector );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
diff changeset
466 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
467
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
468 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
469
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
470 __externC void hal_interrupt_unmask( cyg_uint32 vector )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
471 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
472 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
473 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
474 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
475 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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476 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
477 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
478 cyg_uint32 csr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
479 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
480 csr |= CYGARC_REG_SYSTICK_CSR_TICKINT;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
481 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
482 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
483 HAL_VAR_INTERRUPT_UNMASK( vector );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
484 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
485
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
486 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
487
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
488 __externC void hal_interrupt_acknowledge( cyg_uint32 vector )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
489 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
490 HAL_VAR_INTERRUPT_ACKNOWLEDGE( vector );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
491 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
492
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
493 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
494
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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diff changeset
495 __externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
496 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
497 HAL_VAR_INTERRUPT_CONFIGURE( vector, level, up );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
498 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
499
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
500 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
501
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
502 __externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
503 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
504 cyg_uint32 l = (level)+CYGNUM_HAL_CORTEXM_PRIORITY_MAX;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
505 if( l > 0xFF ) l = 0xFF; /* clamp to 0xFF */
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
506 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
507 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
508 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
509 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
510 l );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
511 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
512 else if ( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
513 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
514 cyg_uint32 shpr2;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
515 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
516 shpr2 &= ~0xFF000000;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
517 shpr2 |= (l)<<24;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
518 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
519 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
520 HAL_VAR_INTERRUPT_SET_LEVEL( vector, level );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
521 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
522
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
523 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
524 // Microsecond delay
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
525 //
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
526 // The system RTC is set up to tick at 1MHz so all we need to do here
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
527 // is count ticks.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
528
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
529 __externC void hal_delay_us( cyg_int32 us )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
530 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
531 cyg_uint32 t0, t1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
532
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
533 HAL_CLOCK_READ( &t0 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
534 while ( us > 0 )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
535 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
536 HAL_CLOCK_READ( &t1 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
537 if( t1 < t0 )
2589
9da21501bc5b * include/hal_intr.h:
nickg
parents: 2580
diff changeset
538 us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0);
9da21501bc5b * include/hal_intr.h:
nickg
parents: 2580
diff changeset
539 else
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
540 us -= t1 - t0;
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
541 t0 = t1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
542 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
543 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
544
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
545 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
546 // C++ support - run initial constructors
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
547
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
548 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
549 cyg_bool cyg_hal_stop_constructors;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
550 #endif
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
551
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
552 typedef void (*pfunc) (void);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
553
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
554 extern pfunc __init_array_start__[];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
555 extern pfunc __init_array_end__[];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
556 #define CONSTRUCTORS_START (__init_array_start__[0])
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
557 #define CONSTRUCTORS_END (__init_array_end__)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
558 #define NEXT_CONSTRUCTOR(c) ((c)++)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
559
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
560 void
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
561 cyg_hal_invoke_constructors (void)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
562 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
563 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
564 static pfunc *p = &CONSTRUCTORS_START;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
565
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
566 cyg_hal_stop_constructors = 0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
567 for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
568 (*p)();
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
569 if (cyg_hal_stop_constructors) {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
570 NEXT_CONSTRUCTOR(p);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
571 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
572 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
573 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
574 #else
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
575 pfunc *p;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
576
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
577 for (p = &CONSTRUCTORS_START; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p))
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
578 (*p)();
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
579 #endif
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
580 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
581
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
582 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
583 // Architecture default ISR
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
584
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
585 __externC cyg_uint32
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
586 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
587 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
588 CYG_TRACE1(true, "Interrupt: %d", vector);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
589
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
590 CYG_FAIL("Spurious Interrupt!!!");
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
591
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
592 return 0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
593 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
594
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
595 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
596 // GDB support
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
597 //
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
598 // These functions translate between HAL saved contexts and GDB
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
599 // register dumps.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
600
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
601 __externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
602 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
603 int i;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
604
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
605 switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
606 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
607 case HAL_SAVEDREGISTERS_THREAD:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
608 for( i = 0; i < 13; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
609 gdbreg->gpr[i] = regs->u.thread.r[i];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
610 gdbreg->gpr[13] = regs->u.thread.sp;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
611 gdbreg->gpr[14] = regs->u.thread.pc;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
612 gdbreg->gpr[15] = regs->u.thread.pc;
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
613 gdbreg->xpsr = 0x01000000;
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
614
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
615 GDB_STUB_SAVEDREG_FPU_THREAD_GET(gdbreg, regs);
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
616 break;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
617
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
618 case HAL_SAVEDREGISTERS_EXCEPTION:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
619 gdbreg->gpr[0] = regs->u.exception.r0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
620 gdbreg->gpr[1] = regs->u.exception.r1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
621 gdbreg->gpr[2] = regs->u.exception.r2;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
622 gdbreg->gpr[3] = regs->u.exception.r3;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
623 for( i = 0; i < 8; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
624 gdbreg->gpr[i+4] = regs->u.exception.r4_11[i];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
625 gdbreg->gpr[12] = regs->u.exception.r12;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
626 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.exception);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
627 gdbreg->gpr[14] = regs->u.exception.lr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
628 gdbreg->gpr[15] = regs->u.exception.pc;
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
629 gdbreg->xpsr = regs->u.exception.psr;
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
630 #ifdef CYGSEM_HAL_DEBUG_FPU
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
631 GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(gdbreg, regs);
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
632 #endif
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
633 break;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
634
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
635 case HAL_SAVEDREGISTERS_INTERRUPT:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
636 gdbreg->gpr[0] = regs->u.interrupt.r0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
637 gdbreg->gpr[1] = regs->u.interrupt.r1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
638 gdbreg->gpr[2] = regs->u.interrupt.r2;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
639 gdbreg->gpr[3] = regs->u.interrupt.r3;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
640 gdbreg->gpr[12] = regs->u.interrupt.r12;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
641 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.interrupt);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
642 gdbreg->gpr[14] = regs->u.interrupt.lr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
643 gdbreg->gpr[15] = regs->u.interrupt.pc;
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
644 gdbreg->xpsr = regs->u.interrupt.psr;
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
645 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
646 }
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
647 #ifdef CYGARC_CORTEXM_GDB_REG_FPA
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
648 // Clear FP state, which we don't use
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
649 {
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
650 cyg_uint32 *p = gdbreg->f0;
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
651 for( i = 0; i < (8*3+1); i++ )
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
652 p[i] = 0;
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
653 }
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
654 #endif
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
655 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
656
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
657 __externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
658 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
659 int i;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
660
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
661 switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
662 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
663 case HAL_SAVEDREGISTERS_THREAD:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
664 for( i = 0; i < 13; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
665 regs->u.thread.r[i] = gdbreg->gpr[i];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
666 regs->u.thread.sp = gdbreg->gpr[13];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
667 regs->u.thread.pc = gdbreg->gpr[14];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
668 regs->u.thread.pc = gdbreg->gpr[15];
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
669
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
670 GDB_STUB_SAVEDREG_FPU_THREAD_SET(gdbreg, regs);
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
671 break;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
672
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
673 case HAL_SAVEDREGISTERS_EXCEPTION:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
674 regs->u.exception.r0 = gdbreg->gpr[0];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
675 regs->u.exception.r1 = gdbreg->gpr[1];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
676 regs->u.exception.r2 = gdbreg->gpr[2];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
677 regs->u.exception.r3 = gdbreg->gpr[3];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
678 for( i = 0; i < 8; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
679 regs->u.exception.r4_11[i] = gdbreg->gpr[i+4];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
680 regs->u.exception.r12 = gdbreg->gpr[12];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
681 regs->u.exception.lr = gdbreg->gpr[14];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
682 regs->u.exception.pc = gdbreg->gpr[15];
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
683 regs->u.exception.psr = gdbreg->xpsr;
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
684 #ifdef CYGSEM_HAL_DEBUG_FPU
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
685 GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(gdbreg, regs);
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
686 #endif
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
687 break;
3234
abf5be1b8582 Whitespace cleanup
vae
parents: 3215
diff changeset
688
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
689 case HAL_SAVEDREGISTERS_INTERRUPT:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
690 regs->u.interrupt.r0 = gdbreg->gpr[0];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
691 regs->u.interrupt.r1 = gdbreg->gpr[1];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
692 regs->u.interrupt.r2 = gdbreg->gpr[2];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
693 regs->u.interrupt.r3 = gdbreg->gpr[3];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
694 regs->u.interrupt.r12 = gdbreg->gpr[12];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
695 regs->u.interrupt.lr = gdbreg->gpr[14];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
696 regs->u.interrupt.pc = gdbreg->gpr[15];
3285
614e724c4b7a Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
vae
parents: 3234
diff changeset
697 regs->u.interrupt.psr = gdbreg->xpsr;
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
698 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
699 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
700 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
701
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
702 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
703 // When compiling C++ code with static objects the compiler
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
704 // inserts a call to __cxa_atexit() with __dso_handle as one of the
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
705 // arguments. __cxa_atexit() would normally be provided by glibc, and
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
706 // __dso_handle is part of crtstuff.c. eCos applications
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
707 // are linked rather differently, so either a differently-configured
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
708 // compiler is needed or dummy versions of these symbols should be
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
709 // provided. If these symbols are not actually used then providing
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
710 // them is still harmless, linker garbage collection will remove them.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
711
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
712 void
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
713 __cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
714 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
715 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
716
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
717 void* __dso_handle = (void*) &__dso_handle;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
718
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
719 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
720 // EOF hal_misc.c