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annotate packages/hal/mips/tx49/current/include/var_cache.h @ 143:6b5f480c6929 ecos-sw-2000-12-08

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Merge from eCos master repository on 2000-12-08-02:09:36-GMT
author jlarmour
date Fri, 08 Dec 2000 03:30:06 +0000
parents d2f49caf9e38
children e0c0827131d1
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors:nickg, jskov
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39 // Date: 2000-05-09
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/imp_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <pkgconf/hal.h>
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53 #include <cyg/infra/cyg_type.h>
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54
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55 #include <cyg/hal/mips-regs.h>
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56
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57 #include <cyg/hal/plf_cache.h>
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58
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59 //=============================================================================
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60 // Toshiba TX4955
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61
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62 #ifdef CYGPKG_HAL_MIPS_TX4955
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63
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64 //-----------------------------------------------------------------------------
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65 // Cache dimensions
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66
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67 // Data cache
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68 #define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
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69 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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70 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
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71
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72 // Instruction cache
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73 #define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
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74 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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75 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
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76
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77 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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78 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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79
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80 #define HAL_MIPS_CACHE_INSN_USES_LSB
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81
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82 //-----------------------------------------------------------------------------
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83 // Cache controls
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84
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85 // Register $16 is Config register (controls cache state)
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86
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87 // Config Register fields
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88 #define CYGARC_REG_CONFIG_ICE 0x00020000 // Instruction cache enable
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89 #define CYGARC_REG_CONFIG_DCE 0x00010000 // Data cache enable
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90
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91
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92 //-----------------------------------------------------------------------------
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93 // Global control of data cache
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94
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95 // Enable the data cache
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96 // This uses a bit in the config register, which is TX49 specific.
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97 #define HAL_DCACHE_ENABLE_DEFINED
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98 #define HAL_DCACHE_ENABLE() \
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99 CYG_MACRO_START \
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100 cyg_uint32 tmp; \
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101 asm volatile ("mfc0 %0,$16;" \
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102 "and %0,%0,%1;" \
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103 "mtc0 %0,$16;" \
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104 : "=&r" (tmp) \
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105 : "r" (~CYGARC_REG_CONFIG_DCE) \
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106 ); \
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107 CYG_MACRO_END
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108
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109 // Disable the data cache
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110 #define HAL_DCACHE_DISABLE_DEFINED
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111 #define HAL_DCACHE_DISABLE() \
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112 CYG_MACRO_START \
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113 cyg_uint32 tmp; \
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114 asm volatile ("mfc0 %0,$16;" \
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115 "or %0,%0,%1;" \
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116 "mtc0 %0,$16;" \
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117 : "=&r" (tmp) \
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118 : "r" (CYGARC_REG_CONFIG_DCE) \
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119 ); \
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120 CYG_MACRO_END
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121
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122 #define HAL_DCACHE_IS_ENABLED_DEFINED
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123 #define HAL_DCACHE_IS_ENABLED(_state_) \
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124 CYG_MACRO_START \
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125 cyg_uint32 _cstate_; \
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126 asm volatile ( "mfc0 %0,$16\n" \
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127 : "=r"(_cstate_) \
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128 ); \
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129 if( _cstate_ & CYGARC_REG_CONFIG_DCE) \
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130 _state_ = 0; \
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131 else \
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132 _state_ = 1; \
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133 CYG_MACRO_END
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134
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135 // Architecture HAL defines other operations
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136
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137
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138 //-----------------------------------------------------------------------------
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139 // Global control of Instruction cache
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140
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141 // Enable the instruction cache
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142 #define HAL_ICACHE_ENABLE_DEFINED
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143 #define HAL_ICACHE_ENABLE() \
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144 CYG_MACRO_START \
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145 cyg_uint32 tmp; \
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146 asm volatile ("mfc0 %0,$16;" \
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147 "and %0,%0,%1;" \
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148 "mtc0 %0,$16;" \
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149 : "=&r" (tmp) \
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150 : "r" (~CYGARC_REG_CONFIG_ICE) \
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151 ); \
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152 CYG_MACRO_END
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153
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154 // Disable the instruction cache
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155 #define HAL_ICACHE_DISABLE_DEFINED
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156 #define HAL_ICACHE_DISABLE() \
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157 CYG_MACRO_START \
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158 cyg_uint32 tmp; \
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159 asm volatile ("mfc0 %0,$16;" \
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160 "or %0,%0,%1;" \
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161 "mtc0 %0,$16;" \
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162 : "=&r" (tmp) \
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163 : "r" (CYGARC_REG_CONFIG_ICE) \
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164 ); \
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165 CYG_MACRO_END
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166
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167 #define HAL_ICACHE_IS_ENABLED_DEFINED
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168 #define HAL_ICACHE_IS_ENABLED(_state_) \
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169 CYG_MACRO_START \
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170 cyg_uint32 _cstate_; \
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171 asm volatile ( "mfc0 %0,$16\n" \
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172 : "=r"(_cstate_) \
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173 ); \
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174 if( _cstate_ & CYGARC_REG_CONFIG_ICE) \
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175 _state_ = 0; \
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176 else \
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177 _state_ = 1; \
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178 CYG_MACRO_END
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179
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180 // TX49 cache instruction must not affect the line it executes out of,
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181 // so disable instruction cache before invalidating it.
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182 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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183 #define HAL_ICACHE_INVALIDATE_ALL() \
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184 CYG_MACRO_START \
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185 register CYG_ADDRESS _baddr_ = 0x80000000; \
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186 register CYG_ADDRESS _addr_ = 0x80000000; \
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187 register CYG_WORD _state_; \
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188 _HAL_ASM_SET_MIPS_ISA(3); \
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189 HAL_ICACHE_IS_ENABLED( _state_ ); \
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190 HAL_ICACHE_DISABLE(); \
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191 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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192 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
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193 if( _state_ ) HAL_ICACHE_ENABLE(); \
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194 _HAL_ASM_SET_MIPS_ISA(0); \
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195 CYG_MACRO_END
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196
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197 // Architecture HAL defines other operations
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198
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199 #endif // CYGPKG_HAL_MIPS_TX4955
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200
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201
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202 //-----------------------------------------------------------------------------
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203 #endif // ifndef CYGONCE_VAR_CACHE_H
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204 // End of var_cache.h