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annotate packages/hal/sh/arch/current/include/arch.inc @ 139:79d72068f491 ecos-sw-2000-11-24

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Merge from eCos master repository on 2000-11-24-16:52:55-GMT
author jlarmour
date Fri, 24 Nov 2000 17:42:47 +0000
parents 289bf90c6a9b
children e0c0827131d1
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1 ##=============================================================================
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2 ##
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3 ## arch.inc
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4 ##
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5 ## SH architecture assembler header file
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6 ##
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7 ##=============================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.1 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://www.redhat.com/
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 ##=============================================================================
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32 #######DESCRIPTIONBEGIN####
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33 ##
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34 ## Author(s): jskov
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35 ## Contributors:jskov
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36 ## Date: 2000-02-28
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37 ## Purpose: SH definitions.
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38 ## Description: This file contains various definitions and macros that are
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39 ## useful for writing assembly code for the SH
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40 ## It also includes the variant/platform assembly header file.
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41 ## Usage:
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42 ## #include <cyg/hal/arch.inc>
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43 ## ...
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44 ##
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45 ##
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46 ######DESCRIPTIONEND####
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47 ##
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48 ##=============================================================================
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49
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50 #include <cyg/hal/basetype.h>
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51 #include <cyg/hal/sh_regs.h>
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52
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53 ##-----------------------------------------------------------------------------
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54 ## SH entry definitions. This allows _ prefixing to change by modifying
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55 ## the CYG_LABEL_DEFN macro.
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56
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57 #define FUNC_START(name) \
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58 .type CYG_LABEL_DEFN(name),@function; \
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59 .globl CYG_LABEL_DEFN(name); \
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60 CYG_LABEL_DEFN(name):
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61
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62 #define FUNC_END(name) \
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63 .globl CYG_LABEL_DEFN(name); \
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64 CYG_LABEL_DEFN(name):
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65
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66 #define SYM_DEF(name) \
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67 .globl CYG_LABEL_DEFN(name); \
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68 CYG_LABEL_DEFN(name):
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69
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70 #define SYM_PTR_REF(name) \
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71 .globl CYG_LABEL_DEFN(name); \
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72 $##name: .long CYG_LABEL_DEFN(name)
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73
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74 # We need this macro because the SH assembler is lacking the nice
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75 # inline immediate constant feature of the ARM assembler. So we have
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76 # to define constants ourselves, and sometimes we need more than one of
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77 # the same type. This allows the symbols used to change.
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78 #define SYM_PTR_REFn(name,n) \
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79 .globl CYG_LABEL_DEFN(name); \
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80 $##name##n: .long CYG_LABEL_DEFN(name)
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81
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82 #include <cyg/hal/platform.inc>
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83
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84 ##-----------------------------------------------------------------------------
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85 ## SH FPU state handling
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86 ## Empty for now.
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87
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88 .macro hal_fpu_save regs
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89 .endm
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90
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91 .macro hal_fpu_load regs
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92 .endm
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93
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94 ##-----------------------------------------------------------------------------
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95 ## CPU specific macros. These provide a common assembler interface to
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96 ## operations that may have CPU specific implementations on different
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97 ## variants of the architecture.
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98
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99 # Enable interrupts
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100 .macro hal_cpu_int_enable t1,t2
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101 stc sr,\t1
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102 mov #CYGARC_REG_SR_IMASK>>1,\t2
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103 shll \t2
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104 not \t2,\t2
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105 and \t2,\t1
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106 ldc \t1,sr
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107 .endm
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108
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109 # Disable interrupts
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110 .macro hal_cpu_int_disable t1,t2
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111 stc sr,\t1
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112 mov #CYGARC_REG_SR_IMASK>>1,\t2
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113 shll \t2
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114 or \t2,\t1
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115 ldc \t1,sr
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116 .endm
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117
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118 # Merge the interrupt enable state of the status register in
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119 # \sr with the current sr.
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120 .macro hal_cpu_int_merge sr,t1,t2
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121 stc sr,\t1
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122 mov #CYGARC_REG_SR_IMASK>>1,\t2
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123 shll \t2
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124 and \t2,\sr
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125 not \t2,\t2
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126 and \t2,\t1
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127 or \sr,\t1
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128 ldc \t1,sr
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129 .endm
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130
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131 #------------------------------------------------------------------------------
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
132 # end of arch.inc