Mercurial > nand-ecoscentric
annotate packages/hal/mips/arch/current/src/mips-stub.c @ 50:a0774359f013 ecos-sw-1999-11-02
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
| author | jlarmour |
|---|---|
| date | Tue, 02 Nov 1999 20:57:07 +0000 |
| parents | 4741a3c3496a |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 0 | 1 /* mips-stub.c - helper functions for stub, generic to all MIPS processors |
| 2 * | |
| 2 | 3 * Copyright (c) 1998,1999 Cygnus Solutions |
| 0 | 4 * |
| 5 * The authors hereby grant permission to use, copy, modify, distribute, | |
| 6 * and license this software and its documentation for any purpose, provided | |
| 7 * that existing copyright notices are retained in all copies and that this | |
| 8 * notice is included verbatim in any distributions. No written agreement, | |
| 9 * license, or royalty fee is required for any of the authorized uses. | |
| 10 * Modifications to this software may be copyrighted by their authors | |
| 11 * and need not follow the licensing terms described here, provided that | |
| 12 * the new terms are clearly indicated on the first page of each file where | |
| 13 * they apply. | |
| 14 */ | |
| 15 | |
| 16 #include <stddef.h> | |
| 17 | |
| 2 | 18 #include <pkgconf/hal.h> |
| 0 | 19 |
| 20 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 21 | |
| 2 | 22 #include <cyg/hal/hal_stub.h> |
| 0 | 23 |
| 2 | 24 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
| 25 #include <cyg/hal/mips-regs.h> | |
| 0 | 26 |
| 2 | 27 #include <cyg/hal/hal_arch.h> |
| 28 #include <cyg/hal/mips_opcode.h> | |
| 0 | 29 |
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30 typedef unsigned long t_inst; |
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31 |
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32 /*---------------------------------------------------------------------- |
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33 * Asynchronous interrupt support |
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34 */ |
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35 |
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36 static struct |
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37 { |
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38 t_inst *targetAddr; |
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39 t_inst savedInstr; |
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40 } asyncBuffer; |
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41 |
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42 /* Called to asynchronously interrupt a running program. |
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43 Must be passed address of instruction interrupted. |
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44 This is typically called in response to a debug port |
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45 receive interrupt. |
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46 */ |
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47 |
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48 void |
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49 install_async_breakpoint(void *epc) |
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50 { |
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51 long gp_save; |
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52 |
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53 /* This may be called from a separately linked program, |
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54 so we need to save and restore the incoming gp register |
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55 and setup our stub local gp register. |
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56 Alternatively, we could skip this foolishness if we |
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57 compiled libstub with "-G 0". */ |
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58 |
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59 __asm__ volatile ( "move %0,$28\n" |
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60 ".extern _gp\n" |
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61 "la $28,_gp\n" |
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62 : "=r" (gp_save) ); |
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63 |
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64 asyncBuffer.targetAddr = epc; |
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65 asyncBuffer.savedInstr = *(t_inst *)epc; |
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66 *(t_inst *)epc = *(t_inst *)_breakinst; |
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67 __instruction_cache(CACHE_FLUSH); |
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68 __data_cache(CACHE_FLUSH); |
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69 |
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70 __asm__ volatile ( "move $28,%0\n" :: "r"(gp_save) ); |
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71 } |
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72 |
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73 /*--------------------------------------------------------------------*/ |
| 0 | 74 /* Given a trap value TRAP, return the corresponding signal. */ |
| 75 | |
| 76 int __computeSignal (unsigned int trap_number) | |
| 77 { | |
| 78 switch (trap_number) | |
| 79 { | |
| 80 case EXC_INT: | |
| 81 /* External interrupt */ | |
| 82 return SIGINT; | |
| 83 | |
| 84 case EXC_RI: | |
| 85 /* Reserved instruction */ | |
| 86 case EXC_CPU: | |
| 87 /* Coprocessor unusable */ | |
| 88 return SIGILL; | |
| 89 | |
| 90 case EXC_BP: | |
| 91 /* Break point */ | |
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92 if (asyncBuffer.targetAddr != NULL) |
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93 { |
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94 /* BP installed by serial driver to stop running program */ |
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95 *asyncBuffer.targetAddr = asyncBuffer.savedInstr; |
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96 __instruction_cache(CACHE_FLUSH); |
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97 __data_cache(CACHE_FLUSH); |
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98 asyncBuffer.targetAddr = NULL; |
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99 return SIGINT; |
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100 } |
| 0 | 101 return SIGTRAP; |
| 102 | |
| 103 case EXC_OVF: | |
| 104 /* Arithmetic overflow */ | |
| 105 case EXC_TRAP: | |
| 106 /* Trap exception */ | |
| 107 case EXC_FPE: | |
| 108 /* Floating Point Exception */ | |
| 109 return SIGFPE; | |
| 110 | |
| 111 case EXC_IBE: | |
| 112 /* Bus error (Ifetch) */ | |
| 113 case EXC_DBE: | |
| 114 /* Bus error (data load or store) */ | |
| 115 return SIGBUS; | |
| 116 | |
| 117 case EXC_MOD: | |
| 118 /* TLB modification exception */ | |
| 119 case EXC_TLBL: | |
| 120 /* TLB miss (Load or Ifetch) */ | |
| 121 case EXC_TLBS: | |
| 122 /* TLB miss (Store) */ | |
| 123 case EXC_ADEL: | |
| 124 /* Address error (Load or Ifetch) */ | |
| 125 case EXC_ADES: | |
| 126 /* Address error (Store) */ | |
| 127 return SIGSEGV; | |
| 128 | |
| 129 case EXC_SYS: | |
| 130 /* System call */ | |
| 131 return SIGSYS; | |
| 132 | |
| 133 default: | |
| 134 return SIGTERM; | |
| 135 } | |
| 136 } | |
| 137 | |
| 138 /* Return the trap number corresponding to the last-taken trap. */ | |
| 139 | |
| 140 int __get_trap_number (void) | |
| 141 { | |
| 142 return (get_register (CAUSE) & CAUSE_EXCMASK) >> CAUSE_EXCSHIFT; | |
| 143 } | |
| 144 | |
| 145 /* Set the currently-saved pc register value to PC. This also updates NPC | |
| 146 as needed. */ | |
| 147 | |
| 148 void set_pc (target_register_t pc) | |
| 149 { | |
| 150 put_register (PC, pc); | |
| 151 } | |
| 152 | |
| 153 | |
| 154 /*---------------------------------------------------------------------- | |
| 155 * Single-step support | |
| 156 */ | |
| 157 | |
| 158 /* Saved instruction data for single step support. */ | |
| 159 | |
| 160 static struct | |
| 161 { | |
| 162 t_inst *targetAddr; | |
| 163 t_inst savedInstr; | |
| 164 } instrBuffer; | |
| 165 | |
| 166 | |
| 167 /* Set things up so that the next user resume will execute one instruction. | |
| 168 This may be done by setting breakpoints or setting a single step flag | |
| 169 in the saved user registers, for example. */ | |
| 170 | |
| 2 | 171 void __single_step (void) |
| 0 | 172 { |
| 173 InstFmt inst; | |
| 174 t_inst *pc = (t_inst *) get_register (PC); | |
| 175 | |
| 2 | 176 instrBuffer.targetAddr = pc + 1; /* set default */ |
| 0 | 177 |
| 2 | 178 inst.word = *pc; /* read the next instruction */ |
| 0 | 179 |
| 180 //diag_printf("pc %08x %08x\n",pc,inst.word); | |
| 181 | |
| 182 switch (inst.RType.op) { /* override default if branch */ | |
| 183 case OP_SPECIAL: | |
| 184 switch (inst.RType.func) { | |
| 185 case OP_JR: | |
| 186 case OP_JALR: | |
| 187 instrBuffer.targetAddr = (t_inst *) get_register (inst.RType.rs); | |
| 188 break; | |
| 189 }; | |
| 190 break; | |
| 191 | |
| 192 case OP_REGIMM: | |
| 193 switch (inst.IType.rt) { | |
| 194 case OP_BLTZ: | |
| 195 case OP_BLTZL: | |
| 196 case OP_BLTZAL: | |
| 197 case OP_BLTZALL: | |
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198 if ((int)get_register (inst.IType.rs) < 0 ) |
| 0 | 199 instrBuffer.targetAddr = |
| 200 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 201 + (get_register (PC) + 4)); | |
| 202 else | |
| 203 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 204 break; | |
| 205 case OP_BGEZ: | |
| 206 case OP_BGEZL: | |
| 207 case OP_BGEZAL: | |
| 208 case OP_BGEZALL: | |
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209 if ((int)get_register (inst.IType.rs) >= 0 ) |
| 0 | 210 instrBuffer.targetAddr = |
| 211 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 212 + (get_register (PC) + 4)); | |
| 213 else | |
| 214 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 215 break; | |
| 216 }; | |
| 217 break; | |
| 218 | |
| 219 case OP_J: | |
| 220 case OP_JAL: | |
| 221 instrBuffer.targetAddr = | |
| 222 (t_inst *)((inst.JType.target<<2) | |
| 2 | 223 + ((get_register (PC) + 4)&0xf0000000)); |
| 0 | 224 break; |
| 225 | |
| 226 case OP_BEQ: | |
| 227 case OP_BEQL: | |
| 228 if (get_register (inst.IType.rs) == get_register (inst.IType.rt)) | |
| 229 instrBuffer.targetAddr = | |
| 230 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 2 | 231 + (get_register (PC) + 4)); |
| 0 | 232 else |
| 233 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 234 break; | |
| 235 case OP_BNE: | |
| 236 case OP_BNEL: | |
| 237 if (get_register (inst.IType.rs) != get_register (inst.IType.rt)) | |
| 238 instrBuffer.targetAddr = | |
| 239 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 2 | 240 + (get_register (PC) + 4)); |
| 0 | 241 else |
| 242 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 243 break; | |
| 244 case OP_BLEZ: | |
| 245 case OP_BLEZL: | |
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246 if ((int)get_register (inst.IType.rs) <= 0) |
| 0 | 247 instrBuffer.targetAddr = |
| 248 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4)); | |
| 249 else | |
| 250 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 251 break; | |
| 252 case OP_BGTZ: | |
| 253 case OP_BGTZL: | |
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254 if ((int)get_register (inst.IType.rs) > 0) |
| 0 | 255 instrBuffer.targetAddr = |
| 256 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4)); | |
| 257 else | |
| 258 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 259 break; | |
| 260 | |
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261 #ifdef CYGHWR_HAL_MIPS_FPU |
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262 |
| 0 | 263 case OP_COP1: |
| 264 if (inst.RType.rs == OP_BC) | |
| 265 switch (inst.RType.rt) { | |
| 266 case COPz_BCF: | |
| 267 case COPz_BCFL: | |
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268 if (get_register (FCR31) & FCR31_C) |
| 0 | 269 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); |
| 270 else | |
| 271 instrBuffer.targetAddr = | |
| 272 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 273 + (get_register (PC) + 4)); | |
| 274 break; | |
| 275 case COPz_BCT: | |
| 276 case COPz_BCTL: | |
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277 if (get_register (FCR31) & FCR31_C) |
| 0 | 278 instrBuffer.targetAddr = |
| 279 (t_inst *)(((signed short)inst.IType.imm<<2) | |
| 280 + (get_register (PC) + 4)); | |
| 281 else | |
| 282 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8); | |
| 283 break; | |
| 284 }; | |
| 285 break; | |
| 286 #endif | |
| 287 | |
| 288 } | |
| 289 } | |
| 290 | |
| 291 | |
| 292 /* Clear the single-step state. */ | |
| 293 | |
| 2 | 294 void __clear_single_step (void) |
| 0 | 295 { |
| 296 //diag_printf("clear_ss ta %08x\n",instrBuffer.targetAddr); | |
| 297 if (instrBuffer.targetAddr != NULL) | |
| 298 { | |
| 299 *instrBuffer.targetAddr = instrBuffer.savedInstr; | |
| 300 instrBuffer.targetAddr = NULL; | |
| 301 } | |
| 302 instrBuffer.savedInstr = NOP_INSTR; | |
| 303 } | |
| 304 | |
| 305 | |
| 2 | 306 void __install_breakpoints () |
| 0 | 307 { |
| 308 //diag_printf("install_bpt ta %08x\n",instrBuffer.targetAddr); | |
| 309 if (instrBuffer.targetAddr != NULL) | |
| 310 { | |
| 311 instrBuffer.savedInstr = *instrBuffer.targetAddr; | |
| 312 *instrBuffer.targetAddr = __break_opcode (); | |
| 313 //diag_printf("ta %08x si %08x *ta %08x\n", | |
| 314 // instrBuffer.targetAddr,instrBuffer.savedInstr,*instrBuffer.targetAddr); | |
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315 |
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316 /* Ensure that the planted breakpoint makes it out to memory and |
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317 is subsequently loaded into the instruction cache. |
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318 */ |
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319 __data_cache (CACHE_FLUSH) ; |
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Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
320 __instruction_cache (CACHE_FLUSH) ; |
| 0 | 321 } |
| 322 } | |
| 323 | |
| 2 | 324 void __clear_breakpoints (void) |
| 325 { | |
| 326 } | |
| 327 | |
| 0 | 328 |
| 329 /* If the breakpoint we hit is in the breakpoint() instruction, return a | |
| 330 non-zero value. */ | |
| 331 | |
| 332 int | |
| 333 __is_breakpoint_function () | |
| 334 { | |
|
50
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
26
diff
changeset
|
335 return get_register (PC) == (target_register_t)(unsigned long)&CYG_LABEL_NAME(breakinst); |
| 0 | 336 } |
| 337 | |
| 338 | |
| 339 /* Skip the current instruction. Since this is only called by the | |
| 340 stub when the PC points to a breakpoint or trap instruction, | |
| 341 we can safely just skip 4. */ | |
| 342 | |
| 343 void __skipinst (void) | |
| 344 { | |
| 2 | 345 put_register (PC, get_register (PC) + 4); |
| 0 | 346 } |
| 347 | |
| 348 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
