annotate packages/hal/mips/arch/current/src/mips-stub.c @ 50:a0774359f013 ecos-sw-1999-11-02

Merge from eCos master repository on 1999-11-02-17:02:15-GMT
author jlarmour
date Tue, 02 Nov 1999 20:57:07 +0000
parents 4741a3c3496a
children c38311975d4f
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1 /* mips-stub.c - helper functions for stub, generic to all MIPS processors
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2 *
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3 * Copyright (c) 1998,1999 Cygnus Solutions
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4 *
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5 * The authors hereby grant permission to use, copy, modify, distribute,
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6 * and license this software and its documentation for any purpose, provided
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7 * that existing copyright notices are retained in all copies and that this
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8 * notice is included verbatim in any distributions. No written agreement,
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9 * license, or royalty fee is required for any of the authorized uses.
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10 * Modifications to this software may be copyrighted by their authors
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11 * and need not follow the licensing terms described here, provided that
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12 * the new terms are clearly indicated on the first page of each file where
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13 * they apply.
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14 */
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15
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16 #include <stddef.h>
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17
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18 #include <pkgconf/hal.h>
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19
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20 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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21
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22 #include <cyg/hal/hal_stub.h>
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23
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24 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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25 #include <cyg/hal/mips-regs.h>
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26
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27 #include <cyg/hal/hal_arch.h>
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28 #include <cyg/hal/mips_opcode.h>
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29
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30 typedef unsigned long t_inst;
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31
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32 /*----------------------------------------------------------------------
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33 * Asynchronous interrupt support
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34 */
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35
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36 static struct
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37 {
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38 t_inst *targetAddr;
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39 t_inst savedInstr;
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40 } asyncBuffer;
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41
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42 /* Called to asynchronously interrupt a running program.
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43 Must be passed address of instruction interrupted.
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44 This is typically called in response to a debug port
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45 receive interrupt.
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46 */
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47
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48 void
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49 install_async_breakpoint(void *epc)
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50 {
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51 long gp_save;
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52
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53 /* This may be called from a separately linked program,
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54 so we need to save and restore the incoming gp register
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55 and setup our stub local gp register.
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56 Alternatively, we could skip this foolishness if we
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57 compiled libstub with "-G 0". */
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58
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59 __asm__ volatile ( "move %0,$28\n"
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60 ".extern _gp\n"
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61 "la $28,_gp\n"
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62 : "=r" (gp_save) );
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63
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64 asyncBuffer.targetAddr = epc;
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65 asyncBuffer.savedInstr = *(t_inst *)epc;
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66 *(t_inst *)epc = *(t_inst *)_breakinst;
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67 __instruction_cache(CACHE_FLUSH);
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68 __data_cache(CACHE_FLUSH);
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69
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70 __asm__ volatile ( "move $28,%0\n" :: "r"(gp_save) );
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71 }
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72
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73 /*--------------------------------------------------------------------*/
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74 /* Given a trap value TRAP, return the corresponding signal. */
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75
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76 int __computeSignal (unsigned int trap_number)
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77 {
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78 switch (trap_number)
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79 {
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80 case EXC_INT:
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81 /* External interrupt */
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82 return SIGINT;
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83
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84 case EXC_RI:
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85 /* Reserved instruction */
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86 case EXC_CPU:
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87 /* Coprocessor unusable */
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88 return SIGILL;
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89
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90 case EXC_BP:
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91 /* Break point */
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92 if (asyncBuffer.targetAddr != NULL)
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93 {
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94 /* BP installed by serial driver to stop running program */
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95 *asyncBuffer.targetAddr = asyncBuffer.savedInstr;
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96 __instruction_cache(CACHE_FLUSH);
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97 __data_cache(CACHE_FLUSH);
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98 asyncBuffer.targetAddr = NULL;
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99 return SIGINT;
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100 }
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101 return SIGTRAP;
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102
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103 case EXC_OVF:
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104 /* Arithmetic overflow */
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105 case EXC_TRAP:
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106 /* Trap exception */
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107 case EXC_FPE:
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108 /* Floating Point Exception */
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109 return SIGFPE;
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110
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111 case EXC_IBE:
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112 /* Bus error (Ifetch) */
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113 case EXC_DBE:
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114 /* Bus error (data load or store) */
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115 return SIGBUS;
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116
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117 case EXC_MOD:
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118 /* TLB modification exception */
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119 case EXC_TLBL:
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120 /* TLB miss (Load or Ifetch) */
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121 case EXC_TLBS:
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122 /* TLB miss (Store) */
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123 case EXC_ADEL:
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124 /* Address error (Load or Ifetch) */
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125 case EXC_ADES:
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126 /* Address error (Store) */
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127 return SIGSEGV;
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128
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129 case EXC_SYS:
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130 /* System call */
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131 return SIGSYS;
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132
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133 default:
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134 return SIGTERM;
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135 }
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136 }
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137
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138 /* Return the trap number corresponding to the last-taken trap. */
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139
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140 int __get_trap_number (void)
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141 {
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142 return (get_register (CAUSE) & CAUSE_EXCMASK) >> CAUSE_EXCSHIFT;
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143 }
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144
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145 /* Set the currently-saved pc register value to PC. This also updates NPC
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146 as needed. */
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147
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148 void set_pc (target_register_t pc)
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149 {
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150 put_register (PC, pc);
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151 }
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152
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153
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154 /*----------------------------------------------------------------------
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155 * Single-step support
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156 */
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157
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158 /* Saved instruction data for single step support. */
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159
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160 static struct
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161 {
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162 t_inst *targetAddr;
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163 t_inst savedInstr;
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164 } instrBuffer;
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165
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166
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167 /* Set things up so that the next user resume will execute one instruction.
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168 This may be done by setting breakpoints or setting a single step flag
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169 in the saved user registers, for example. */
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170
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171 void __single_step (void)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
172 {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
173 InstFmt inst;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
174 t_inst *pc = (t_inst *) get_register (PC);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
175
2
443894e2e912 Block commit of eCos version 1.2.1
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parents: 0
diff changeset
176 instrBuffer.targetAddr = pc + 1; /* set default */
0
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
177
2
443894e2e912 Block commit of eCos version 1.2.1
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parents: 0
diff changeset
178 inst.word = *pc; /* read the next instruction */
0
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
179
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
180 //diag_printf("pc %08x %08x\n",pc,inst.word);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
181
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
182 switch (inst.RType.op) { /* override default if branch */
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
183 case OP_SPECIAL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
184 switch (inst.RType.func) {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
185 case OP_JR:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
186 case OP_JALR:
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
187 instrBuffer.targetAddr = (t_inst *) get_register (inst.RType.rs);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
188 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
189 };
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
190 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
191
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
192 case OP_REGIMM:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
193 switch (inst.IType.rt) {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
194 case OP_BLTZ:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
195 case OP_BLTZL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
196 case OP_BLTZAL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
197 case OP_BLTZALL:
26
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parents: 10
diff changeset
198 if ((int)get_register (inst.IType.rs) < 0 )
0
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
199 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
200 (t_inst *)(((signed short)inst.IType.imm<<2)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
201 + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
202 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
203 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
204 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
205 case OP_BGEZ:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
206 case OP_BGEZL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
207 case OP_BGEZAL:
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
208 case OP_BGEZALL:
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
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parents: 10
diff changeset
209 if ((int)get_register (inst.IType.rs) >= 0 )
0
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
210 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
211 (t_inst *)(((signed short)inst.IType.imm<<2)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
212 + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
213 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
214 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
215 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
216 };
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
217 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
218
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
219 case OP_J:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
220 case OP_JAL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
221 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
222 (t_inst *)((inst.JType.target<<2)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
223 + ((get_register (PC) + 4)&0xf0000000));
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
224 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
225
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
226 case OP_BEQ:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
227 case OP_BEQL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
228 if (get_register (inst.IType.rs) == get_register (inst.IType.rt))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
229 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
230 (t_inst *)(((signed short)inst.IType.imm<<2)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
231 + (get_register (PC) + 4));
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
232 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
233 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
234 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
235 case OP_BNE:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
236 case OP_BNEL:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
237 if (get_register (inst.IType.rs) != get_register (inst.IType.rt))
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
238 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
239 (t_inst *)(((signed short)inst.IType.imm<<2)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
240 + (get_register (PC) + 4));
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
241 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
242 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
243 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
244 case OP_BLEZ:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
245 case OP_BLEZL:
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
246 if ((int)get_register (inst.IType.rs) <= 0)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
247 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
248 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
249 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
250 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
251 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
252 case OP_BGTZ:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
253 case OP_BGTZL:
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
254 if ((int)get_register (inst.IType.rs) > 0)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
255 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
256 (t_inst *)(((signed short)inst.IType.imm<<2) + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
257 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
258 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
259 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
260
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
261 #ifdef CYGHWR_HAL_MIPS_FPU
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
262
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
263 case OP_COP1:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
264 if (inst.RType.rs == OP_BC)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
265 switch (inst.RType.rt) {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
266 case COPz_BCF:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
267 case COPz_BCFL:
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
268 if (get_register (FCR31) & FCR31_C)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
269 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
270 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
271 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
272 (t_inst *)(((signed short)inst.IType.imm<<2)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
273 + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
274 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
275 case COPz_BCT:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
276 case COPz_BCTL:
26
4741a3c3496a Merge from eCos master repository on 1999-07-23-05:47:06-BST
jlarmour
parents: 10
diff changeset
277 if (get_register (FCR31) & FCR31_C)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
278 instrBuffer.targetAddr =
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
279 (t_inst *)(((signed short)inst.IType.imm<<2)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
280 + (get_register (PC) + 4));
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
281 else
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
282 instrBuffer.targetAddr = (t_inst *)(get_register (PC) + 8);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
283 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
284 };
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
285 break;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
286 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
287
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
288 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
289 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
290
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
291
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
292 /* Clear the single-step state. */
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
293
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
294 void __clear_single_step (void)
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
295 {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
296 //diag_printf("clear_ss ta %08x\n",instrBuffer.targetAddr);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
297 if (instrBuffer.targetAddr != NULL)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
298 {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
299 *instrBuffer.targetAddr = instrBuffer.savedInstr;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
300 instrBuffer.targetAddr = NULL;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
301 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
302 instrBuffer.savedInstr = NOP_INSTR;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
303 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
304
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
305
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
306 void __install_breakpoints ()
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
307 {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
308 //diag_printf("install_bpt ta %08x\n",instrBuffer.targetAddr);
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
309 if (instrBuffer.targetAddr != NULL)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
310 {
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
311 instrBuffer.savedInstr = *instrBuffer.targetAddr;
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
312 *instrBuffer.targetAddr = __break_opcode ();
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
313 //diag_printf("ta %08x si %08x *ta %08x\n",
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
314 // instrBuffer.targetAddr,instrBuffer.savedInstr,*instrBuffer.targetAddr);
8
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
315
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
316 /* Ensure that the planted breakpoint makes it out to memory and
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
317 is subsequently loaded into the instruction cache.
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
318 */
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
319 __data_cache (CACHE_FLUSH) ;
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents: 2
diff changeset
320 __instruction_cache (CACHE_FLUSH) ;
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
321 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
322 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
323
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
324 void __clear_breakpoints (void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
325 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
326 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
327
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
328
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
329 /* If the breakpoint we hit is in the breakpoint() instruction, return a
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
330 non-zero value. */
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
331
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
332 int
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
333 __is_breakpoint_function ()
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
334 {
50
a0774359f013 Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents: 26
diff changeset
335 return get_register (PC) == (target_register_t)(unsigned long)&CYG_LABEL_NAME(breakinst);
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
336 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
337
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
338
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
339 /* Skip the current instruction. Since this is only called by the
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
340 stub when the PC points to a breakpoint or trap instruction,
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
341 we can safely just skip 4. */
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
342
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
343 void __skipinst (void)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
344 {
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents: 0
diff changeset
345 put_register (PC, get_register (PC) + 4);
0
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
346 }
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
347
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
348 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS