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annotate packages/hal/cortexm/arch/current/include/hal_io.h @ 3076:a532b7c12094

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* include/hal_io.h: conditional VTOR setting. [ Bugzilla 1001117 ]
author sergeig
date Wed, 19 Jan 2011 18:59:15 +0000
parents 8fe6d83b6d48
children 9aec6a8ff9b9
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1 #ifndef CYGONCE_HAL_IO_H
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2 #define CYGONCE_HAL_IO_H
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3 /*==========================================================================
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4 //
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5 // hal_io.h
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6 //
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7 // Cortex-M architecture IO register definitions
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8 //
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9 //==========================================================================
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10 // ####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 2008 Free Software Foundation, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later
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18 // version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License
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26 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use
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30 // macros or inline functions from this file, or you compile this file
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31 // and link it with other works to produce a work based on this file,
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32 // this file does not by itself cause the resulting work to be covered by
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33 // the GNU General Public License. However the source code for this file
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34 // must still be made available in accordance with section (3) of the GNU
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35 // General Public License v2.
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36 //
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37 // This exception does not invalidate any other reasons why a work based
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38 // on this file might be covered by the GNU General Public License.
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39 // -------------------------------------------
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40 // ####ECOSGPLCOPYRIGHTEND####
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41 //==========================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): nickg
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45 // Date: 2008-07-30
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46 // Description: Define IO registers
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //========================================================================*/
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51
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52 #include <pkgconf/system.h>
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53 #include <pkgconf/hal.h>
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54
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55 #include <cyg/infra/cyg_type.h>
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56
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57 #include <cyg/hal/var_io.h>
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58
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59 //==========================================================================
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60 // Handy macros for defining register bits and fields:
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61 //
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62
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63 #define BIT_(__n) (1<<(__n))
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64 #define MASK_(__n,__s) (((1<<(__s))-1)<<(__n))
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65 #define VALUE_(__n,__v) ((__v)<<(__n))
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66
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67 //==========================================================================
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68 // SysTick timer
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69 //
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70 // This is really part of the NVIC, but we break it out into a
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71 // separate definition for convenience.
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72
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73 #define CYGARC_REG_SYSTICK_BASE 0xE000E010
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74
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75 #define CYGARC_REG_SYSTICK_CSR 0
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76 #define CYGARC_REG_SYSTICK_RELOAD 4
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77 #define CYGARC_REG_SYSTICK_VALUE 8
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78 #define CYGARC_REG_SYSTICK_CAL 12
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79
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80 #define CYGARC_REG_SYSTICK_CSR_COUNTFLAG BIT_(16)
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81 #define CYGARC_REG_SYSTICK_CSR_CLK_EXT VALUE_(2,0)
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82 #define CYGARC_REG_SYSTICK_CSR_CLK_INT VALUE_(2,1)
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83 #define CYGARC_REG_SYSTICK_CSR_TICKINT BIT_(1)
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84 #define CYGARC_REG_SYSTICK_CSR_ENABLE BIT_(0)
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85
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86 #define CYGARC_REG_SYSTICK_CAL_NOREF BIT_(31)
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87 #define CYGARC_REG_SYSTICK_CAL_SKEW BIT_(30)
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88 #define CYGARC_REG_SYSTICK_CAL_TENMS MASK_(0,23)
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89
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90 //==========================================================================
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91 // NVIC registers
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92
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93 #define CYGARC_REG_NVIC_BASE 0xE000E000
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94
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95 #if defined(CYGHWR_HAL_CORTEXM_M3)
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96 #define CYGARC_REG_NVIC_TYPE 0x004
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97 #endif
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98
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99 #define CYGARC_REG_NVIC_SER0 0x100
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100 #define CYGARC_REG_NVIC_CER0 0x180
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101 #define CYGARC_REG_NVIC_SPR0 0x200
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102 #define CYGARC_REG_NVIC_CPR0 0x280
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103 #define CYGARC_REG_NVIC_ABR0 0x300
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104 #define CYGARC_REG_NVIC_PR0 0x400
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105
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106 // Generate address of 32 bit control register for interrupt
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107 #define CYGARC_REG_NVIC_SER(__intr) (CYGARC_REG_NVIC_SER0+4*((__intr)>>5))
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108 #define CYGARC_REG_NVIC_CER(__intr) (CYGARC_REG_NVIC_CER0+4*((__intr)>>5))
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109 #define CYGARC_REG_NVIC_SPR(__intr) (CYGARC_REG_NVIC_SPR0+4*((__intr)>>5))
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110 #define CYGARC_REG_NVIC_CPR(__intr) (CYGARC_REG_NVIC_CPR0+4*((__intr)>>5))
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111 #define CYGARC_REG_NVIC_ABR(__intr) (CYGARC_REG_NVIC_ABR0+4*((__intr)>>5))
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112
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113 // Generate bit in register for interrupt
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114 #define CYGARC_REG_NVIC_IBIT(__intr) BIT_((__intr)&0x1F)
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115
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116 // Generate byte address of interrupt's priority register.
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117 #define CYGARC_REG_NVIC_PR(__intr) (CYGARC_REG_NVIC_PR0+(__intr))
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118
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119
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120 #if defined(CYGHWR_HAL_CORTEXM_M3)
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121
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122 #define CYGARC_REG_NVIC_CPUID 0xD00
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123 #define CYGARC_REG_NVIC_ICSR 0xD04
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124 #define CYGARC_REG_NVIC_VTOR 0xD08
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125 #define CYGARC_REG_NVIC_AIRCR 0xD0C
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126 #define CYGARC_REG_NVIC_SCR 0xD10
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127 #define CYGARC_REG_NVIC_CCR 0xD14
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128 #define CYGARC_REG_NVIC_SHPR0 0xD18
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129 #define CYGARC_REG_NVIC_SHPR1 0xD1C
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130 #define CYGARC_REG_NVIC_SHPR2 0xD20
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131 #define CYGARC_REG_NVIC_SHCSR 0xD24
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132 #define CYGARC_REG_NVIC_CFSR 0xD28
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133 #define CYGARC_REG_NVIC_HFSR 0xD2C
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134 #define CYGARC_REG_NVIC_DFSR 0xD30
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135 #define CYGARC_REG_NVIC_MMAR 0xD34
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136 #define CYGARC_REG_NVIC_BFAR 0xD38
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137 #define CYGARC_REG_NVIC_AFSR 0xD3C
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138 #define CYGARC_REG_NVIC_PFR0 0xD40
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139 #define CYGARC_REG_NVIC_PFR1 0xD44
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140 #define CYGARC_REG_NVIC_DFR0 0xD48
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141 #define CYGARC_REG_NVIC_AFR0 0xD4C
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142 #define CYGARC_REG_NVIC_MMFR0 0xD50
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143 #define CYGARC_REG_NVIC_MMFR1 0xD54
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144 #define CYGARC_REG_NVIC_MMFR2 0xD58
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145 #define CYGARC_REG_NVIC_MMFR3 0xD5C
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146 #define CYGARC_REG_NVIC_ISAR0 0xD60
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147 #define CYGARC_REG_NVIC_ISAR1 0xD64
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148 #define CYGARC_REG_NVIC_ISAR2 0xD68
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149 #define CYGARC_REG_NVIC_ISAR3 0xD6C
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150 #define CYGARC_REG_NVIC_ISAR4 0xD70
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151 #define CYGARC_REG_NVIC_STIR 0xF00
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152 #define CYGARC_REG_NVIC_PID4 0xFD0
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153 #define CYGARC_REG_NVIC_PID5 0xFD4
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154 #define CYGARC_REG_NVIC_PID6 0xFD8
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155 #define CYGARC_REG_NVIC_PID7 0xFDC
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156 #define CYGARC_REG_NVIC_PID0 0xFE0
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157 #define CYGARC_REG_NVIC_PID1 0xFE4
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158 #define CYGARC_REG_NVIC_PID2 0xFE8
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159 #define CYGARC_REG_NVIC_PID3 0xFEC
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160 #define CYGARC_REG_NVIC_CID0 0xFF0
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161 #define CYGARC_REG_NVIC_CID1 0xFF4
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162 #define CYGARC_REG_NVIC_CID2 0xFF8
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163 #define CYGARC_REG_NVIC_CID3 0xFFC
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164
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165 // ICSR
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166
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167 #define CYGARC_REG_NVIC_ICSR_NMIPENDSET BIT_(31)
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168 #define CYGARC_REG_NVIC_ICSR_PENDSVSET BIT_(28)
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169 #define CYGARC_REG_NVIC_ICSR_PENDSVCLR BIT_(27)
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170 #define CYGARC_REG_NVIC_ICSR_PENDSTSET BIT_(26)
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171 #define CYGARC_REG_NVIC_ICSR_PENDSTCLR BIT_(25)
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172 #define CYGARC_REG_NVIC_ICSR_ISRPREEMPT BIT_(23)
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173 #define CYGARC_REG_NVIC_ICSR_ISRPENDING BIT_(22)
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174 #define CYGARC_REG_NVIC_ICSR_VECTPENDING MASK_(12,9)
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175 #define CYGARC_REG_NVIC_ICSR_RETTOBASE BIT_(11)
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176 #define CYGARC_REG_NVIC_ICSR_VECTACTIVE MASK_(0,9)
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177
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178 // VTOR
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179
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180 #define CYGARC_REG_NVIC_VTOR_TBLOFF(__o) VALUE_(7,__o)
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181 #define CYGARC_REG_NVIC_VTOR_TBLBASE_CODE 0
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182 #ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
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183 #define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM BIT_(29)
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184 #endif
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185
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186 // AI/RCR
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187
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188 #define CYGARC_REG_NVIC_AIRCR_KEY VALUE_(16,0x5FA)
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189 #define CYGARC_REG_NVIC_AIRCR_BIGENDIAN BIT_(15)
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190 #define CYGARC_REG_NVIC_AIRCR_PRIGROUP(__p) VALUE_(8,__p)
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191 #define CYGARC_REG_NVIC_AIRCR_SYSRESETREQ BIT_(2)
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192 #define CYGARC_REG_NVIC_AIRCR_VECTCLRACTIVE BIT_(1)
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193 #define CYGARC_REG_NVIC_AIRCR_VECTRESET BIT_(0)
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194
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195 // SCR
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196
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197 #define CYGARC_REG_NVIC_SCR_SLEEPONEXIT BIT_(1)
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198 #define CYGARC_REG_NVIC_SCR_DEEPSLEEP BIT_(2)
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199 #define CYGARC_REG_NVIC_SCR_SEVONPEND BIT_(4)
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200
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201 // SHCSR
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202
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203 #define CYGARC_REG_NVIC_SHCSR_USGFAULTENA BIT_(18)
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204 #define CYGARC_REG_NVIC_SHCSR_BUSFAULTENA BIT_(17)
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205 #define CYGARC_REG_NVIC_SHCSR_MEMFAULTENA BIT_(16)
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206 #define CYGARC_REG_NVIC_SHCSR_SVCALLPENDED BIT_(15)
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207 #define CYGARC_REG_NVIC_SHCSR_BUSFAULTPENDED BIT_(14)
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208 #define CYGARC_REG_NVIC_SHCSR_MEMFAULTPENDED BIT_(13)
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209 #define CYGARC_REG_NVIC_SHCSR_USGFAULTPENDED BIT_(12)
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210 #define CYGARC_REG_NVIC_SHCSR_SYSTICKACT BIT_(11)
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211 #define CYGARC_REG_NVIC_SHCSR_PENDSVACT BIT_(10)
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212 #define CYGARC_REG_NVIC_SHCSR_MONITORACT BIT_(8)
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213 #define CYGARC_REG_NVIC_SHCSR_SVCALLACT BIT_(7)
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214 #define CYGARC_REG_NVIC_SHCSR_USGFAULTACT BIT_(3)
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215 #define CYGARC_REG_NVIC_SHCSR_BUSFAULTACT BIT_(1)
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216 #define CYGARC_REG_NVIC_SHCSR_MEMFAULTACT BIT_(0)
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217
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218 #endif
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219
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220 //==========================================================================
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221 // Debug registers
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222
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223 #if defined(CYGHWR_HAL_CORTEXM_M3)
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224
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225 #define CYGARC_REG_DEBUG_BASE 0xE000EDF0
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226
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227 #define CYGARC_REG_DEBUG_DHSR 0x00
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228 #define CYGARC_REG_DEBUG_DCRSR 0x04
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229 #define CYGARC_REG_DEBUG_DCRDR 0x08
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230 #define CYGARC_REG_DEBUG_DEMCR 0x0C
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231
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232
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233 #define CYGARC_REG_DEBUG_DHSR_DBGKEY VALUE_(16,0xA05F)
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234 #define CYGARC_REG_DEBUG_DHSR_S_RESET BIT_(25)
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235 #define CYGARC_REG_DEBUG_DHSR_S_RETIRE BIT_(24)
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236 #define CYGARC_REG_DEBUG_DHSR_S_LOCKUP BIT_(19)
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237 #define CYGARC_REG_DEBUG_DHSR_S_SLEEP BIT_(18)
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238 #define CYGARC_REG_DEBUG_DHSR_S_HALT BIT_(17)
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239 #define CYGARC_REG_DEBUG_DHSR_S_REGRDY BIT_(16)
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240 #define CYGARC_REG_DEBUG_DHSR_C_SNAPSTALL BIT_(5)
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241 #define CYGARC_REG_DEBUG_DHSR_C_MASKINTS BIT_(3)
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242 #define CYGARC_REG_DEBUG_DHSR_C_STEP BIT_(2)
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243 #define CYGARC_REG_DEBUG_DHSR_C_HALT BIT_(1)
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244 #define CYGARC_REG_DEBUG_DHSR_C_DEBUGEN BIT_(0)
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245
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246
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247 #define CYGARC_REG_DEBUG_DCRSR_REG_WRITE BIT_(16)
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248 #define CYGARC_REG_DEBUG_DCRSR_REG_READ 0
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249 #define CYGARC_REG_DEBUG_DCRSR_REG(__x) VALUE_(0,__x)
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250
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251
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252 #define CYGARC_REG_DEBUG_DEMCR_TRCENA BIT_(24)
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253 #define CYGARC_REG_DEBUG_DEMCR_MON_REQ BIT_(19)
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254 #define CYGARC_REG_DEBUG_DEMCR_MON_STEP BIT_(18)
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255 #define CYGARC_REG_DEBUG_DEMCR_MON_PEND BIT_(17)
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256 #define CYGARC_REG_DEBUG_DEMCR_MON_EN BIT_(16)
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257 #define CYGARC_REG_DEBUG_DEMCR_VC_HARDERR BIT_(10)
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258 #define CYGARC_REG_DEBUG_DEMCR_VC_INTERR BIT_(9)
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259 #define CYGARC_REG_DEBUG_DEMCR_VC_BUSERR BIT_(8)
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260 #define CYGARC_REG_DEBUG_DEMCR_VC_STATERR BIT_(7)
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261 #define CYGARC_REG_DEBUG_DEMCR_VC_CHKERR BIT_(6)
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262 #define CYGARC_REG_DEBUG_DEMCR_VC_NOCPERR BIT_(5)
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263 #define CYGARC_REG_DEBUG_DEMCR_VC_MMERR BIT_(4)
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264 #define CYGARC_REG_DEBUG_DEMCR_VC_CORERESET BIT_(0)
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265
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266 #endif
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267
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268 //==========================================================================
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269 // IO Register address.
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270 // This type is for recording the address of an IO register.
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271
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272 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
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273
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274 //-----------------------------------------------------------------------------
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275 // HAL IO macros.
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276
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277 #ifndef HAL_IO_MACROS_DEFINED
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278
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279 //-----------------------------------------------------------------------------
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280 // BYTE Register access.
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281 // Individual and vectorized access to 8 bit registers.
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282
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283
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284 #define HAL_READ_UINT8( _register_, _value_ ) \
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285 ((_value_) = *((volatile CYG_BYTE *)(_register_)))
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286
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287 #define HAL_WRITE_UINT8( _register_, _value_ ) \
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288 (*((volatile CYG_BYTE *)(_register_)) = (_value_))
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289
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290 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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291 CYG_MACRO_START \
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292 cyg_count32 _i_,_j_; \
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293 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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294 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
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295 CYG_MACRO_END
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296
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297 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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298 CYG_MACRO_START \
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299 cyg_count32 _i_,_j_; \
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300 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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301 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
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302 CYG_MACRO_END
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303
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304 #define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \
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305 CYG_MACRO_START \
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306 cyg_count32 _i_; \
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307 for( _i_ = 0; _i_ < (_count_); _i_++) \
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308 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_]; \
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309 CYG_MACRO_END
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310
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311 #define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \
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312 CYG_MACRO_START \
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313 cyg_count32 _i_; \
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314 for( _i_ = 0; _i_ < (_count_); _i_++) \
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315 ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_]; \
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316 CYG_MACRO_END
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317
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318 //-----------------------------------------------------------------------------
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319 // 16 bit access.
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320 // Individual and vectorized access to 16 bit registers.
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321
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322
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323 #define HAL_READ_UINT16( _register_, _value_ ) \
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324 ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
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325
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326 #define HAL_WRITE_UINT16( _register_, _value_ ) \
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327 (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
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328
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329 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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330 CYG_MACRO_START \
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331 cyg_count32 _i_,_j_; \
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332 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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333 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
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334 CYG_MACRO_END
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335
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336 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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337 CYG_MACRO_START \
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338 cyg_count32 _i_,_j_; \
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339 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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340 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
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341 CYG_MACRO_END
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342
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343 #define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
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344 CYG_MACRO_START \
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345 cyg_count32 _i_; \
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346 for( _i_ = 0; _i_ < (_count_); _i_++) \
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347 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_]; \
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348 CYG_MACRO_END
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349
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350 #define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
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351 CYG_MACRO_START \
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352 cyg_count32 _i_; \
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353 for( _i_ = 0; _i_ < (_count_); _i_++) \
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354 ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_]; \
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355 CYG_MACRO_END
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356
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357 //-----------------------------------------------------------------------------
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358 // 32 bit access.
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359 // Individual and vectorized access to 32 bit registers.
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360
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361 #define HAL_READ_UINT32( _register_, _value_ ) \
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362 ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
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363
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364 #define HAL_WRITE_UINT32( _register_, _value_ ) \
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365 (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
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366
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367 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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368 CYG_MACRO_START \
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369 cyg_count32 _i_,_j_; \
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370 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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371 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
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372 CYG_MACRO_END
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373
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374 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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375 CYG_MACRO_START \
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376 cyg_count32 _i_,_j_; \
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377 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
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378 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
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379 CYG_MACRO_END
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380
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381 #define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \
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382 CYG_MACRO_START \
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383 cyg_count32 _i_; \
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384 for( _i_ = 0; _i_ < (_count_); _i_++) \
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385 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_]; \
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386 CYG_MACRO_END
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387
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388 #define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \
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389 CYG_MACRO_START \
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390 cyg_count32 _i_; \
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391 for( _i_ = 0; _i_ < (_count_); _i_++) \
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392 ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_]; \
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393 CYG_MACRO_END
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394
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395
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396 #define HAL_IO_MACROS_DEFINED
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397
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398 #endif // !HAL_IO_MACROS_DEFINED
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399
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400 // Enforce a flow "barrier" to prevent optimizing compiler from reordering
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401 // operations.
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402 #define HAL_IO_BARRIER()
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403
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404
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405 //==========================================================================
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406 #endif //CYGONCE_HAL_IO_H