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annotate packages/hal/arm/cma230/current/include/hal_cache.h @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 6e51d764f8f1
children bf00f99aec69
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg, gthomas
58
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38 // Contributors: nickg, gthomas, msalter
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39 // Date: 1998-09-28
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/hal_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <cyg/infra/cyg_type.h>
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53
58
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54 #ifdef __CMA222
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55 //-----------------------------------------------------------------------------
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56 // Cache dimensions
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57
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58 #define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes
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59 #define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line
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60 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
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61 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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62
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63 #define HAL_CACHE_UNIFIED // Let programs know the caches are combined
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64
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65 //-----------------------------------------------------------------------------
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66 // Global control of caches
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67
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68 // Note: the 'mrc' doesn't seem to work.
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69 #if 0
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70 // Enable the data cache
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71 // mrc MMU_CP,0,r1,MMU_Control,c0
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72 // orr r1,r1,#MMU_Control_C|MMU_Control_B
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73 // mcr MMU_CP,0,r1,MMU_Control,c0
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74
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75 #define HAL_UCACHE_ENABLE() \
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76 { \
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77 asm volatile ("mrc p15,0,r1,c1,c0;" \
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78 "orr r1,r1,#0x000C;" \
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79 "mcr p15,0,r1,c1,c0;" \
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80 : \
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81 : \
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82 : "r1" /* Clobber list */ \
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83 ); \
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84 \
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85 }
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86
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87 // Disable the data cache
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88 #define HAL_UCACHE_DISABLE() \
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89 { \
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90 asm volatile ("mrc p15,0,r1,c1,c0;" \
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91 "bic r1,r1,#0x000C;" \
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92 "mcr p15,0,r1,c1,c0;" \
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93 : \
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94 : \
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95 : "r1" /* Clobber list */ \
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96 ); \
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97 \
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98 }
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99 #else
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100 #define HAL_UCACHE_ENABLE() \
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101 { \
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102 asm volatile ("mov r1,#0x7D;" \
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103 "mcr p15,0,r1,c1,c0;" \
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104 : \
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105 : \
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106 : "r1" /* Clobber list */ \
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107 ); \
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108 \
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109 }
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110
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111 // Disable the data cache
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112 #define HAL_UCACHE_DISABLE() \
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113 { \
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114 asm volatile ("mov r1,#0x71;" \
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115 "mcr p15,0,r1,c1,c0;" \
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116 : \
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117 : \
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118 : "r1" /* Clobber list */ \
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119 ); \
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120 \
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121 }
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122 #endif
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123
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124 // Is the cache turned on?
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125 #define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
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126
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127 // Invalidate the entire cache
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128 // mcr MMU_CP,0,r1,MMU_InvalidateCache,c0
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129 #define HAL_UCACHE_INVALIDATE_ALL() \
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130 { \
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131 asm volatile ("mcr p15,0,r1,c7,c0,0;" ); \
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132 \
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133 }
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134
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135 // Synchronize the contents of the cache with memory.
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136 #define HAL_UCACHE_SYNC() \
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137 { \
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138 cyg_uint32 *ROM = (cyg_uint32 *)0xE0000000; \
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139 int i; \
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140 volatile cyg_uint32 val; \
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141 for (i = 0; i < HAL_UCACHE_SETS; i++) { \
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142 val = *ROM; \
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143 ROM += HAL_UCACHE_LINE_SIZE; \
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144 } \
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145 }
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146
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147 // Purge contents of data cache
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148 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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149
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150 //-----------------------------------------------------------------------------
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151 // Data cache line control
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152
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153 // Write dirty cache lines to memory and invalidate the cache entries
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154 // for the given address range.
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155 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC()
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156
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157 // Write dirty cache lines to memory for the given address range.
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158 #define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC()
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159
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160 #endif // ifdef __CMA222
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161
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162 #ifdef HAL_CACHE_UNIFIED
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163 //-----------------------------------------------------------------------------
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164 // Global control of data cache
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165
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166 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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167 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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168 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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169 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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170
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171 // Enable the data cache
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172 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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173
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174 // Disable the data cache
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175 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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176
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177 // Invalidate the entire cache
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178 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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179
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180 // Synchronize the contents of the cache with memory.
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181 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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182
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183 // Query the state of the data cache
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184 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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185
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186 //-----------------------------------------------------------------------------
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187 // Data cache line control
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188
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189 // Write dirty cache lines to memory and invalidate the cache entries
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190 // for the given address range.
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191 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ )
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192
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193 // Write dirty cache lines to memory for the given address range.
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194 #define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ )
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195
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196 //-----------------------------------------------------------------------------
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197 // Global control of Instruction cache - use Data cache controls since they
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198 // are not separatable.
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199
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200 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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201 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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202 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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203 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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204
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205 // Enable the instruction cache
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206 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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207
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208 // Disable the instruction cache
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209 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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210
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211 // Invalidate the entire cache
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212 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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213
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214 // Synchronize the contents of the cache with memory.
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215 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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216
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217 #else
46
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218 //-----------------------------------------------------------------------------
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219 // Cache dimensions
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220
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221 // Data cache
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222 #define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
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223 #define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
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224 #define HAL_DCACHE_WAYS 0 // Associativity of the cache
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225
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226 // Instruction cache
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227 #define HAL_ICACHE_SIZE 0 // Size of cache in bytes
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228 #define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
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229 #define HAL_ICACHE_WAYS 0 // Associativity of the cache
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230
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231 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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232 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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233
58
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234
46
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235 //-----------------------------------------------------------------------------
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236 // Global control of data cache
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237
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238 // Enable the data cache
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239 #define HAL_DCACHE_ENABLE()
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240
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241 // Disable the data cache
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242 #define HAL_DCACHE_DISABLE()
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243
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244 // Invalidate the entire cache
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245 #define HAL_DCACHE_INVALIDATE_ALL()
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246
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247 // Synchronize the contents of the cache with memory.
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248 #define HAL_DCACHE_SYNC()
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249
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250 // Purge contents of data cache
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251 #define HAL_DCACHE_PURGE_ALL()
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252
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253 // Set the data cache refill burst size
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254 //#define HAL_DCACHE_BURST_SIZE(_size_)
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255
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256 // Set the data cache write mode
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257 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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258
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259 //#define HAL_DCACHE_WRITETHRU_MODE 0
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260 //#define HAL_DCACHE_WRITEBACK_MODE 1
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261
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262 // Load the contents of the given address range into the data cache
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263 // and then lock the cache so that it stays there.
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264 //#define HAL_DCACHE_LOCK(_base_, _size_)
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265
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266 // Undo a previous lock operation
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267 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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268
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269 // Unlock entire cache
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270 //#define HAL_DCACHE_UNLOCK_ALL()
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271
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272 //-----------------------------------------------------------------------------
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273 // Data cache line control
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274
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275 // Allocate cache lines for the given address range without reading its
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276 // contents from memory.
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277 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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278
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279 // Write dirty cache lines to memory and invalidate the cache entries
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280 // for the given address range.
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281 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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282
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283 // Invalidate cache lines in the given range without writing to memory.
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284 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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285
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286 // Write dirty cache lines to memory for the given address range.
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287 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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288
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289 // Preread the given range into the cache with the intention of reading
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290 // from it later.
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291 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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292
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293 // Preread the given range into the cache with the intention of writing
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294 // to it later.
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295 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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296
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297 // Allocate and zero the cache lines associated with the given range.
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298 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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299
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300 //-----------------------------------------------------------------------------
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301 // Global control of Instruction cache
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302
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303 // Enable the instruction cache
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304 #define HAL_ICACHE_ENABLE()
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305
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306 // Disable the instruction cache
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307 #define HAL_ICACHE_DISABLE()
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308
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309 // Invalidate the entire cache
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310 #define HAL_ICACHE_INVALIDATE_ALL()
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311
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312 // Synchronize the contents of the cache with memory.
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313 #define HAL_ICACHE_SYNC()
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314
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315 // Set the instruction cache refill burst size
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316 //#define HAL_ICACHE_BURST_SIZE(_size_)
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317
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318 // Load the contents of the given address range into the instruction cache
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319 // and then lock the cache so that it stays there.
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320 //#define HAL_ICACHE_LOCK(_base_, _size_)
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321
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322 // Undo a previous lock operation
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323 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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324
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325 // Unlock entire cache
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326 //#define HAL_ICACHE_UNLOCK_ALL()
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327
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328 //-----------------------------------------------------------------------------
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329 // Instruction cache line control
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330
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331 // Invalidate cache lines in the given range without writing to memory.
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332 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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333
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334 //-----------------------------------------------------------------------------
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335 #endif // ifndef HAL_CACHE_UNIFIED
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336 #endif // ifndef CYGONCE_HAL_CACHE_H
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337 // End of hal_cache.h