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annotate packages/hal/arm/pid/current/src/plf_stub.c @ 64:c38311975d4f ecos-sw-2000-01-28
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
| author | jlarmour |
|---|---|
| date | Fri, 28 Jan 2000 04:59:39 +0000 |
| parents | 443894e2e912 |
| children | bf00f99aec69 |
| rev | line source |
|---|---|
| 2 | 1 //============================================================================= |
| 2 // | |
| 3 // plf_stub.c | |
| 4 // | |
| 5 // Platform specific code for GDB stub support. | |
| 6 // | |
| 7 //============================================================================= | |
| 8 //####COPYRIGHTBEGIN#### | |
|
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 2 | 30 //####COPYRIGHTEND#### |
| 31 //============================================================================= | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 34 // Author(s): gthomas (based on the old ARM/PID hal_stub.c) | |
| 35 // Contributors:gthomas, jskov | |
| 36 // Date: 1999-02-15 | |
| 37 // Purpose: Platform specific code for GDB stub support. | |
| 38 // | |
| 39 //####DESCRIPTIONEND#### | |
| 40 // | |
| 41 //============================================================================= | |
| 42 | |
| 43 #include <pkgconf/hal.h> | |
| 44 | |
| 45 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 46 | |
| 47 #include <cyg/hal/hal_stub.h> | |
| 48 | |
| 49 #include <cyg/hal/hal_io.h> // HAL IO macros | |
| 50 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 51 #include <cyg/hal/hal_intr.h> // HAL interrupt macros | |
| 52 #include <cyg/hal/drv_api.h> // HAL ISR support | |
| 53 #endif | |
| 54 | |
| 55 //----------------------------------------------------------------------------- | |
| 56 // Serial definitions. | |
| 57 #if CYGHWR_HAL_ARM_PID_GDB_PORT==0 | |
| 58 // This is the base address of the A-channel | |
| 59 #define CYG_DEVICE_SERIAL_RS232_16550_BASE 0x0D800000 | |
| 60 #define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIALA | |
| 61 #else | |
| 62 // This is the base address of the B-channel | |
| 63 #define CYG_DEVICE_SERIAL_RS232_16550_BASE 0x0D800020 | |
| 64 #define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIALB | |
| 65 #endif | |
| 66 | |
| 67 #if CYGHWR_HAL_ARM_PID_GDB_BAUD==9600 | |
| 68 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 | |
| 69 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x0C | |
| 70 #endif | |
| 71 #if CYGHWR_HAL_ARM_PID_GDB_BAUD==19200 | |
| 72 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 | |
| 73 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x06 | |
| 74 #endif | |
| 75 #if CYGHWR_HAL_ARM_PID_GDB_BAUD==38400 | |
| 76 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 | |
| 77 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x03 | |
| 78 #endif | |
| 79 #if CYGHWR_HAL_ARM_PID_GDB_BAUD==115200 | |
| 80 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 | |
| 81 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x01 | |
| 82 #endif | |
| 83 | |
| 84 #ifndef CYG_DEVICE_SERIAL_RS232_BAUD_MSB | |
| 85 #error Missing/incorrect serial baud rate defined - CDL error? | |
| 86 #endif | |
| 87 | |
| 88 // Define the serial registers. | |
| 89 #define CYG_DEVICE_SERIAL_RS232_16550_RBR \ | |
| 90 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 91 // receiver buffer register, read, dlab = 0 | |
| 92 #define CYG_DEVICE_SERIAL_RS232_16550_THR \ | |
| 93 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 94 // transmitter holding register, write, dlab = 0 | |
| 95 #define CYG_DEVICE_SERIAL_RS232_16550_DLL \ | |
| 96 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) | |
| 97 // divisor latch (LS), read/write, dlab = 1 | |
| 98 #define CYG_DEVICE_SERIAL_RS232_16550_IER \ | |
| 99 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04) | |
| 100 // interrupt enable register, read/write, dlab = 0 | |
| 101 #define CYG_DEVICE_SERIAL_RS232_16550_DLM \ | |
| 102 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x04) | |
| 103 // divisor latch (MS), read/write, dlab = 1 | |
| 104 #define CYG_DEVICE_SERIAL_RS232_16550_IIR \ | |
| 105 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) | |
| 106 // interrupt identification register, read, dlab = 0 | |
| 107 #define CYG_DEVICE_SERIAL_RS232_16550_FCR \ | |
| 108 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) | |
| 109 // fifo control register, write, dlab = 0 | |
| 110 #define CYG_DEVICE_SERIAL_RS232_16550_LCR \ | |
| 111 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x0C) | |
| 112 // line control register, read/write | |
| 113 #define CYG_DEVICE_SERIAL_RS232_16550_MCR \ | |
| 114 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10) | |
| 115 // modem control register, read/write | |
| 116 #define CYG_DEVICE_SERIAL_RS232_16550_LSR \ | |
| 117 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x14) | |
| 118 // line status register, read | |
| 119 #define CYG_DEVICE_SERIAL_RS232_16550_MSR \ | |
| 120 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x18) | |
| 121 // modem status register, read | |
| 122 | |
| 123 // The interrupt enable register bits. | |
| 124 #define SIO_IER_ERDAI 0x01 // enable received data available irq | |
| 125 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt | |
| 126 #define SIO_IER_ELSI 0x04 // enable receiver line status irq | |
| 127 #define SIO_IER_EMSI 0x08 // enable modem status interrupt | |
| 128 | |
| 129 // The interrupt identification register bits. | |
| 130 #define SIO_IIR_IP 0x01 // 0 if interrupt pending | |
| 131 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits | |
| 132 | |
| 133 // The line status register bits. | |
| 134 #define SIO_LSR_DR 0x01 // data ready | |
| 135 #define SIO_LSR_OE 0x02 // overrun error | |
| 136 #define SIO_LSR_PE 0x04 // parity error | |
| 137 #define SIO_LSR_FE 0x08 // framing error | |
| 138 #define SIO_LSR_BI 0x10 // break interrupt | |
| 139 #define SIO_LSR_THRE 0x20 // transmitter holding register empty | |
| 140 #define SIO_LSR_TEMT 0x40 // transmitter register empty | |
| 141 #define SIO_LSR_ERR 0x80 // any error condition | |
| 142 | |
| 143 // The modem status register bits. | |
| 144 #define SIO_MSR_DCTS 0x01 // delta clear to send | |
| 145 #define SIO_MSR_DDSR 0x02 // delta data set ready | |
| 146 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator | |
| 147 #define SIO_MSR_DDCD 0x08 // delta data carrier detect | |
| 148 #define SIO_MSR_CTS 0x10 // clear to send | |
| 149 #define SIO_MSR_DSR 0x20 // data set ready | |
| 150 #define SIO_MSR_RI 0x40 // ring indicator | |
| 151 #define SIO_MSR_DCD 0x80 // data carrier detect | |
| 152 | |
| 153 // The line control register bits. | |
| 154 #define SIO_LCR_WLS0 0x01 // word length select bit 0 | |
| 155 #define SIO_LCR_WLS1 0x02 // word length select bit 1 | |
| 156 #define SIO_LCR_STB 0x04 // number of stop bits | |
| 157 #define SIO_LCR_PEN 0x08 // parity enable | |
| 158 #define SIO_LCR_EPS 0x10 // even parity select | |
| 159 #define SIO_LCR_SP 0x20 // stick parity | |
| 160 #define SIO_LCR_SB 0x40 // set break | |
| 161 #define SIO_LCR_DLAB 0x80 // divisor latch access bit | |
| 162 | |
| 163 // Interrupt Enable Register | |
| 164 #define SIO_IER_RCV 0x01 | |
| 165 #define SIO_IER_XMT 0x02 | |
| 166 #define SIO_IER_LS 0x04 | |
| 167 #define SIO_IER_MS 0x08 | |
| 168 | |
| 169 // Modem Control Register | |
| 170 #define SIO_MCR_DTR 0x01 | |
| 171 #define SIO_MCR_RTS 0x02 | |
| 172 #define SIO_MCR_INT 0x08 // Enable interrupts | |
| 173 | |
| 174 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 175 static cyg_interrupt gdb_interrupt; | |
| 176 static cyg_handle_t gdb_interrupt_handle; | |
| 177 #endif | |
| 178 | |
| 179 //----------------------------------------------------------------------------- | |
| 180 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 181 // This ISR is called only for serial receive interrupts. | |
| 182 int | |
| 183 cyg_hal_gdb_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) | |
| 184 { | |
| 185 cyg_uint8 c; | |
| 186 | |
| 187 c = hal_pid_get_char(); // Fetch the character | |
| 188 if( 3 == c ) { // ^C | |
| 189 // Ctrl-C: set a breakpoint at PC so GDB will display the | |
| 190 // correct program context when stopping rather than the | |
| 191 // interrupt handler. | |
| 192 cyg_hal_gdb_interrupt (regs->pc); | |
| 193 cyg_drv_interrupt_acknowledge(CYG_DEVICE_SERIAL_INT); | |
| 194 } | |
| 195 return 0; // No need to run DSR | |
| 196 } | |
| 197 | |
| 198 int | |
| 199 hal_pid_interruptible(int state) | |
| 200 { | |
| 201 if (state) { | |
| 202 cyg_drv_interrupt_unmask(CYG_DEVICE_SERIAL_INT); | |
| 203 } else { | |
| 204 cyg_drv_interrupt_mask(CYG_DEVICE_SERIAL_INT); | |
| 205 } | |
| 206 | |
| 207 return 0; | |
| 208 } | |
| 209 #endif | |
| 210 | |
| 211 // Initialize the current serial port. | |
| 212 void hal_pid_init_serial(void) | |
| 213 { | |
| 214 cyg_uint8 lcr; | |
| 215 | |
| 216 // 8-1-no parity. | |
| 217 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, | |
| 218 SIO_LCR_WLS0 | SIO_LCR_WLS1); | |
| 219 | |
| 220 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 221 lcr |= SIO_LCR_DLAB; | |
| 222 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 223 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLL, | |
| 224 CYG_DEVICE_SERIAL_RS232_BAUD_LSB); | |
| 225 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLM, | |
| 226 CYG_DEVICE_SERIAL_RS232_BAUD_MSB); | |
| 227 lcr &= ~SIO_LCR_DLAB; | |
| 228 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr); | |
| 229 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_FCR, 0x07); // Enable & clear FIFO | |
| 230 | |
| 231 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 232 cyg_drv_interrupt_create(CYG_DEVICE_SERIAL_INT, | |
| 233 99, // Priority - what goes here? | |
| 234 0, // Data item passed to interrupt handler | |
| 235 cyg_hal_gdb_isr, | |
| 236 0, | |
| 237 &gdb_interrupt_handle, | |
| 238 &gdb_interrupt); | |
| 239 cyg_drv_interrupt_attach(gdb_interrupt_handle); | |
| 240 cyg_drv_interrupt_unmask(CYG_DEVICE_SERIAL_INT); | |
| 241 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_IER, SIO_IER_RCV); | |
| 242 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS); | |
| 243 #endif | |
| 244 } | |
| 245 | |
| 246 // Write C to the current serial port. | |
| 247 void hal_pid_put_char(int c) | |
| 248 { | |
| 249 cyg_uint8 lsr; | |
| 250 | |
| 251 do { | |
| 252 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr); | |
| 253 } while ((lsr & SIO_LSR_THRE) == 0); | |
| 254 | |
| 255 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c); | |
| 256 } | |
| 257 | |
| 258 // Read one character from the current serial port. | |
| 259 int hal_pid_get_char(void) | |
| 260 { | |
| 261 char c; | |
| 262 cyg_uint8 lsr; | |
| 263 | |
| 264 do { | |
| 265 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr); | |
| 266 } while ((lsr & SIO_LSR_DR) == 0); | |
| 267 | |
| 268 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, c); | |
| 269 return c; | |
| 270 } | |
| 271 | |
| 272 #endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 273 //----------------------------------------------------------------------------- | |
| 274 // End of plf_stub.c |