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annotate packages/hal/mn10300/arch/current/include/hal_cache.h @ 64:c38311975d4f ecos-sw-2000-01-28
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
| author | jlarmour |
|---|---|
| date | Fri, 28 Jan 2000 04:59:39 +0000 |
| parents | e97d78785e2d |
| children | bf00f99aec69 |
| rev | line source |
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| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 2 | 6 // hal_cache.h |
| 0 | 7 // |
| 2 | 8 // HAL cache control API |
| 0 | 9 // |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 0 | 33 //####COPYRIGHTEND#### |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 2 | 37 // Author(s): nickg |
| 38 // Contributors: nickg | |
| 39 // Date: 1998-02-17 | |
| 40 // Purpose: Cache control API | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 0 | 42 // cache control operations. |
| 43 // Usage: | |
| 2 | 44 // #include <cyg/hal/hal_cache.h> |
| 45 // ... | |
| 46 // | |
| 0 | 47 // |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //============================================================================= | |
| 51 | |
| 2 | 52 #include <pkgconf/hal.h> |
| 0 | 53 #include <cyg/infra/cyg_type.h> |
| 54 | |
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55 #if !defined(CYG_HAL_MN10300_AM31_SIM) |
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56 |
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57 #include <cyg/hal/var_cache.h> |
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58 |
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59 #else |
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60 |
| 0 | 61 //============================================================================= |
| 62 // MN10300 Simulator | |
| 63 | |
| 64 //----------------------------------------------------------------------------- | |
| 65 // Cache dimensions | |
| 66 | |
| 67 // Data cache | |
| 68 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 69 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 70 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 71 | |
| 72 // Instruction cache | |
| 73 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 74 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 75 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 76 | |
| 77 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 78 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 79 | |
| 80 //----------------------------------------------------------------------------- | |
| 81 // Global control of data cache | |
| 82 | |
| 83 // Enable the data cache | |
| 84 #define HAL_DCACHE_ENABLE() | |
| 85 | |
| 86 // Disable the data cache | |
| 87 #define HAL_DCACHE_DISABLE() | |
| 88 | |
| 89 // Invalidate the entire cache | |
| 90 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 91 | |
| 92 // Synchronize the contents of the cache with memory. | |
| 93 #define HAL_DCACHE_SYNC() | |
| 94 | |
| 95 // Set the data cache refill burst size | |
| 96 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 97 | |
| 98 // Set the data cache write mode | |
| 99 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 100 | |
| 101 // Load the contents of the given address range into the data cache | |
| 102 // and then lock the cache so that it stays there. | |
| 103 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 104 | |
| 105 // Undo a previous lock operation | |
| 106 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 107 | |
| 2 | 108 // Unlock entire cache |
| 109 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 110 | |
| 0 | 111 //----------------------------------------------------------------------------- |
| 112 // Data cache line control | |
| 113 | |
| 114 // Allocate cache lines for the given address range without reading its | |
| 115 // contents from memory. | |
| 116 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 117 | |
| 118 // Write dirty cache lines to memory and invalidate the cache entries | |
| 119 // for the given address range. | |
| 120 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 121 | |
| 122 // Invalidate cache lines in the given range without writing to memory. | |
| 123 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 124 | |
| 125 // Write dirty cache lines to memory for the given address range. | |
| 126 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 127 | |
| 128 // Preread the given range into the cache with the intention of reading | |
| 129 // from it later. | |
| 130 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 131 | |
| 132 // Preread the given range into the cache with the intention of writing | |
| 133 // to it later. | |
| 134 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 135 | |
| 136 // Allocate and zero the cache lines associated with the given range. | |
| 137 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 138 | |
| 139 //----------------------------------------------------------------------------- | |
| 140 // Global control of Instruction cache | |
| 141 | |
| 142 // Enable the instruction cache | |
| 143 #define HAL_ICACHE_ENABLE() | |
| 144 | |
| 145 // Disable the instruction cache | |
| 146 #define HAL_ICACHE_DISABLE() | |
| 147 | |
| 148 // Invalidate the entire cache | |
| 149 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 150 | |
| 151 // Synchronize the contents of the cache with memory. | |
| 152 #define HAL_ICACHE_SYNC() | |
| 153 | |
| 154 // Set the instruction cache refill burst size | |
| 155 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 156 | |
| 157 // Load the contents of the given address range into the instruction cache | |
| 158 // and then lock the cache so that it stays there. | |
| 159 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 160 | |
| 161 // Undo a previous lock operation | |
| 162 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 163 | |
| 2 | 164 // Unlock entire cache |
| 165 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 166 | |
| 0 | 167 //----------------------------------------------------------------------------- |
| 168 // Instruction cache line control | |
| 169 | |
| 170 // Invalidate cache lines in the given range without writing to memory. | |
| 171 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 172 | |
| 173 #endif | |
| 174 | |
| 175 | |
| 2 | 176 //----------------------------------------------------------------------------- |
| 177 // Check that a supported configuration has actually defined some macros. | |
| 178 | |
| 179 #ifndef HAL_DCACHE_ENABLE | |
| 180 | |
| 181 #error Unsupported MN10300 configuration | |
| 182 | |
| 183 #endif | |
| 0 | 184 |
| 185 //----------------------------------------------------------------------------- | |
| 186 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 187 // End of hal_cache.h |
