Mercurial > nand-ecoscentric

annotate packages/hal/mn10300/am31/current/include/variant.inc @ 36:e97d78785e2d ecos-sw-1999-09-12

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Merge from eCos master repository on 1999-09-12-15:40:34-BST
author jlarmour
date Sun, 12 Sep 1999 15:26:05 +0000
parents 641b639be825
children 7a6ac9edc838
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## AM31 assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Cygnus eCos Public License
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14 # Version 1.0 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://sourceware.cygnus.com/ecos
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Cygnus Operating System, released
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24 # September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Cygnus. Portions created
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27 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 ##=============================================================================
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32 #######DESCRIPTIONBEGIN####
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33 ##
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34 ## Author(s): nickg
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35 ## Contributors: nickg
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36 ## Date: 1999-04-06
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37 ## Purpose: AM31 definitions.
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38 ## Description: This file contains various definitions and macros that are
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39 ## useful for writing assembly code for the AM31 CPU variant.
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40 ## Usage:
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41 ## #include <cyg/hal/variant.inc>
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42 ## ...
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43 ##
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44 ##
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45 ######DESCRIPTIONEND####
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46 ##
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47 ##=============================================================================
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48
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49 #include <pkgconf/hal.h>
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50
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51 #include <cyg/hal/platform.inc>
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52
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53
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54 #------------------------------------------------------------------------------
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55 # Register definitions
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56
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57 #define NMICR 0x34000100 // NMI control register
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58 #define DCR 0x20000030 // Debug control register
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59 #define ISR 0x20000034 // Interrupt control register
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60
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61 #define DCR_DE 0x0010 // DE bit in DCR
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62
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63 #------------------------------------------------------------------------------
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64 # CPU state save and restore macros
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65
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66 .macro hal_cpu_save_all
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67 movm [d2,d3,a2,a3,other],(sp) # push all registers
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68 .endm
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69
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70 .macro hal_cpu_load_all
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71 movm (sp),[d2,d3,a2,a3,other] # pop regs
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72 .endm
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73
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74 .macro hal_cpu_get_psw reg
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75 mov psw,\reg
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76 .endm
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77
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78 .macro hal_cpu_set_psw reg
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79 mov \reg,psw
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80 .endm
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81
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82 ##-----------------------------------------------------------------------------
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83 # It appears that there is an undocumented extra bit
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84 # in the PSW that masks the delivery of NMIs. It is in
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85 # the upper 16 bits of the register that we cannot access
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86 # directly. So, to clear it, we must set up a fake interrupt
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87 # state and do an RTI to load the PSW. We need to do this if
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88 # we are going to be able to set breakpoints in NMI handlers.
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89
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90 .macro hal_cpu_clear_nmid
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91 mov PSW,d3 # D3 = PSW
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92 and 0xFFFF,d3
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93 mov nmid\@,d2 # D2 = Next PC
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94 movm [d2,d3],(sp) # Push
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95 rti # and load into CPU
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96 nmid\@:
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97 .endm
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98
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99
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100 ##-----------------------------------------------------------------------------
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101 ## Register addresses and initialization values
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102
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103 .equ IOBCTR ,0x32000010
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104 .equ MEMCTR0 ,0x32000020
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105 .equ MEMCTR1 ,0x32000022
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106 .equ MEMCTR2 ,0x32000024
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107 .equ MEMCTR3 ,0x32000026
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108 .equ MEMCTR4 ,0x32000028
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109 .equ MEMCTR5 ,0x3200002a
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110 .equ MEMCTR6 ,0x3200002c
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111 .equ MEMCTR7 ,0x3200002e
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112 .equ DRAMCTR ,0x32000040
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113 .equ REFCNT ,0x32000042
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114
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115 .equ INIT_MEMCTR0,0x1200 # 2wait
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116 .equ INIT_MEMCTR1,0x0120 # 1wait-32bit-
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117 .equ INIT_MEMCTR2,0x0065
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118 .equ INIT_DRAMCTR,0x0287
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119 .equ INIT_REFCNT,0x00eb
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120
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121 .equ P2OUT ,0x36008004
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122 .equ P2MD ,0x36008024
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123 .equ P2SS ,0x36008044
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124 .equ P2DIR ,0x36008064
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125
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126 .equ INIT_P2MD,0xf0
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127 .equ INIT_P2DIR,0xff
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128
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129 #------------------------------------------------------------------------------
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130 # MEMC macros.
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131
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132 #ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
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133
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134 .macro hal_memc_init
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135 mov INIT_MEMCTR0,d2
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136 movhu d2,(MEMCTR0)
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137
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138 mov INIT_MEMCTR1,d2
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139 movhu d2,(MEMCTR1)
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140
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141 mov INIT_MEMCTR2,d2
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142 movhu d2,(MEMCTR2)
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143
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144 mov INIT_REFCNT,d2
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145 movhu d2,(REFCNT)
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146
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147 mov INIT_DRAMCTR,d2
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148 movhu d2,(DRAMCTR)
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149 .endm
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150
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151 #define CYGPKG_HAL_MN10300_MEMC_DEFINED
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152
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153 #endif
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154
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155 ##-----------------------------------------------------------------------------
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156 # Default interrupt decoding macros.
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157
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158 #ifndef CYGPKG_HAL_MN10300_INTC_DEFINED
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159
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160
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161
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162 # initialize all interrupts to disabled
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163 .macro hal_intc_init
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164 .endm
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165
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166 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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167
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168 #define CYG_ISR_TABLE_SIZE 10
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169
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170 .macro hal_intc_decode dreg,areg,dreg1
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171 mov _mn10300_interrupt_control,\areg
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172 movhu (0x100,\areg),\dreg1 # dreg1 = IAGR
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173 mov (0,a2),\dreg # dreg = vector priority
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174 mov \dreg1,(0,a2) # store real vector in saved state
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175 asl 2,\dreg # dreg = byte index of isr
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176 add 12,\dreg # skip NMI vectors
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177 .endm
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178
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179 #else
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180
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181 #define CYG_ISR_TABLE_SIZE 34
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182
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183 # decode the interrupt
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184 .macro hal_intc_decode dreg,areg,dreg1
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185 mov _mn10300_interrupt_control,\areg
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186 movhu (0x100,\areg),\dreg # dreg = IAGR
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187 mov \dreg,(0,a2) # store real vector in saved state
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188 add 12,\dreg # skip NMI vectors
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189 .endm
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190
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191 #endif
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192
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193 #define CYGPKG_HAL_MN10300_INTC_DEFINED
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194
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195 #endif
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196
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197
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198 #------------------------------------------------------------------------------
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199 # Diagnostics macros.
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200
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201 #ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED
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202
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203 .macro hal_diag_init
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204 # Set up LED
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205 mov INIT_P2MD,d2
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206 movbu d2,(P2MD)
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207 mov INIT_P2DIR,d2
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208 movbu d2,(P2DIR)
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209 .endm
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210
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211 .macro hal_diag_excpt_start
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212 .endm
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213
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214 .macro hal_diag_intr_start
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215 .endm
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216
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217 .macro hal_diag_restore
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218 .endm
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219
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220 .macro hal_diag_led val
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221 movm [d2],(sp)
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222 mov \val,d2
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223 asl 4,d2
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224 movbu d2,(P2OUT)
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225 movm (sp),[d2]
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226 .endm
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227
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228
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229 .macro hal_diag_data
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230 led_count: .long 0
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231 led_value: .byte 0x40
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232 led_foo1: .byte 0x00 # Keep alignment to work around compiler/linker bug
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233 led_foo2: .byte 0x00
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234 led_foo3: .byte 0x00
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235 .endm
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236
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237 #define CYGPKG_HAL_MN10300_DIAG_DEFINED
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238
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239 #endif
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240
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241 #------------------------------------------------------------------------------
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242 # Monitor initialization.
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243
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244 #ifndef CYGPKG_HAL_MN10300_MON_DEFINED
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245
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246 .macro hal_mon_init
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247 hal_mon_init_vectors
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248 hal_mon_init_vsr
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249 .endm
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250
36
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251 #if defined(CYG_HAL_STARTUP_ROM) || \
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252 defined(CYGPKG_HAL_MN10300_AM31_SIM)
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253 .macro hal_mon_init_vectors
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254 mov _mn10300_interrupt_vectors,a0
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255 mov __hardware_vector_0,d0
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256 movhu d0,(0,a0)
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257 mov __hardware_vector_1,d0
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258 movhu d0,(4,a0)
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259 mov __hardware_vector_2,d0
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260 movhu d0,(8,a0)
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261 mov __hardware_vector_3,d0
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262 movhu d0,(12,a0)
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263 mov __hardware_vector_4,d0
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264 movhu d0,(16,a0)
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265 mov __hardware_vector_5,d0
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266 movhu d0,(20,a0)
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267 mov __hardware_vector_6,d0
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268 movhu d0,(24,a0)
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269 .endm
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270 #else
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271 .macro hal_mon_init_vectors
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272 .endm
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273 #endif
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274
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275 #if defined(CYG_HAL_STARTUP_RAM)
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276
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277 # init vsr table in SRAM where the ROM
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278 # vectors the interrupts.
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279
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280 .macro hal_mon_init_vsr
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281 mov _hal_vsr_table,a0
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282 mov __default_interrupt_vsr,d0
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283 mov d0,(0,a0)
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284 mov d0,(4,a0)
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285 mov d0,(8,a0)
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286 #ifndef CYG_HAL_USE_ROM_MONITOR_CYGMON
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287 # When using Cygmon, leave level 3 for GDB
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288 # Ctrl-C interrupts.
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289 mov d0,(12,a0)
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290 #endif
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291 mov d0,(16,a0)
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292 mov d0,(20,a0)
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293 mov d0,(24,a0)
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294 mov __default_nmi_vsr,d0
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295 mov d0,(28,a0)
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296 mov __default_trap_vsr,d0
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297 mov d0,(32,a0)
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298 .endm
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299
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300 #else
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301 .macro hal_mon_init_vsr
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302 .endm
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303 #endif
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304
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305 #if !(defined(CYG_HAL_STARTUP_ROM) || \
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306 defined(CYGPKG_HAL_MN10300_AM31_SIM) || \
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307 !defined(CYG_HAL_USE_ROM_MONITOR))
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308
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309 #define CYG_HAL_MN10300_VSR_TABLE_DEFINED
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310
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311 #endif
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312
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313
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314
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315 #define CYGPKG_HAL_MN10300_MON_DEFINED
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316
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317 #endif
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318
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319
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320
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321 #------------------------------------------------------------------------------
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322 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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323 # end of variant.inc