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annotate packages/hal/mips/tx49/current/include/var_cache.h @ 3403:8c8767bb9a62 default tip

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devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
author Ross Younger <wry@ecoscentric.com>
date Sun, 18 Jan 2015 17:59:01 +1300
parents 74dbf4c3f2e1
children
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
208
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors:nickg, jskov
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47 // Date: 2000-05-09
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/imp_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/mips-regs.h>
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64
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65 #include <cyg/hal/plf_cache.h>
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66
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67 //=============================================================================
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68 // Toshiba TX4955
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69
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70 #ifdef CYGPKG_HAL_MIPS_TX4955
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71
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72 //-----------------------------------------------------------------------------
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73 // Cache dimensions
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74
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75 // Data cache
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76 #define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
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77 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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78 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
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79
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80 // Instruction cache
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81 #define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
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82 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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83 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
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84
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85 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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86 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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87
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88 #define HAL_MIPS_CACHE_INSN_USES_LSB
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89
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90 //-----------------------------------------------------------------------------
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91 // Cache controls
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92
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93 // Register $16 is Config register (controls cache state)
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94
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95 // Config Register fields
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96 #define CYGARC_REG_CONFIG_ICE 0x00020000 // Instruction cache enable
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97 #define CYGARC_REG_CONFIG_DCE 0x00010000 // Data cache enable
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98
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99
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100 //-----------------------------------------------------------------------------
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101 // Global control of data cache
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102
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103 // Enable the data cache
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104 // This uses a bit in the config register, which is TX49 specific.
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105 #define HAL_DCACHE_ENABLE_DEFINED
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106 #define HAL_DCACHE_ENABLE() \
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107 CYG_MACRO_START \
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108 cyg_uint32 tmp; \
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109 asm volatile ("mfc0 %0,$16;" \
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110 "and %0,%0,%1;" \
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111 "mtc0 %0,$16;" \
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112 : "=&r" (tmp) \
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113 : "r" (~CYGARC_REG_CONFIG_DCE) \
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114 ); \
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115 CYG_MACRO_END
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116
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117 // Disable the data cache
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118 #define HAL_DCACHE_DISABLE_DEFINED
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119 #define HAL_DCACHE_DISABLE() \
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120 CYG_MACRO_START \
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121 cyg_uint32 tmp; \
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122 asm volatile ("mfc0 %0,$16;" \
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123 "or %0,%0,%1;" \
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124 "mtc0 %0,$16;" \
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125 : "=&r" (tmp) \
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126 : "r" (CYGARC_REG_CONFIG_DCE) \
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127 ); \
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128 CYG_MACRO_END
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129
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130 #define HAL_DCACHE_IS_ENABLED_DEFINED
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131 #define HAL_DCACHE_IS_ENABLED(_state_) \
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132 CYG_MACRO_START \
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133 cyg_uint32 _cstate_; \
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134 asm volatile ( "mfc0 %0,$16\n" \
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135 : "=r"(_cstate_) \
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136 ); \
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137 if( _cstate_ & CYGARC_REG_CONFIG_DCE) \
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138 _state_ = 0; \
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139 else \
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140 _state_ = 1; \
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141 CYG_MACRO_END
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142
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143 // Architecture HAL defines other operations
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144
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145
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146 //-----------------------------------------------------------------------------
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147 // Global control of Instruction cache
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148
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149 // Enable the instruction cache
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150 #define HAL_ICACHE_ENABLE_DEFINED
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151 #define HAL_ICACHE_ENABLE() \
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152 CYG_MACRO_START \
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153 cyg_uint32 tmp; \
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154 asm volatile ("mfc0 %0,$16;" \
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155 "and %0,%0,%1;" \
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156 "mtc0 %0,$16;" \
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157 : "=&r" (tmp) \
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158 : "r" (~CYGARC_REG_CONFIG_ICE) \
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159 ); \
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160 CYG_MACRO_END
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161
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162 // Disable the instruction cache
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163 #define HAL_ICACHE_DISABLE_DEFINED
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164 #define HAL_ICACHE_DISABLE() \
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165 CYG_MACRO_START \
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166 cyg_uint32 tmp; \
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167 asm volatile ("mfc0 %0,$16;" \
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168 "or %0,%0,%1;" \
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169 "mtc0 %0,$16;" \
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170 : "=&r" (tmp) \
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171 : "r" (CYGARC_REG_CONFIG_ICE) \
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172 ); \
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173 CYG_MACRO_END
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174
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175 #define HAL_ICACHE_IS_ENABLED_DEFINED
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176 #define HAL_ICACHE_IS_ENABLED(_state_) \
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177 CYG_MACRO_START \
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178 cyg_uint32 _cstate_; \
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179 asm volatile ( "mfc0 %0,$16\n" \
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180 : "=r"(_cstate_) \
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181 ); \
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182 if( _cstate_ & CYGARC_REG_CONFIG_ICE) \
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183 _state_ = 0; \
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184 else \
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185 _state_ = 1; \
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186 CYG_MACRO_END
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187
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188 // TX49 cache instruction must not affect the line it executes out of,
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189 // so disable instruction cache before invalidating it.
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190 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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191 #define HAL_ICACHE_INVALIDATE_ALL() \
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192 CYG_MACRO_START \
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193 register CYG_ADDRESS _baddr_ = 0x80000000; \
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194 register CYG_ADDRESS _addr_ = 0x80000000; \
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195 register CYG_WORD _state_; \
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196 _HAL_ASM_SET_MIPS_ISA(3); \
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197 HAL_ICACHE_IS_ENABLED( _state_ ); \
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198 HAL_ICACHE_DISABLE(); \
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199 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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200 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
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201 if( _state_ ) HAL_ICACHE_ENABLE(); \
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202 _HAL_ASM_SET_MIPS_ISA(0); \
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203 CYG_MACRO_END
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204
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205 // Architecture HAL defines other operations
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206
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207 #endif // CYGPKG_HAL_MIPS_TX4955
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208
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209
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210 //-----------------------------------------------------------------------------
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211 #endif // ifndef CYGONCE_VAR_CACHE_H
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212 // End of var_cache.h