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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3
4 //=============================================================================
5 //
6 // hal_cache.h
7 //
8 // HAL cache control API
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): nickg
36 // Contributors: nickg
37 // Date: 1998-02-17
38 // Purpose: Cache control API
39 // Description: The macros defined here provide the HAL APIs for handling
40 // cache control operations.
41 // Usage:
42 // #include <cyg/hal/hal_cache.h>
43 // ...
44 //
45 //
46 //####DESCRIPTIONEND####
47 //
48 //=============================================================================
49
50 #include <pkgconf/hal.h>
51 #include <cyg/infra/cyg_type.h>
52 #include <cyg/hal/ppc_regs.h>
53
54 //=============================================================================
55 // PowerPC simulator
56
57 #ifdef CYG_HAL_POWERPC_SIM
58
59 //-----------------------------------------------------------------------------
60 // Cache dimensions
61
62 // Data cache
63 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
64 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
65 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
66
67 // Instruction cache
68 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
69 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
70 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
71
72 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
73 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
74
75 //-----------------------------------------------------------------------------
76 // Global control of data cache
77
78 // Enable the data cache
79 #define HAL_DCACHE_ENABLE()
80
81 // Disable the data cache
82 #define HAL_DCACHE_DISABLE()
83
84 // Invalidate the entire cache
85 #define HAL_DCACHE_INVALIDATE_ALL()
86
87 // Synchronize the contents of the cache with memory.
88 #define HAL_DCACHE_SYNC()
89
90 // Set the data cache refill burst size
91 //#define HAL_DCACHE_BURST_SIZE(_size_)
92
93 // Set the data cache write mode
94 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
95
96 //#define HAL_DCACHE_WRITETHRU_MODE 0
97 //#define HAL_DCACHE_WRITEBACK_MODE 1
98
99 // Load the contents of the given address range into the data cache
100 // and then lock the cache so that it stays there.
101 //#define HAL_DCACHE_LOCK(_base_, _size_)
102
103 // Undo a previous lock operation
104 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
105
106 //-----------------------------------------------------------------------------
107 // Data cache line control
108
109 // Allocate cache lines for the given address range without reading its
110 // contents from memory.
111 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
112
113 // Write dirty cache lines to memory and invalidate the cache entries
114 // for the given address range.
115 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
116
117 // Invalidate cache lines in the given range without writing to memory.
118 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
119
120 // Write dirty cache lines to memory for the given address range.
121 //#define HAL_DCACHE_STORE( _base_ , _size_ )
122
123 // Preread the given range into the cache with the intention of reading
124 // from it later.
125 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
126
127 // Preread the given range into the cache with the intention of writing
128 // to it later.
129 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
130
131 // Allocate and zero the cache lines associated with the given range.
132 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
133
134 //-----------------------------------------------------------------------------
135 // Global control of Instruction cache
136
137 // Enable the instruction cache
138 #define HAL_ICACHE_ENABLE()
139
140 // Disable the instruction cache
141 #define HAL_ICACHE_DISABLE()
142
143 // Invalidate the entire cache
144 #define HAL_ICACHE_INVALIDATE_ALL()
145
146 // Synchronize the contents of the cache with memory.
147 #define HAL_ICACHE_SYNC()
148
149 // Set the instruction cache refill burst size
150 //#define HAL_ICACHE_BURST_SIZE(_size_)
151
152 // Load the contents of the given address range into the instruction cache
153 // and then lock the cache so that it stays there.
154 //#define HAL_ICACHE_LOCK(_base_, _size_)
155
156 // Undo a previous lock operation
157 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
158
159 //-----------------------------------------------------------------------------
160 // Instruction cache line control
161
162 // Invalidate cache lines in the given range without writing to memory.
163 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
164
165 #endif
166
167
168 //=============================================================================
169 // Motorola MP860
170
171 #ifdef CYG_HAL_POWERPC_MP860
172
173 //-----------------------------------------------------------------------------
174 // Cache dimensions
175
176 // Data cache
177 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
178 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
179 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
180
181 // Instruction cache
182 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
183 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
184 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
185
186 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
187 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
188
189 //-----------------------------------------------------------------------------
190 // Global control of data cache
191
192 // FIXME:
193 // The revision A.2 MPC860 might do all sorts of horrible things to
194 // the cache contents in a few specific (and unlikely)
195 // situations. However, as I don't feel like being bitten by these,
196 // leave caches disabled at all times.
197 #if 1
198 // Enable the data cache
199 #define HAL_DCACHE_ENABLE()
200
201 // Disable the data cache
202 #define HAL_DCACHE_DISABLE()
203
204 // Invalidate the entire cache
205 #define HAL_DCACHE_INVALIDATE_ALL()
206
207 // Synchronize the contents of the cache with memory.
208 #define HAL_DCACHE_SYNC()
209 #else
210 // Enable the data cache
211 #define HAL_DCACHE_ENABLE() \
212 asm volatile ("sync;" \
213 "mtspr 568, %0;" /* DC_CST */ \
214 : : "r" (DC_CMD_CE))
215
216 // Disable the data cache
217 #define HAL_DCACHE_DISABLE() \
218 asm volatile ("sync;" \
219 "mtspr 568, %0;" /* DC_CST */ \
220 : : "r" (DC_CMD_CD))
221
222 // Invalidate the entire cache
223 #define HAL_DCACHE_INVALIDATE_ALL() \
224 asm volatile ("sync;" \
225 "mtspr 568, %0;" /* DC_CST */ \
226 : : "r" (DC_CMD_IA))
227
228 // Synchronize the contents of the cache with memory.
229 #define HAL_DCACHE_SYNC() \
230 CYG_MACRO_START \
231 int i; \
232 int cmd = DC_CMD_FL; \
233 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
234 asm volatile ("sync;" \
235 "mtspr 569, %0;" /* DC_ADR */ \
236 "mtspr 568, %2;" /* DC_CST */ \
237 "mtspr 569, %1;" /* DC_ADR */ \
238 "mtspr 568, %2;" /* DC_CST */ \
239 : /* no output */ \
240 : "r" (i << 4), "r" (0x1000 | (i << 4)), \
241 "r" (cmd)); \
242 } \
243 CYG_MACRO_END
244 #endif
245
246 // Set the data cache refill burst size
247 //#define HAL_DCACHE_BURST_SIZE(_size_)
248
249 // Set the data cache write mode
250 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
251
252 //#define HAL_DCACHE_WRITETHRU_MODE 0
253 //#define HAL_DCACHE_WRITEBACK_MODE 1
254
255 // Load the contents of the given address range into the data cache
256 // and then lock the cache so that it stays there.
257 //#define HAL_DCACHE_LOCK(_base_, _size_)
258
259 // Undo a previous lock operation
260 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
261
262 //-----------------------------------------------------------------------------
263 // Data cache line control
264
265 // Allocate cache lines for the given address range without reading its
266 // contents from memory.
267 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
268
269 // Write dirty cache lines to memory and invalidate the cache entries
270 // for the given address range.
271 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
272
273 // Invalidate cache lines in the given range without writing to memory.
274 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
275
276 // Write dirty cache lines to memory for the given address range.
277 //#define HAL_DCACHE_STORE( _base_ , _size_ )
278
279 // Preread the given range into the cache with the intention of reading
280 // from it later.
281 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
282
283 // Preread the given range into the cache with the intention of writing
284 // to it later.
285 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
286
287 // Allocate and zero the cache lines associated with the given range.
288 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
289
290 //-----------------------------------------------------------------------------
291 // Global control of Instruction cache
292
293 // FIXME:
294 // The revision A.2 MPC860 might do all sorts of horrible things to
295 // the cache contents in a few specific (and unlikely)
296 // situations. However, as I don't feel like being bitten by these,
297 // leave caches disabled at all times.
298 #if 1
299 // Enable the instruction cache
300 #define HAL_ICACHE_ENABLE()
301
302 // Disable the instruction cache
303 #define HAL_ICACHE_DISABLE()
304
305 // Invalidate the entire cache
306 #define HAL_ICACHE_INVALIDATE_ALL()
307
308 // Synchronize the contents of the cache with memory.
309 #define HAL_ICACHE_SYNC()
310 #else
311 // Enable the instruction cache
312 #define HAL_ICACHE_ENABLE() \
313 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
314 "isync" \
315 : : "r" (IC_CMD_CE))
316
317 // Disable the instruction cache
318 #define HAL_ICACHE_DISABLE() \
319 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
320 "isync" \
321 : : "r" (IC_CMD_CD))
322
323 // Invalidate the entire cache
324 #define HAL_ICACHE_INVALIDATE_ALL() \
325 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
326 "isync" \
327 : : "r" (IC_CMD_IA))
328
329 // Synchronize the contents of the cache with memory.
330 #define HAL_ICACHE_SYNC()
331 #endif
332
333 // Set the instruction cache refill burst size
334 //#define HAL_ICACHE_BURST_SIZE(_size_)
335
336 // Load the contents of the given address range into the instruction cache
337 // and then lock the cache so that it stays there.
338 //#define HAL_ICACHE_LOCK(_base_, _size_)
339
340 // Undo a previous lock operation
341 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
342
343 //-----------------------------------------------------------------------------
344 // Instruction cache line control
345
346 // Invalidate cache lines in the given range without writing to memory.
347 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
348
349 #endif
350
351 //-----------------------------------------------------------------------------
352 #endif // ifndef CYGONCE_HAL_CACHE_H
353 // End of hal_cache.h