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annotate packages/hal/powerpc/arch/current/include/hal_cache.h @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/hal_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal.h>
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51 #include <cyg/infra/cyg_type.h>
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52 #include <cyg/hal/ppc_regs.h>
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53
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54 //=============================================================================
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55 // PowerPC simulator
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56
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57 #ifdef CYG_HAL_POWERPC_SIM
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58
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59 //-----------------------------------------------------------------------------
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60 // Cache dimensions
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61
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62 // Data cache
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63 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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64 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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65 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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66
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67 // Instruction cache
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68 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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69 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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70 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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71
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72 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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73 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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74
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75 //-----------------------------------------------------------------------------
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76 // Global control of data cache
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77
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78 // Enable the data cache
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79 #define HAL_DCACHE_ENABLE()
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80
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81 // Disable the data cache
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82 #define HAL_DCACHE_DISABLE()
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83
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84 // Invalidate the entire cache
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85 #define HAL_DCACHE_INVALIDATE_ALL()
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86
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87 // Synchronize the contents of the cache with memory.
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88 #define HAL_DCACHE_SYNC()
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89
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90 // Set the data cache refill burst size
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91 //#define HAL_DCACHE_BURST_SIZE(_size_)
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92
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93 // Set the data cache write mode
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94 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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95
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96 //#define HAL_DCACHE_WRITETHRU_MODE 0
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97 //#define HAL_DCACHE_WRITEBACK_MODE 1
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98
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99 // Load the contents of the given address range into the data cache
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100 // and then lock the cache so that it stays there.
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101 //#define HAL_DCACHE_LOCK(_base_, _size_)
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102
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103 // Undo a previous lock operation
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104 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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105
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106 //-----------------------------------------------------------------------------
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107 // Data cache line control
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108
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109 // Allocate cache lines for the given address range without reading its
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110 // contents from memory.
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111 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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112
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113 // Write dirty cache lines to memory and invalidate the cache entries
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114 // for the given address range.
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115 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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116
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117 // Invalidate cache lines in the given range without writing to memory.
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118 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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119
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120 // Write dirty cache lines to memory for the given address range.
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121 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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122
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123 // Preread the given range into the cache with the intention of reading
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124 // from it later.
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125 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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126
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127 // Preread the given range into the cache with the intention of writing
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128 // to it later.
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129 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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130
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131 // Allocate and zero the cache lines associated with the given range.
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132 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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133
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134 //-----------------------------------------------------------------------------
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135 // Global control of Instruction cache
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136
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137 // Enable the instruction cache
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138 #define HAL_ICACHE_ENABLE()
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139
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140 // Disable the instruction cache
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141 #define HAL_ICACHE_DISABLE()
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142
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143 // Invalidate the entire cache
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144 #define HAL_ICACHE_INVALIDATE_ALL()
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145
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146 // Synchronize the contents of the cache with memory.
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147 #define HAL_ICACHE_SYNC()
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148
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149 // Set the instruction cache refill burst size
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150 //#define HAL_ICACHE_BURST_SIZE(_size_)
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151
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152 // Load the contents of the given address range into the instruction cache
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153 // and then lock the cache so that it stays there.
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154 //#define HAL_ICACHE_LOCK(_base_, _size_)
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155
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156 // Undo a previous lock operation
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157 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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158
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159 //-----------------------------------------------------------------------------
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160 // Instruction cache line control
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161
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162 // Invalidate cache lines in the given range without writing to memory.
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163 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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164
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165 #endif
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166
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167
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168 //=============================================================================
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169 // Motorola MP860
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170
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171 #ifdef CYG_HAL_POWERPC_MP860
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172
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173 //-----------------------------------------------------------------------------
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174 // Cache dimensions
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175
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176 // Data cache
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177 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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178 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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179 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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180
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181 // Instruction cache
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182 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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183 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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184 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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185
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186 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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187 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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188
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189 //-----------------------------------------------------------------------------
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190 // Global control of data cache
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191
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192 // FIXME:
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193 // The revision A.2 MPC860 might do all sorts of horrible things to
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194 // the cache contents in a few specific (and unlikely)
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195 // situations. However, as I don't feel like being bitten by these,
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196 // leave caches disabled at all times.
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197 #if 1
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198 // Enable the data cache
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199 #define HAL_DCACHE_ENABLE()
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200
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201 // Disable the data cache
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202 #define HAL_DCACHE_DISABLE()
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203
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204 // Invalidate the entire cache
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205 #define HAL_DCACHE_INVALIDATE_ALL()
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206
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207 // Synchronize the contents of the cache with memory.
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208 #define HAL_DCACHE_SYNC()
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209 #else
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210 // Enable the data cache
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211 #define HAL_DCACHE_ENABLE() \
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212 asm volatile ("sync;" \
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213 "mtspr 568, %0;" /* DC_CST */ \
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214 : : "r" (DC_CMD_CE))
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215
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216 // Disable the data cache
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217 #define HAL_DCACHE_DISABLE() \
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218 asm volatile ("sync;" \
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219 "mtspr 568, %0;" /* DC_CST */ \
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220 : : "r" (DC_CMD_CD))
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221
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222 // Invalidate the entire cache
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223 #define HAL_DCACHE_INVALIDATE_ALL() \
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224 asm volatile ("sync;" \
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225 "mtspr 568, %0;" /* DC_CST */ \
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226 : : "r" (DC_CMD_IA))
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227
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228 // Synchronize the contents of the cache with memory.
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229 #define HAL_DCACHE_SYNC() \
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230 CYG_MACRO_START \
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231 int i; \
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232 int cmd = DC_CMD_FL; \
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233 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
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234 asm volatile ("sync;" \
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235 "mtspr 569, %0;" /* DC_ADR */ \
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236 "mtspr 568, %2;" /* DC_CST */ \
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237 "mtspr 569, %1;" /* DC_ADR */ \
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238 "mtspr 568, %2;" /* DC_CST */ \
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239 : /* no output */ \
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240 : "r" (i << 4), "r" (0x1000 | (i << 4)), \
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241 "r" (cmd)); \
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242 } \
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243 CYG_MACRO_END
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244 #endif
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245
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246 // Set the data cache refill burst size
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247 //#define HAL_DCACHE_BURST_SIZE(_size_)
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248
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249 // Set the data cache write mode
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250 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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251
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252 //#define HAL_DCACHE_WRITETHRU_MODE 0
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253 //#define HAL_DCACHE_WRITEBACK_MODE 1
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254
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255 // Load the contents of the given address range into the data cache
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256 // and then lock the cache so that it stays there.
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257 //#define HAL_DCACHE_LOCK(_base_, _size_)
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258
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259 // Undo a previous lock operation
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260 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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261
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262 //-----------------------------------------------------------------------------
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263 // Data cache line control
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264
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265 // Allocate cache lines for the given address range without reading its
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266 // contents from memory.
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267 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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268
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269 // Write dirty cache lines to memory and invalidate the cache entries
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270 // for the given address range.
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271 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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272
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273 // Invalidate cache lines in the given range without writing to memory.
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274 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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275
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276 // Write dirty cache lines to memory for the given address range.
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277 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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278
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279 // Preread the given range into the cache with the intention of reading
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280 // from it later.
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281 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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282
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283 // Preread the given range into the cache with the intention of writing
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284 // to it later.
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285 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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286
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287 // Allocate and zero the cache lines associated with the given range.
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288 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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289
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290 //-----------------------------------------------------------------------------
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291 // Global control of Instruction cache
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292
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293 // FIXME:
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294 // The revision A.2 MPC860 might do all sorts of horrible things to
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295 // the cache contents in a few specific (and unlikely)
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296 // situations. However, as I don't feel like being bitten by these,
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297 // leave caches disabled at all times.
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298 #if 1
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299 // Enable the instruction cache
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300 #define HAL_ICACHE_ENABLE()
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301
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302 // Disable the instruction cache
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303 #define HAL_ICACHE_DISABLE()
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304
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305 // Invalidate the entire cache
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306 #define HAL_ICACHE_INVALIDATE_ALL()
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307
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308 // Synchronize the contents of the cache with memory.
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309 #define HAL_ICACHE_SYNC()
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310 #else
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311 // Enable the instruction cache
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312 #define HAL_ICACHE_ENABLE() \
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313 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
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314 "isync" \
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315 : : "r" (IC_CMD_CE))
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316
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317 // Disable the instruction cache
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318 #define HAL_ICACHE_DISABLE() \
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319 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
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320 "isync" \
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321 : : "r" (IC_CMD_CD))
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322
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323 // Invalidate the entire cache
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324 #define HAL_ICACHE_INVALIDATE_ALL() \
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325 asm volatile ("mtspr 560, %0;" /* IC_CST */ \
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326 "isync" \
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327 : : "r" (IC_CMD_IA))
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328
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329 // Synchronize the contents of the cache with memory.
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330 #define HAL_ICACHE_SYNC()
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331 #endif
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332
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333 // Set the instruction cache refill burst size
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334 //#define HAL_ICACHE_BURST_SIZE(_size_)
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335
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336 // Load the contents of the given address range into the instruction cache
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337 // and then lock the cache so that it stays there.
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338 //#define HAL_ICACHE_LOCK(_base_, _size_)
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339
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340 // Undo a previous lock operation
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341 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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342
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343 //-----------------------------------------------------------------------------
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344 // Instruction cache line control
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345
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346 // Invalidate cache lines in the given range without writing to memory.
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347 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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348
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349 #endif
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350
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351 //-----------------------------------------------------------------------------
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352 #endif // ifndef CYGONCE_HAL_CACHE_H
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353 // End of hal_cache.h