--- a/packages/devs/eth/arm/lpc2xxx/current/ChangeLog
+++ b/packages/devs/eth/arm/lpc2xxx/current/ChangeLog
@@ -1,3 +1,8 @@
+2011-02-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/lpc2xxx_eth.cdl, src/if_lpc2xxx.c: Added support for
+	LPC17xx CPUs.
+
 2008-09-09  Uwe Kindler  <uwe_kindler@web.de>
 
 	* LPC2xxx ethernet driver package created
@@ -8,7 +13,7 @@ 2008-09-09  Uwe Kindler  <uwe_kindler@we
 // ####GPLCOPYRIGHTBEGIN####                                                
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
 //
 // This program is free software; you can redistribute it and/or modify     
 // it under the terms of the GNU General Public License as published by     

--- a/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl
+++ b/packages/devs/eth/arm/lpc2xxx/current/cdl/lpc2xxx_eth.cdl
@@ -40,6 +40,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):    Uwe Kindler
+# Contributors: ilijak
 # Date:         2008-08-05
 #
 #####DESCRIPTIONEND####
@@ -80,19 +81,32 @@ cdl_package CYGPKG_DEVS_ETH_ARM_LPC2XXX 
              debug messages while an application is loaded and run via GDB
              TCP/IP connection"
     }
-    
+
+    # For backward compatibility with LPC24xx platforms
+    # that do not have CYGNUM_HAL_IRQ_PRIORITY_LEVELS defined.
+    cdl_option CYGNUM_DEVS_ETH_IRQ_PRIORITY_LEVELS {
+        display       "Interrupt priority levels"
+        flavor        data
+        calculated    { CYGNUM_HAL_IRQ_PRIORITY_LEVELS ? CYGNUM_HAL_IRQ_PRIORITY_LEVELS : 15 }
+        description   "
+            For backward compatibility with LPC 24XX plarforms that do
+            not have CYGNUM_HAL_IRQ_PRIORITY_LEVELS defined."
+    }
+
     cdl_option CYGPKG_DEVS_ETH_ARM_LPC2XXX_INTPRIO {
         display       "Interrupt priority"
         flavor        data
-        legal_values  0 to 15
-        default_value 15
+        legal_values  0 to CYGNUM_DEVS_ETH_IRQ_PRIORITY_LEVELS-1
+        default_value CYGNUM_DEVS_ETH_IRQ_PRIORITY_LEVELS-1
         description   "
-            This option selects the interrupt priority for the EMAC interrupts. 
-            There are 16 priority levels corresponding to the values 0 through 
-            15 decimal, of which 15 is the lowest priority. The reset value of 
-            these registers defaults all interrupts to the lowest priority, 
-            allowing a single write to elevate the priority of an 
-            individual interrupt."
+            This option selects the interrupt priority for the EMAC
+            interrupts.  There are CYGNUM_DEVS_ETH_IRQ_PRIORITY_LEVELS
+            priority levels corresponding to the values 0 through
+            CYGNUM_DEVS_ETH_IRQ_PRIORITY_LEVELS-1 decimal, of which
+            the highest value is the lowest priority. The reset value
+            of these registers defaults all interrupts to the lowest
+            priority, allowing a single write to elevate the priority
+            of an individual interrupt."
     }
 
     cdl_option CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS {

--- a/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c
+++ b/packages/devs/eth/arm/lpc2xxx/current/src/if_lpc2xxx.c
@@ -38,7 +38,7 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    Uwe Kindler
-// Contributors:
+// Contributors: ilijak
 // Date:         2008-08-10
 // Description:  Hardware driver for LPC2xxx on-chip EMAC peripheral
 //
@@ -254,9 +254,17 @@
 //===========================================================================
 //                ETHERNET RAM AND DMA CONFIGURATION
 //===========================================================================
-#define EMAC_RAM_BASE          0x7FE00000
-#define EMAC_RAM_SIZE          0x00004000
-#define EMAC_BLOCK_SIZE        0x600
+#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB
+# include <cyg/infra/cyg_type.h>
+# define EMAC_RAM_MEM_SECTION   CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_LPC_EMAC_MEM_SECTION)
+# define EMAC_RAM_BASE          (&emac_ahb_ram)
+# define EMAC_RAM_SIZE          sizeof(emac_ahb_ram)
+# define EMAC_BLOCK_SIZE        CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE
+#else // Backward compatibility
+# define EMAC_RAM_BASE          0x7FE00000
+# define EMAC_RAM_SIZE          0x00004000
+# define EMAC_BLOCK_SIZE        0x600
+#endif // CYGHWR_HAL_LPC_EMAC_RAM_AHB
 
 //
 // EMAC Descriptor TX and RX Control fields
@@ -345,6 +353,9 @@ typedef struct eth_ram_cfg_st
     volatile eth_buf_t    rx_buf[CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS];
 } eth_ram_cfg_t;
 
+#ifdef CYGHWR_HAL_LPC_EMAC_RAM_AHB
+volatile static eth_ram_cfg_t emac_ahb_ram EMAC_RAM_MEM_SECTION;
+#endif
 
 #if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL < 3
 #if CYGPKG_DEVS_ETH_ARM_LPC2XXX_DEBUG_LEVEL > 0