Mercurial > nand-ecoscentric
changeset 3140:098660d4164c
* cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Add support for LPC-L2294-8M
board: new CDL component CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT
with CDL option CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE.
* include/hal_platform_setup.h: Add support for LPC-L2294-8M board.
* include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_{rom,ram}.{h,ldi}: Define
RAM size with new CDL option.
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--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/ChangeLog @@ -1,3 +1,13 @@ +2010-11-03 JF Argentino <jf.argentino@osean.fr> +2010-11-24 Sergei Gavrikov <sergei.gavrikov@gmail.com> + + * cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Add support for LPC-L2294-8M + board: new CDL component CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT + with CDL option CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE. + * include/hal_platform_setup.h: Add support for LPC-L2294-8M board. + * include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_{rom,ram}.{h,ldi}: Define + RAM size with new CDL option. + 2009-02-02 Sergei Gavrikov <sergei.gavrikov@gmail.com> * cdl/hal_arm_lpc2xxx_olpcl2294.cdl: Expanded a list the legal baud
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/cdl/hal_arm_lpc2xxx_olpcl2294.cdl @@ -3,7 +3,7 @@ # hal_arm_lpc2xxx_olpcl2294.cdl # # ARM LPC2XXX OLPCL2294 development board package configuration -# data +# data, for both 1MB and 8MB of external RAM # # ==================================================================== ## ####ECOSGPLCOPYRIGHTBEGIN#### @@ -49,14 +49,14 @@ # ==================================================================== cdl_package CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 { - display "Olimex LPC-L2294-1MB development board HAL" + display "Olimex LPC-L2294 development board HAL" parent CYGPKG_HAL_ARM_LPC2XXX define_header hal_arm_lpc2xxx_olpcl2294.h include_dir cyg/hal hardware description " The OLPCL2294 HAL package provides the support needed to run - eCos on Olimex LPC-L2294-1MB development board." + eCos on Olimex LPC-L2294-1MB or LPC-L2294-8MB development board." compile olpcl2294_misc.c @@ -71,6 +71,23 @@ cdl_package CYGPKG_HAL_ARM_LPC2XXX_OLPCL puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" } + cdl_component CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT { + display "OLPCL2294 variant used" + flavor data + default_value { "OLPCL2294_1M" } + legal_values { "OLPCL2294_1M" "OLPCL2294_8M" } + define -file system.h CYGHWR_OLIMEX_BOARD + description "Choose the OLIMEX LPC-L2294 board variant" + + cdl_option CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE { + display "External RAM size" + flavor data + calculated { is_substr(CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_VARIANT, "1M") ? + 0x100000 : 0x800000 } + description "The installed RAM size depends on the board variant" + } + } + cdl_component CYG_HAL_STARTUP { display "Startup type" flavor data
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/hal_platform_setup.h @@ -138,8 +138,9 @@ 1: // memories, while memory chips capable of accepting 16 or 32 bit wide // data will work with RBLE = 1. // - // BANK0: 2M FLASH - // TE28F160C3BD70 (1024Kx16 x 1, 70nS) + // BANK0: FLASH memory + // -TE28F160C3BD70 (1024Kx16 x 1 = 2MB, 70nS) for 1MB RAM version + // -TE28F320C3BD70 (2048Kx16 x 1 = 4MB, 70ns) for 8MB RAM version ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0 ldr r1,= (0x3 << 0) /* IDCY=3, idle timing */\ | (0x4 << 5) /* WST1=4, read timing */\ @@ -148,16 +149,28 @@ 1: | (0x1 << 28) /* MW=1, 16-bits */ str r1,[r0] - // BANK1: 1M RAM - // K6R4016V1D (512Kx16 x 2, 10nS) - ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1 + // BANK1: external RAM // Warning: changed these timings, you can fall dramatically the eCos // kernel performance. Check it then using the eCos 'tm_basic' test. + // TODO A way to make the timing value dependent of CCLK + ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1 +#if defined (CYGHWR_OLIMEX_BOARD_OLPCL2294_1M) + // 1MB version uses K6R4016V1D (512Kx16 x 2, 10nS) ldr r1,= (0x0 << 0) /* IDCY=0, idle cycles */\ | (0x0 << 5) /* WST1=0, read timing */\ | (0x1 << 10) /* RBLE=1 */\ | (0x0 << 11) /* WST2=0, write timing */\ | (0x2 << 28) /* MW=2, 32-bits */ +#elif defined (CYGHWR_OLIMEX_BOARD_OLPCL2294_8M) + // 8MB version uses a K1S321611C (2048Kx16 x 2, 70ns) + ldr r1,= (0x3 << 0) /* IDCY=3, idle cycles TODO */\ + | (0x4 << 5) /* WST1=4, read timing */\ + | (0x1 << 10) /* RBLE=1 */\ + | (0x4 << 11) /* WST2=4, write timing */\ + | (0x2 << 28) /* MW=2, 32-bits */ +#else +#error Board not supported, OLIMEX LPC-L2294 1M or 8M only for now. +#endif str r1,[r0] // BANK2: Ethernet
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.h @@ -5,7 +5,7 @@ #endif #define CYGMEM_REGION_ram (0x81000000) -#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #ifndef __ASSEMBLER__ @@ -15,5 +15,5 @@ extern char CYG_LABEL_NAME (__heap1) []; #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_ram.ldi @@ -3,7 +3,7 @@ MEMORY { ram0 : ORIGIN = 0x40000000, LENGTH = 0x4000 - ram : ORIGIN = 0x81000000, LENGTH = 0x100000 + ram : ORIGIN = 0x81000000, LENGTH = CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE } SECTIONS
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.h @@ -8,7 +8,7 @@ #define CYGMEM_REGION_rom_SIZE (0x00040000) #define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) #define CYGMEM_REGION_ram (0x81000000) -#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #ifndef __ASSEMBLER__ @@ -18,5 +18,5 @@ extern char CYG_LABEL_NAME (__heap1) []; #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) -#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
--- a/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi +++ b/packages/hal/arm/lpc2xxx/olpcl2294/current/include/pkgconf/mlt_arm_lpc2xxx_olpcl2294_rom.ldi @@ -3,7 +3,7 @@ MEMORY { ram0 : ORIGIN = 0x40000000, LENGTH = 0x4000 - ram : ORIGIN = 0x81000000, LENGTH = 0x100000 + ram : ORIGIN = 0x81000000, LENGTH = CYGHWR_HAL_ARM_LPC2XXX_OLPCL2294_RAMSIZE rom : ORIGIN = 0x00000000, LENGTH = 0x40000 }