--- a/packages/hal/fr30/arch/current/ChangeLog
+++ b/packages/hal/fr30/arch/current/ChangeLog
@@ -1,3 +1,7 @@
+2008-09-19  Lars Poeschel  <larsi@wh2.tu-dresden.de>
+
+    * include/hal_cache.h: Basic cache support
+
 2008-07-01  Lars Poeschel  <larsi@wh2.tu-dresden.de>
 
     * src/vectors.S:

--- a/packages/hal/fr30/arch/current/include/hal_cache.h
+++ b/packages/hal/fr30/arch/current/include/hal_cache.h
@@ -46,81 +46,134 @@
 //
 // Author(s):   larsi
 // Contributors:
-// Date:        2007-07-09
+// Date:        2008-07-09
 // Purpose:     Cache control API
 // Description: The macros defined here provide the HAL APIs for handling
 //              cache control operations.
-// Usage:
-//              #include <cyg/hal/hal_cache.h>
-//              ...
+// Usage:       #include <cyg/hal/hal_cache.h>
 //
 //####DESCRIPTIONEND####
 //
 //=============================================================================
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
 
-#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/var_cache.h>
 
 //-----------------------------------------------------------------------------
 // Cache dimensions
 
-// Data cache
-#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
-#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
+// FR30 only has an instruction cache, so data cache macros are empty
+#ifndef HAL_DCACHE_SIZES_DEFINED
+#define HAL_DCACHE_SIZE                 0       // Size of cache in bytes
+#define HAL_DCACHE_LINE_SIZE            16      // Size of a cache line
 #define HAL_DCACHE_WAYS                 2       // Associativity of the cache
 
-// Instruction cache
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#endif
+
+#ifndef HAL_ICACHE_SIZES_DEFINED
 #define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
 #define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
 #define HAL_ICACHE_WAYS                 2       // Associativity of the cache
 
-#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-
+#endif
 //-----------------------------------------------------------------------------
-// Global control of data cache
+// Global control of the data cache
+// FR30 only has an instruction cache, so data cache macros are empty
 
-// Enable the data cache
+// Enable the cache
+#ifndef HAL_DCACHE_ENABLE_DEFINED
 #define HAL_DCACHE_ENABLE()
+#endif
 
-// Disable the data cache
+// Disable the cache
+#ifndef HAL_DCACHE_DISABLE_DEFINED
 #define HAL_DCACHE_DISABLE()
+#endif
 
-// Query the state of the data cache
+// Query the state of the cache
+#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
 #define HAL_DCACHE_IS_ENABLED(_state_) \
 CYG_MACRO_START                        \
 _state_ = 1;	                       \
 CYG_MACRO_END
+#endif
 
 // Invalidate the entire cache
+#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
 #define HAL_DCACHE_INVALIDATE_ALL()
+#endif
+
+// Synchronize the contents of the cache to the memory
+#ifndef HAL_DCACHE_SYNC_DEFINED
+#define HAL_DCACHE_SYNC()
+#endif
 
-// Synchronize the contents of the cache with memory.
-#define HAL_DCACHE_SYNC()
+// Locks entry in the cache
+#ifndef HAL_DCACHE_LOCK_DEFINED
+#define HAL_DCACHE_LOCK(_base_, _size_)
+#endif
+
+// Unlocks entry in the cache
+#ifndef HAL_DCACHE_UNLOCK_DEFINED
+#define HAL_DCACHE_UNLOCK(_base_, _size_)
+#endif
+
+// Unlocks the whole cache.
+#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
+#define HAL_DCACHE_UNLOCK_ALL()
+#endif
 
 //-----------------------------------------------------------------------------
-// Global control of Instruction cache
+// Global control of the instruction cache
 
-// Enable the instruction cache
+// Enable the cache
+#ifndef HAL_ICACHE_ENABLE_DEFINED
 #define HAL_ICACHE_ENABLE()
+#endif
 
-// Disable the instruction cache
+// Disable the cache
+#ifndef HAL_ICACHE_DISABLE_DEFINED
 #define HAL_ICACHE_DISABLE()
+#endif
 
-// Query the state of the instruction cache
+// Query the state of the cache
+#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
 #define HAL_ICACHE_IS_ENABLED(_state_) \
 CYG_MACRO_START                        \
 _state_ = 1;                           \
 CYG_MACRO_END
+#endif
 
 // Invalidate the entire cache
+#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
 #define HAL_ICACHE_INVALIDATE_ALL()
+#endif
 
-// Synchronize the contents of the cache with memory.
+// Synchronize the contents of the cache to the memory.
+#ifndef HAL_ICACHE_SYNC_DEFINED
 #define HAL_ICACHE_SYNC()
+#endif
 
-//-----------------------------------------------------------------------------
-// Instruction cache line control
+// Locks entry in the cache, fr30 architecture does not support locking specifc
+// regions, so _base_ and _size are ignored and the whole cache is locked.
+// During cache lock only valid entries are locked. Invalid entries are updated.
+#ifndef HAL_ICACHE_LOCK_DEFINED
+#define HAL_ICACHE_LOCK(_base_, _size_)
+#endif
 
+// Unlocks entry in the cache. fr30 architecture does not support locking specifc
+// regions, so _base_ and _size are ignored and the whole cache is unlocked.
+#ifndef HAL_ICACHE_UNLOCK_DEFINED
+#define HAL_ICACHE_UNLOCK(_base_, _size_)
+#endif
+
+// Unlocks the whole cache.
+#ifndef HAL_ICACHE_UNLOCK_ALL_DEFINED
+#define HAL_ICACHE_UNLOCK_ALL()
+#endif
 
 //-----------------------------------------------------------------------------
 #endif // ifndef CYGONCE_HAL_CACHE_H