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changeset 2160:34ebb920ba9b

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* hal_arm_at91sam7s.cdl: Change the PLL-defaults so that 96MHz is generated so that the USB does work. * cdl/hal_arm_at91sam7s.cdl: Set the debug UART as the default channel and fix some dodge spelling. * src/at91sam7s_misc.c (hal_plf_hardware_init): Enable the Debug UART pins for output and control by the device. * include/plf_io.h: Define USART2 to be the debug UART.
author asl
date Mon, 13 Mar 2006 07:48:20 +0000
parents 90fe3e2dc215
children afacaa648a92
files packages/hal/arm/at91/at91sam7s/current/ChangeLog packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl packages/hal/arm/at91/at91sam7s/current/include/plf_io.h packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c
diffstat 4 files changed, 46 insertions(+), 26 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/arm/at91/at91sam7s/current/ChangeLog
+++ b/packages/hal/arm/at91/at91sam7s/current/ChangeLog
@@ -1,3 +1,17 @@
+2006-03-10  Oliver Munz  <oli@snr.ch>
+
+	* hal_arm_at91sam7s.cdl: Change the PLL-defaults so that 96MHz is
+	generated so that the USB does work.
+	
+2006-03-10  Andrew Lunn  <andrew.lunn@ascom.ch>
+            Oliver Munz  <munz@speag.ch>
+	
+	* cdl/hal_arm_at91sam7s.cdl: Set the debug UART as the default
+	channel and fix some dodge spelling.
+	* src/at91sam7s_misc.c (hal_plf_hardware_init): Enable the Debug UART
+	pins for output and control by the device.
+	* include/plf_io.h: Define USART2 to be the debug UART.
+	
 2006-03-01  Andrew Lunn  <andrew.lunn@ascom.ch>
 
 	* cdl/hal_arm_at91sam7s.cdl: Change the crystal frequency.  The
--- a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
+++ b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
@@ -39,7 +39,7 @@
 ######DESCRIPTIONBEGIN####
 #
 # Author(s):      gthomas
-# Contributors:   gthomas, tkoeller, nickg, Oliver Munz
+# Contributors:   gthomas, tkoeller, nickg, Oliver Munz, asl
 # Date:           2005-06-20
 #
 #####DESCRIPTIONEND####
@@ -62,11 +62,11 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
     requires      { CYGHWR_HAL_ARM_AT91_FIQ     }
     requires      { CYGHWR_HAL_ARM_AT91SAM7S == "at91sam7s32" implies
                     CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 == 0 }
-    requires      { CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2 == 0 }
 
     implements    CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW
     implements    CYGINT_HAL_ARM_AT91_PIT_HW
     implements    CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+    implements    CYGINT_DEVS_USB_AT91_HAS_USB
 
     define_proc {
         puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
@@ -82,8 +82,8 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         display        "AT91SAM7S variant used"
         flavor         data
         default_value  {"at91sam7s256"}
-        legal_values   {"at91sam7s32" "at91sam7s64" "at91sam7s128" 
-                        "at91sam7s256"}
+        legal_values   {"at91sam7s32" "at91sam7s321" "at91sam7s64" 
+                        "at91sam7s128" "at91sam7s256"}
         description    "
            The AT91SAM7S microcontroller family has several variants,
            the main differences being the amount of on-chip SRAM,
@@ -124,9 +124,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         no_define
         define -file system.h CYG_HAL_STARTUP
         description   "
-            When targetting the AT91SAM7S eval board it is possible to build
+            When targeting the AT91SAM7S eval board it is possible to build
             the system for either RAM bootstrap or ROM bootstrap(s). Select
-            'ram' when building programs to load into RAM using onboard
+            'ram' when building programs to load into RAM using on board
             debug software such as Angel or eCos GDB stubs.  Select 'rom'
             when building a stand-alone application which will be put
             into ROM"
@@ -160,7 +160,7 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         display       "Divider for PLL clock"
         flavor        data
         legal_values  { 0 to 255 }
-        default_value 14
+        default_value 24
         description   "
             The X-tal clock is divided by this value when generating the
             PLL clock"
@@ -170,7 +170,7 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         display       "Multiplier for PLL clock"
         flavor        data
         legal_values  { 0 to 2047 }
-        default_value 145
+        default_value 125
         description   "
            The X-tal clock is multiplied by this value when generating
            the PLL clock."
@@ -181,20 +181,20 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         flavor        data
         default_value { 32768 }
         description   "
-            The slow clock is an LC oscilator which runs all the
+            The slow clock is an LC oscillator which runs all the
             time. The accuracy of this clock is not very high and 
-            is temperature dependant"
+            is temperature dependent."
     }
 
     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
         display       "Number of communication channels on the board"
         flavor        data
-        default_value 1
+        default_value 3
         description   "
-            The AT91SAM7S development boards have only one USART serial
-            port connector even though there are two real serial ports. 
-            Also don't confuse the debug port as a USART serial port. It
-            needs a different driver."
+            The AT91SAM7S development boards has two Serial port connectors.
+            these correspond to USART0 and the Debug Serial port. The chip
+            has a third serial port which does not have a 9pin D
+            connector, but is accessible via the patch panel pins."
     }
  
     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
@@ -202,9 +202,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
         flavor data
         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
-        default_value    0
+        default_value    2
         description      "
-            The AT91SAM7S has two USART serial ports. This option
+            The AT91SAM7S has three serial ports. This option
             chooses which port will be used to connect to a host
             running GDB."
      }
@@ -214,9 +214,9 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
          active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
          flavor data
          legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
-         default_value    0
+         default_value    2
          description      "
-            The AT91SAM7S board has two USART serial ports. This option
+            The AT91SAM7S board has three USART serial ports. This option
             chooses which port will be used for diagnostic output."
      }
      
@@ -242,10 +242,10 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7S {
         display       "Dynamic calculation of baud rate"
         default_value 0
         description   "
-             The AT91SAM7S has a flexiable clock generation mechanism 
+             The AT91SAM7S has a flexible clock generation mechanism 
              where the main clock used to drive peripherals can be
-             changed during runtime. Such changes affect the serial port
-             baud rate generaters. Enabling this option includes code 
+             changed during run time. Such changes affect the serial port
+             baud rate generators. Enabling this option includes code 
              which calculates the baud rate setting dynamically from the
              current clock settings. Without this option a static
              calculation is performed which assumes the clock frequency
--- a/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h
+++ b/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h
@@ -63,6 +63,12 @@
 #define AT91_USART0 0xFFFC0000
 #define AT91_USART1 0xFFFC4000
 
+// Define USART2 to be the debug UART. It is similar enough to a USART
+// that both the hal_diag and interrupt driven driver will work.
+// However trying to change parity, start/stop bits etc will not work.
+#define CYGNUM_HAL_INTERRUPT_USART2 CYGNUM_HAL_INTERRUPT_DBG 
+#define AT91_USART2 AT91_DBG 
+
 #ifndef __ASSEMBLER__
 #ifdef CYGBLD_HAL_ARM_AT91_BAUD_DYNAMIC
 extern cyg_uint32 hal_at91_us_baud(cyg_uint32 baud);
--- a/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c
+++ b/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c
@@ -94,11 +94,12 @@ void hal_plf_hardware_init (void)
 {
   /* Enable the Serial devices to driver the serial port pins */
   HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PDR, 
-                   AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0);
+                   AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 | AT91_PIO_PSR_DTXD);
 
   /* Set the serial port pins to PIOA */
   HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_ASR,
-                   AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0);
+                   AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 |
+                   AT91_PIO_PSR_DRXD | AT91_PIO_PSR_DTXD);
 
 #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
   /* Enable the Serial devices to driver the serial port pins */
@@ -120,8 +121,7 @@ void hal_plf_hardware_init (void)
   /* Enable peripheral clocks for USART 0 and 1 if they are to be used */
   HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, 
                    AT91_PMC_PCER_US0 |
-                   AT91_PMC_PCER_US1 |
-                   CYGNUM_HAL_INTERRUPT_SYS);
+                   AT91_PMC_PCER_US1);
 #endif
 
 #ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC