--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog
+++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -1,3 +1,18 @@
+2012-01-05  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/kinetis_irq_scheme.cdl
+    Centralized IRQ priority scheme.
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* cdl/kinetis_flexbus.cdl
+	* include/var_io_devs.h:
+	* include/var_io.h:
+	* src/kinetis_clocking.c:
+	* src/kinetis_misc.c:
+	Add I/O defs for eDMA, DSPI. Add flexbus control.
+	CYG_HAL_STARTUP parenthed bt CYG_HAL_STARTUP_ENV.
+	Early clock start [Bugzilla 1001450]
+
 2011-11-15  Tomas Frydrych <tomas@sleepfive.com>
 
 	* include/var_io_gpio.h:

--- a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
@@ -153,7 +153,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
     cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
         display       "Clock interrupt ISR priority"
         flavor        data
-        default_value 0xE0
+        calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
         description   "Set clock ISR priority. Default setting is lowest priority."
     }
 
@@ -183,38 +183,40 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
         }
     }
 
-    cdl_component CYG_HAL_STARTUP {
-        display       "Startup type"
+    cdl_option CYG_HAL_STARTUP_VAR {
+        display       "By variant"
         flavor        data
-        calculated  {
-            (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
-            CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR
-        }
-        no_define
-        define -file system.h CYG_HAL_STARTUP
+        parent CYG_HAL_STARTUP_ENV
+        default_value {
+            (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
+            "ByPlatform" : "ROM" }
+        legal_values  { "ROM" "SRAM" }
+        active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
         description   "
+        'ROM' startup builds a stand-alone application which will
+        be placed into flash. SRAM startup builds application
+        intended for loading in on-chip SRAM by means of JTAG/SWD.
+        Note: Variant Startup Type can be overriden/overloaded by
+        Platform Startup Type."
+    }
+
+        cdl_component CYG_HAL_STARTUP {
+            display       "Startup type calculator"
+            flavor        data
+            parent CYG_HAL_STARTUP_ENV
+            calculated  {
+                (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
+                CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR
+            }
+            no_define
+            define -file system.h CYG_HAL_STARTUP
+            description "
             Startup type defines what type of application shall be built.
             Startup type  can be defined by variant (CYG_HAL_STARTUP_VAR)
             or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
             is defined and not equal to 'ByVariant' then it shall
             override CYG_HAL_STARTUP_VAR."
-
-        cdl_option CYG_HAL_STARTUP_VAR {
-            display       "By variant"
-            flavor        data
-            default_value {
-                (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
-                "ByPlatform" : "ROM" }
-            legal_values  { "ROM" "SRAM" }
-            active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
-            description   "
-                'ROM' startup builds a stand-alone application which will
-                be placed into flash. SRAM startup builds application
-                intended for loading in on-chip SRAM by means of JTAG/SWD.
-                Note: Variant Startup Type can be overriden/overloaded by
-                Platform Startup Type."
         }
-    }
 
     cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF {
         display "FlexNVM configuration"
@@ -314,6 +316,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
         display "Memory layout"
         flavor data
         no_define
+        parent CYG_HAL_STARTUP_ENV
         calculated {
             (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
             (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_"
@@ -505,13 +508,13 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
                         display "Port size (encoded)"
                         flavor data
                         calculated ( \
-                            CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
-                            CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
-                            CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+                                    CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
+                                    CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
+                                    CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+                    }
                     }
                 }
             }
-        }
 
         cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF {
         display "Flash configuration field"
@@ -593,6 +596,25 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
         }
     }
 
+    cdl_interface CYGINT_HAL_DMA {
+        display "Platform uses DMA"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DMA and if DMA is
+            used on target hardware"
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display "Variant IRQ priority defaults"
+        no_define
+        flavor none
+        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by Kinetis variant"
+        script kinetis_irq_scheme.cdl
+    }
+
     cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS {
         display "Build options"
         flavor  none

new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
@@ -0,0 +1,84 @@
+##==========================================================================
+##
+##      kinetis_flexbus.cdl
+##
+##      Cortex-M Freescale Kinetis FlexBus
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+#        cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+#        display       "FlexBus"
+
+for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } {
+    
+    cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display     "Platform uses Chip select [set ::chipsel]"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides chip select [set ::chipsel], and if
+            that chip select is used on target hardware."
+    }
+    
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display       "Chip select [set ::chipsel]"
+        flavor        bool
+        active_if     CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        description   "
+            This option includes initialization data for
+            chip select [set ::chipsel]."
+        
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS {
+            display "Port size (encoded)"
+            flavor data
+            calculated ( \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+        }
+    }
+}
+
+
+# EOF kinetis_flexbus.cdl

new file mode 100644
--- /dev/null
+++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
@@ -0,0 +1,183 @@
+##==========================================================================
+##
+##      kinetis_irq_scheme.cdl
+##
+##      Cortex-M Freescale Kinetis IRQ configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+#        display "Variant IRQ priority defaults"
+#        no_define
+#        flavor none
+#        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+#        description "
+#            Interrupt priorities defined by Kinetis variant"
+
+        cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP {
+            display       "Clock IRQ priority"
+            flavor        data
+            no_define
+            default_value 0xE0
+            description   "Set clock ISR priority. Default setting is lowest priority."
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP {
+            display "Ethernet IRQ priority"
+            flavor data
+            no_define
+            active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+            default_value 0xE0
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART {
+            display "UART IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP {
+                display "UART0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP {
+                display "UART1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP {
+                display "UART2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP {
+                display "UART3 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART3
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP {
+                display "UART4 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART4
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP {
+                display "UART5 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART5
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_DSPI {
+            display "DSPI IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI_SP {
+                display "DSPI bus 0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI_SP {
+                display "DSPI bus 1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI_SP {
+                display "DSPI bus 2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+        }
+#    }
+
+
+# EOF kinetis_irq_scheme.cdl

--- a/packages/hal/cortexm/kinetis/var/current/include/var_io.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h
@@ -1028,6 +1028,11 @@ typedef volatile struct cyghwr_hal_kinet
 #ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
 # include <cyg/hal/var_io_flexbus.h>
 #endif
+//----------------------------------------------------------------------------
+// DMA
+//#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DMA
+//# include <cyg/hal/var_io_dma.h>
+//#endif
 
 //---------------------------------------------------------------------------
 // GPIO
@@ -1041,6 +1046,11 @@ typedef volatile struct cyghwr_hal_kinet
 
 // End Peripherals
 
+// Some miscelaneous function prototypes
+// Clock related functions are in kinetis_clocking.c
+__externC void hal_start_clocks(void);
+__externC void hal_update_clock_var(void);
+
 //-----------------------------------------------------------------------------
 // end of var_io.h
 

--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
+++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
@@ -55,6 +55,22 @@
 //=============================================================================
 // DEVS:
 // Following macros may be, and usually are borrwed by some device drivers.
+
+
+//=============================================================================
+// Peripheral clock
+
+//
+//===========================================================================
+
+
+//=============================================================================
+// DEVS:
+// Following macros may be, and usually are borrwed by some device drivers.
+
+// Peripheral clock [Hz];
+__externC cyg_uint32 hal_get_peripheral_clock(void);
+
 //-----------------------------------------------------------------------------
 // Freescale UART
 // Borrow some HAL resources to Freescale UART driver
@@ -126,6 +142,7 @@
 # define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \
         hal_set_pin_function(__pin)
 
+
 // Set baud rate
 __externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
 
@@ -143,6 +160,144 @@
 
 #endif
 
+//----------------------------------------------------------------------------
+// DSPI
+// Lend some HAL dependent macros to DSPI device driver
+
+// DSPI - Peripheral instance base addresses
+#define CYGADDR_IO_SPI_FREESCALE_DSPI0_P ((cyghwr_devs_freescale_dspi_t*)0x4002C000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI1_P ((cyghwr_devs_freescale_dspi_t*)0x4002D000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI2_P ((cyghwr_devs_freescale_dspi_t*)0x400AC000)
+
+#define CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK hal_get_peripheral_clock();
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+#endif
+
+#ifndef KINETIS_PIN_SPI0_OUT_OPT
+#define KINETIS_PIN_SPI0_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_CS_OPT
+#define KINETIS_PIN_SPI0_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_IN_OPT
+#define KINETIS_PIN_SPI0_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+#ifndef KINETIS_PIN_SPI1_OUT_OPT
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_CS_OPT
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_IN_OPT
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_OUT_OPT
+#define KINETIS_PIN_SPI2_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_CS_OPT
+#define KINETIS_PIN_SPI2_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_IN_OPT
+#define KINETIS_PIN_SPI2_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+// DMA MUX ------------------------------------------------------------------
+// DMAMUX DMA request sources
+#define FREESCALE_DMAMUX_SRC_KINETIS_DISABLE      0
+#define FREESCALE_DMAMUX_SRC_KINETIS_RESERVE      1
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0R       2
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0T       3
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1R       4
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1T       5
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2R       6
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2T       7
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3R       8
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3T       9
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4R      10
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4T      11
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5R      12
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5T      13
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2S0R       14
+#define FREESCALE_DMAMUX_SRC_KINETIS_I3S0T       15
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0R       16
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0T       17
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1R       18
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1T       19
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2R       20
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2T       21
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C0        22
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1        23
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C0      24
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C1      25
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C2      26
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C3      27
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C4      28
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C5      29
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C6      30
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C7      31
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C0      32
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C1      33
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C0      34
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C1      35
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T0      36
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T1      37
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T2      38
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T3      39
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC0        40
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC1        41
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP0        42
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP1        43
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP2        44
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC0        45
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC1        46
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMT         47
+#define FREESCALE_DMAMUX_SRC_KINETIS_PDB         48
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTA       49
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTB       50
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTC       51
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTD       52
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTE       53
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX0     54
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX1     55
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX2     56
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX3     57
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX4     58
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX5     59
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX6     60
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX7     61
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX8     62
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX9     63
+
+#define FREESCALE_DMAMUX_SRC_SPI0_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI0R
+#define FREESCALE_DMAMUX_SRC_SPI0_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI0T
+#define FREESCALE_DMAMUX_SRC_SPI1_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI1R
+#define FREESCALE_DMAMUX_SRC_SPI1_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI1T
+#define FREESCALE_DMAMUX_SRC_SPI2_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI2R
+#define FREESCALE_DMAMUX_SRC_SPI2_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI2T
+
+//----------------------------------------------------------------------------
+// eDMA
+// Lend some eDMA macros to device driver that use DMA
+
+// Base address
+#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P
+
 //-----------------------------------------------------------------------------
 // end of var_io_devs.h
 #endif // CYGONCE_HAL_VAR_IO_DEVS_H

--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
@@ -104,10 +104,6 @@ hal_start_clocks( void )
     // Main clock - MCG
     hal_start_main_clock();
 #endif
-    hal_kinetis_sysclk=hal_get_cpu_clock();
-    hal_kinetis_busclk=hal_kinetis_sysclk /
-          CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS;
-    hal_cortexm_systick_clock=hal_kinetis_sysclk;
     // Trace clock
 #ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE
     sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
@@ -335,5 +331,20 @@ hal_freescale_uart_setbaud(cyg_uint32 ua
     }
 }
 
+
+void hal_update_clock_var(void)
+{
+    hal_kinetis_sysclk=hal_get_cpu_clock();
+    hal_kinetis_busclk=hal_kinetis_sysclk /
+          CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS;
+    hal_cortexm_systick_clock=hal_kinetis_sysclk;
+}
+
+
+cyg_uint32 hal_get_peripheral_clock(void)
+{
+    return hal_kinetis_busclk;
+}
+
 //==========================================================================
 // EOF kinetis_clocking.c

--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
+++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
@@ -66,10 +66,7 @@
 #include <cyg/hal/hal_intr.h>           // HAL header
 #include <cyg/hal/hal_if.h>             // HAL header
 
-
-
-// Clock related functions are in kinetis_clocking.c
-void hal_start_clocks( void );
+void sst25xx_freescale_dspi_reg(void);
 
 #ifdef CYG_HAL_STARTUP_ROM
 
@@ -103,16 +100,14 @@ hal_kinetis_flash_conf_p( void )
 
 //=== KINETIS FLASH security configuration END. ============================
 
-
+//volatile cyg_uint32 *poin;
 //==========================================================================
 // Setup variant specific hardware
 //=========================================================================
 
-
 void hal_variant_init( void )
 {
-    hal_start_clocks();
-
+    hal_update_clock_var();
 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
     hal_if_init();
 #endif