Mercurial > nand-ecoscentric
changeset 3137:50f5e8953371
* New package -- Freescale UART driver.
* New package -- Freescale UART header.
line wrap: on
line diff
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/ChangeLog @@ -0,0 +1,33 @@ +2011-03-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_freescale_uart.cdl: + * src/ser_freescale_uart.c: + * include/ser_freescale_uart_chan.inl: + * include/ser_freescale_uart_tty_add.inl: + * include/ser_freescale_uart_termiostty_add.inl: + + New package -- Freescale UART driver. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/cdl/ser_freescale_uart.cdl @@ -0,0 +1,269 @@ +# ==================================================================== +# +# ser_freescale_uart.cdl +# +# eCos serial Freescale UART configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Kocho <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2011-02-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART { + display "Freescale UART device driver" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_IO_SERIAL_FREESCALE_UART_HDR + requires CYGPKG_ERROR + + include_dir cyg/io + + description " + This option enables the serial device drivers for the + Freescale UART, an on-chip serial controller found on some + freescale microcontrollers such as Kinetis, etc." + + compile -library=libextras.a ser_freescale_uart.c + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_freescale_uart.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } + + # Support up to 6 on-chip UART modules. The number may vary between + # processor variants so it is easy to update this here + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { + + cdl_interface CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] { + display "Platform provides UART [set ::channel]" + flavor bool + description " + This interface will be implemented if the specific + controller being used has on-chip UART [set ::channel], and if + that UART is accessible on the target hardware." + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART[set ::channel] { + display "Freescale UART port [set ::channel] driver" + flavor bool + active_if CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] + default_value CYGINT_IO_SERIAL_FREESCALE_UART[set ::channel] + implements CYGINT_IO_SERIAL_TTY_TTY[set ::channel] + description " + This option includes the serial device driver for Freescale + UART port [set ::channel]." + + cdl_option CYGDAT_IO_SERIAL_FREESCALE_UART[set ::channel]_NAME { + display "Device name for Freescale UART port [set ::channel]" + flavor data + default_value [ format {"\"/dev/ser%d\""} $::channel ] + description " + This option specifies the device name for + Freescale UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BAUD { + display "Baud rate for the Freescale UART port [set ::channel] driver" + flavor data + legal_values { 300 600 1200 2400 4800 9600 14400 19200 38400 + 57600 115200 230400 } + default_value 38400 + description " + This option specifies the default baud rate for the + UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_BUFSIZE { + display "Buffer size for the Freescale UART port [set ::channel] driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for Freescale UART port [set ::channel]." + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART[set ::channel]_INT_PRIORITY { + display "Freescale UART port [set ::channel] interrupt priority" + flavor data + default_value 0x80 + description " + This option selects the interupt priority for the + UART [set ::channel] interrupts." + } + } + } + + cdl_component CYGDAT_IO_SERIAL_TTY_ADD_INL { + display "Freescale TTY devices beyond #3" + parent CYGPKG_IO_SERIAL + active_if CYGPKG_IO_SERIAL_TTY + flavor data + calculated { "<cyg/io/ser_freescale_uart_tty_add.inl>" } + + + cdl_component CYGPKG_IO_SERIAL_TTY_TTY4 { + display "TTY mode channel #4" + flavor bool + parent CYGPKG_IO_SERIAL_TTY + active_if CYGPKG_IO_SERIAL_TTY + default_value 0 + description " + This option causes '/dev/tty4', which is provided by Freescale + UART, to be included in the standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TTY_TTY4_DEV { + display "TTY mode channel #4 device" + flavor data + default_value { "\"/dev/ser4\"" } + description " + This option selects the physical device to use for + '/dev/tty4'." + } + } + + cdl_component CYGPKG_IO_SERIAL_TTY_TTY5 { + display "TTY mode channel #5" + flavor bool + parent CYGPKG_IO_SERIAL_TTY + active_if CYGPKG_IO_SERIAL_TTY + default_value 0 + description " + This option causes '/dev/tty5', which is provided by Freescale + UART, to be included in the standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TTY_TTY5_DEV { + display "TTY mode channel #5 device" + flavor data + default_value { "\"/dev/ser5\"" } + description " + This option selects the physical device to use for + '/dev/tty5'." + } + } + } + + cdl_component CYGDAT_IO_SERIAL_TERMIOS_ADD_INL { + display "Freescale TERMIOS devices beyond #3" + parent CYGPKG_IO_SERIAL + active_if CYGPKG_IO_SERIAL_TERMIOS + flavor data + calculated { "<cyg/io/ser_freescale_uart_termiostty_add.inl>" } + + cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4 { + display "Termios TTY channel #4" + flavor bool + default_value 0 + implements CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY + parent CYGPKG_IO_SERIAL_TERMIOS + active_if CYGPKG_IO_SERIAL_TERMIOS + description " + This option causes '/dev/termios4' to be included in the + standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV { + display "Termios TTY channel #4 device" + flavor data + default_value {"\"/dev/ser4\""} + description " + This option selects the physical device to use for + '/dev/termios4'." + } + } + + cdl_component CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5 { + display "Termios TTY channel #5" + flavor bool + default_value 0 + implements CYGINT_IO_SERIAL_TERMIOS_TERMIOS_TTY + parent CYGPKG_IO_SERIAL_TERMIOS + active_if CYGPKG_IO_SERIAL_TERMIOS + description " + This option causes '/dev/termios5' to be included in the + standard drivers." + + cdl_option CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV { + display "Termios TTY channel #5 device" + flavor data + default_value {"\"/dev/ser5\""} + description " + This option selects the physical device to use for + '/dev/termios5'." + } + } + } + + cdl_component CYGPKG_IO_SERIAL_FREESCALE_UART_OPTIONS { + display "Serial device driver build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_IO_SERIAL_FREESCALE_UART_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building these serial device drivers. These flags are + removed from the set of global flags if present." + } + } +} + +# EOF ser_freescale_uart.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_chan.inl @@ -0,0 +1,372 @@ +//========================================================================== +// +// ser_freescale_uart.inl +// +// Freescale UART Serial channel definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-10 +// Purpose: Freescale UART Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART0 +static const uart_pins_t uart0_pins = { + rx : CYGHWR_IO_FREESCALE_UART0_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART0_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART0_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART0_PIN_CTS +}; +static uart_serial_info uart_serial_info0 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY, + pins_p : &uart0_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE]; +static unsigned char + uart_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS( + uart_serial_channel0, + uart_serial_funs, + uart_serial_info0, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf0[0], + sizeof(uart_serial_out_buf0), + &uart_serial_in_buf0[0], + sizeof(uart_serial_in_buf0)); +#else +static +SERIAL_CHANNEL(uart_serial_channel0, + uart_serial_funs, + uart_serial_info0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io0, + CYGDAT_IO_SERIAL_FREESCALE_UART0_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel0); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART0 + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART1 +static const uart_pins_t uart1_pins = { + rx : CYGHWR_IO_FREESCALE_UART1_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART1_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART1_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART1_PIN_CTS +}; +static uart_serial_info uart_serial_info1 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY, + pins_p : &uart1_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE]; +static unsigned char + uart_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel1, + uart_serial_funs, + uart_serial_info1, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf1[0], + sizeof(uart_serial_out_buf1), + &uart_serial_in_buf1[0], + sizeof(uart_serial_in_buf1)); +#else +static +SERIAL_CHANNEL(uart_serial_channel1, + uart_serial_funs, + uart_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io1, + CYGDAT_IO_SERIAL_FREESCALE_UART1_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel1); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART1 + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART2 +static const uart_pins_t uart2_pins = { + rx : CYGHWR_IO_FREESCALE_UART2_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART2_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART2_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART2_PIN_CTS +}; +static uart_serial_info uart_serial_info2 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY, + pins_p : &uart2_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE]; +static unsigned char + uart_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel2, + uart_serial_funs, + uart_serial_info2, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf2[0], + sizeof(uart_serial_out_buf2), + &uart_serial_in_buf2[0], + sizeof(uart_serial_in_buf2)); +#else +static +SERIAL_CHANNEL(uart_serial_channel2, + uart_serial_funs, + uart_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io2, + CYGDAT_IO_SERIAL_FREESCALE_UART2_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel2); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART2 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART3 +static const uart_pins_t uart3_pins = { + rx : CYGHWR_IO_FREESCALE_UART3_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART3_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART3_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART3_PIN_CTS +}; +static uart_serial_info uart_serial_info3 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY, + pins_p : &uart3_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE]; +static unsigned char + uart_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel3, + uart_serial_funs, + uart_serial_info3, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf3[0], + sizeof(uart_serial_out_buf3), + &uart_serial_in_buf3[0], + sizeof(uart_serial_in_buf3)); +#else +static +SERIAL_CHANNEL(uart_serial_channel3, + uart_serial_funs, + uart_serial_info3, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io3, + CYGDAT_IO_SERIAL_FREESCALE_UART3_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel3); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART3 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART4 +static const uart_pins_t uart4_pins = { + rx : CYGHWR_IO_FREESCALE_UART4_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART4_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART4_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART4_PIN_CTS +}; +static uart_serial_info uart_serial_info4 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY, + pins_p : &uart4_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE]; +static unsigned char + uart_serial_in_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel4, + uart_serial_funs, + uart_serial_info4, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf4[0], + sizeof(uart_serial_out_buf4), + &uart_serial_in_buf4[0], + sizeof(uart_serial_in_buf4)); +#else +static +SERIAL_CHANNEL(uart_serial_channel4, + uart_serial_funs, + uart_serial_info4, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io4, + CYGDAT_IO_SERIAL_FREESCALE_UART4_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel4); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART4 + + +#if defined CYGPKG_IO_SERIAL_FREESCALE_UART5 +static const uart_pins_t uart5_pins = { + rx : CYGHWR_IO_FREESCALE_UART5_PIN_RX, + tx : CYGHWR_IO_FREESCALE_UART5_PIN_TX, + rts : CYGHWR_IO_FREESCALE_UART5_PIN_RTS, + cts : CYGHWR_IO_FREESCALE_UART5_PIN_CTS +}; +static uart_serial_info uart_serial_info5 = { + uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, + interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR, + interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY, + pins_p : &uart5_pins +}; +#if CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE > 0 +static unsigned char + uart_serial_out_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE]; +static unsigned char + uart_serial_in_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE]; + +static +SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel5, + uart_serial_funs, + uart_serial_info5, + CYG_SERIAL_BAUD_RATE( + CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &uart_serial_out_buf5[0], + sizeof(uart_serial_out_buf5), + &uart_serial_in_buf5[0], + sizeof(uart_serial_in_buf5)); +#else +static +SERIAL_CHANNEL(uart_serial_channel5, + uart_serial_funs, + uart_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT); +#endif +DEVTAB_ENTRY(uart_serial_io5, + CYGDAT_IO_SERIAL_FREESCALE_UART5_NAME, + 0, // does not depend on a lower level device driver + &cyg_io_serial_devio, + uart_serial_init, + uart_serial_lookup, + &uart_serial_channel5); +#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART5
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_termiostty_add.inl @@ -0,0 +1,79 @@ +#ifndef CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL +#define CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL +//============================================================================= +// +// ser_freescale_uart_termiostty_add.inl +// +// Termios definitions beyond #3. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-03-28 +// Purpose: Termios definitions beyond #3. +// Description: +// Usage: This file is included by pkgconf/io/serial.h +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS4 +static struct termios_private_info termios_private_info4; +DEVTAB_ENTRY(termios_io4, + "/dev/termios4", + CYGDAT_IO_SERIAL_TERMIOS_TERMIOS4_DEV, + &termios_devio, + termios_init, + termios_lookup, + &termios_private_info4); +#endif + +#ifdef CYGPKG_IO_SERIAL_TERMIOS_TERMIOS5 +static struct termios_private_info termios_private_info5; +DEVTAB_ENTRY(termios_io5, + "/dev/termios5", + CYGDAT_IO_SERIAL_TERMIOS_TERMIOS5_DEV, + &termios_devio, + termios_init, + termios_lookup, + &termios_private_info5); +#endif +//----------------------------------------------------------------------------- +// end of ser_freescale_uart_termiostty_add.inl +#endif // CYGONCE_SER_FREESCALE_UART_TERMIOS_ADD_INL
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/include/ser_freescale_uart_tty_add.inl @@ -0,0 +1,79 @@ +#ifndef CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL +#define CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL +//============================================================================= +// +// ser_freescale_uart_tty_add.inl +// +// TTY definitions beyond #3. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-03-28 +// Purpose: TTY definitions beyond 3. +// Description: +// Usage: This file is included by pkgconf/io/serial.h +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +#ifdef CYGPKG_IO_SERIAL_TTY_TTY4 +static struct tty_private_info tty_private_info4; +DEVTAB_ENTRY(tty_io4, + "/dev/tty4", + CYGDAT_IO_SERIAL_TTY_TTY4_DEV, + &tty_devio, + tty_init, + tty_lookup, // Execute this when device is being looked up + &tty_private_info4); +#endif + +#ifdef CYGPKG_IO_SERIAL_TTY_TTY5 +static struct tty_private_info tty_private_info5; +DEVTAB_ENTRY(tty_io5, + "/dev/tty5", + CYGDAT_IO_SERIAL_TTY_TTY5_DEV, + &tty_devio, + tty_init, + tty_lookup, // Execute this when device is being looked up + &tty_private_info5); +#endif +//----------------------------------------------------------------------------- +// end of ser_freescale_uart_tty_add.inl +#endif // CYGONCE_SER_FREESCALE_UART_TTY_ADD_INL
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/drv/current/src/ser_freescale_uart.c @@ -0,0 +1,394 @@ +//========================================================================== +// +// ser_freescale_uart.c +// +// Freescale UART Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-10 +// Purpose: Freescale UART Serial I/O module (interrupt driven version) +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> + +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arbiter.h> +#include <cyg/hal/hal_io.h> +#include <cyg/io/devtab.h> +#include <cyg/infra/diag.h> +#include <cyg/io/serial.h> +#include <cyg/io/ser_freescale_uart.h> + +// Only build this driver for if Freescale UART is needed. +#ifdef CYGPKG_IO_SERIAL_FREESCALE_UART + +typedef struct uart_pins_s { + cyg_uint32 rx; + cyg_uint32 tx; + cyg_uint32 rts; + cyg_uint32 cts; +} uart_pins_t; + + +typedef struct uart_serial_info { + CYG_ADDRWORD uart_base; // Base address of the uart port + CYG_WORD interrupt_num; // NVIC interrupt vector + cyg_priority_t interrupt_priority; // NVIC interupt priority + const uart_pins_t *pins_p; + cyg_bool tx_active; + cyg_interrupt interrupt_obj; // Interrupt object + cyg_handle_t interrupt_handle; // Interrupt handle +} uart_serial_info; + +static bool uart_serial_init(struct cyg_devtab_entry * tab); +static bool uart_serial_putc(serial_channel * chan, unsigned char c); +static Cyg_ErrNo uart_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, + const char * name); +static unsigned char uart_serial_getc(serial_channel *chan); +static Cyg_ErrNo uart_serial_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void uart_serial_start_xmit(serial_channel *chan); +static void uart_serial_stop_xmit(serial_channel *chan); + +// Interrupt servers +static cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, + cyg_addrword_t data); + +static SERIAL_FUNS(uart_serial_funs, + uart_serial_putc, + uart_serial_getc, + uart_serial_set_config, + uart_serial_start_xmit, + uart_serial_stop_xmit); + +// Available baud rates +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 230400, // 230400 +}; + +#include <cyg/io/ser_freescale_uart_chan.inl> + +//---------------------------------------------------------------------------- +// Internal function to actually configure the hardware to desired +// baud rate, etc. +//---------------------------------------------------------------------------- +static bool +uart_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config, + bool init) +{ + cyg_uint32 regval; + uart_serial_info * uart_chan = (uart_serial_info *)(chan->dev_priv); + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 baud_rate = select_baud[new_config->baud]; + + if(!baud_rate) return false; // Invalid baud rate selected + + // Configure PORT pins + CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->rx); + CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->tx); + + CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_base, baud_rate); + + if(new_config->word_length != 8) + return false; + + switch(new_config->parity) { + case CYGNUM_SERIAL_PARITY_NONE: + regval = 0; + break; + case CYGNUM_SERIAL_PARITY_EVEN: + regval = CYGHWR_DEV_FREESCALE_UART_C1_PE; + break; + case CYGNUM_SERIAL_PARITY_ODD: + regval = CYGHWR_DEV_FREESCALE_UART_C1_PE | + CYGHWR_DEV_FREESCALE_UART_C1_PT; + break; + default: return false; + } + + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C1, regval); + + if(init) { // Enable the receiver interrupt + regval = CYGHWR_DEV_FREESCALE_UART_C2_RIE; + } else { // Restore the old interrupt state + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval); + } + + // Enable the device + regval |= CYGHWR_DEV_FREESCALE_UART_C2_TE | + CYGHWR_DEV_FREESCALE_UART_C2_RE; + + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval); + + uart_chan->tx_active = false; + + if(new_config != &chan->config) + chan->config = *new_config; + + return true; +} + +//-------------------------------------------------------------- +// Function to initialize the device. Called at bootstrap time. +//-------------------------------------------------------------- +static bool +uart_serial_init(struct cyg_devtab_entry * tab) +{ + serial_channel * chan = (serial_channel *)tab->priv; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + if(chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(uart_chan->interrupt_num, + uart_chan->interrupt_priority, + // Data item passed to interrupt handler + (cyg_addrword_t)chan, + uart_serial_ISR, + uart_serial_DSR, + &uart_chan->interrupt_handle, + &uart_chan->interrupt_obj); + + cyg_drv_interrupt_attach(uart_chan->interrupt_handle); + cyg_drv_interrupt_unmask(uart_chan->interrupt_num); + } + return uart_serial_config_port(chan, &chan->config, true); +} + +//---------------------------------------------------------------------- +// This routine is called when the device is "looked" up (i.e. attached) +//---------------------------------------------------------------------- +static Cyg_ErrNo +uart_serial_lookup(struct cyg_devtab_entry ** tab, + struct cyg_devtab_entry * sub_tab, const char * name) +{ + serial_channel * chan = (serial_channel *)(*tab)->priv; + // Really only required for interrupt driven devices + (chan->callbacks->serial_init)(chan); + + return ENOERR; +} + +//----------------------------------------------------------------- +// Send a character to Tx +//----------------------------------------------------------------- +static bool +uart_serial_putc(serial_channel * chan, unsigned char ch_out) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_sr; + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE) { + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_out); + return true; + } else { + return false; + } +} + + +//--------------------------------------------------------------------- +// Fetch a character Rx (for polled operation only) +//--------------------------------------------------------------------- +static unsigned char +uart_serial_getc(serial_channel * chan) +{ + cyg_uint8 ch_in; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + + cyg_uint32 uart_sr; + + do { + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + } while(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_RDRF); + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + + return ch_in; +} + + +//--------------------------------------------------- +// Set up the device characteristics; baud rate, etc. +//--------------------------------------------------- +static bool +uart_serial_set_config(serial_channel * chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 * len) +{ + switch(key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: { + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + if(*len < sizeof(cyg_serial_info_t)) { + return -EINVAL; + } + *len = sizeof(cyg_serial_info_t); + if(true != uart_serial_config_port(chan, config, false)) + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return ENOERR; +} + +//------------------------------------- +// Enable the transmitter on the device +//------------------------------------- +static void uart_serial_start_xmit(serial_channel * chan) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_cr12; + + if(!uart_chan->tx_active) { + uart_chan->tx_active = true; + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + uart_cr12 |= CYGHWR_DEV_FREESCALE_UART_C2_TIE; + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + } +} + +//-------------------------------------- +// Disable the transmitter on the device +//-------------------------------------- +static void uart_serial_stop_xmit(serial_channel * chan) +{ + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + cyg_addrword_t uart_base = uart_chan->uart_base; + cyg_uint32 uart_cr12; + + if(uart_chan->tx_active) { + uart_chan->tx_active = false; + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + uart_cr12 &= ~CYGHWR_DEV_FREESCALE_UART_C2_TIE; + HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12); + } +} + +//----------------------------------------- +// The low level interrupt handler +//----------------------------------------- +static +cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + + cyg_drv_interrupt_mask(uart_chan->interrupt_num); + cyg_drv_interrupt_acknowledge(uart_chan->interrupt_num); + + return CYG_ISR_CALL_DSR; // cause the DSR to run +} + + +//------------------------------------------ +// The high level interrupt handler +//------------------------------------------ + +#define CYGHWR_DEV_FREESCALE_UART_S1_ERRORS \ + (CYGHWR_DEV_FREESCALE_UART_S1_OR | \ + CYGHWR_DEV_FREESCALE_UART_S1_NF | \ + CYGHWR_DEV_FREESCALE_UART_S1_FE | \ + CYGHWR_DEV_FREESCALE_UART_S1_PF) + +static void +uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel * chan = (serial_channel *)data; + uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv; + cyg_addrword_t uart_base = uart_chan->uart_base; + volatile cyg_uint32 uart_sr; + cyg_uint8 uart_dr; + + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr); + if(uart_sr & (CYGHWR_DEV_FREESCALE_UART_S1_RDRF | + CYGHWR_DEV_FREESCALE_UART_S1_ERRORS)) { + // Receiver full or errors + HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, uart_dr); + if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_ERRORS) { + // Check for receive error + } else { // No errors, get the character + (chan->callbacks->rcv_char)(chan, (cyg_uint8)uart_dr); + } + } + + if(uart_chan->tx_active && (uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)){ + //Transmitter empty + (chan->callbacks->xmt_char)(chan); + } + + cyg_drv_interrupt_unmask(uart_chan->interrupt_num); +} + +#endif // CYGPKG_IO_SERIAL_FREESCALE_UART +// EOF ser_freescale_uart.c
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/hdr/current/ChangeLog @@ -0,0 +1,29 @@ +2011-03-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/ser_freescale_uart_hdr.cdl: + * include/ser_freescale_uart.h: + New package -- Freescale UART header. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/hdr/current/cdl/ser_freescale_uart_hdr.cdl @@ -0,0 +1,68 @@ +# ==================================================================== +# +# ser_freescale_uart_h.cdl +# +# eCos serial Freescale UART configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Ilija Kocho <ilijak@siva.com.mk> +# Original data: +# Contributors: +# Date: 2011-02-05 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_FREESCALE_UART_HDR { + display "Freescale UART header" + + include_dir cyg/io + description " + This pacckage provides header file with definitions and macros for + Freescale UART. Same header is used by Freescale UART serial driver + as well as by HAL. Freescale UART is on-chip serial controller found + on some Freescale micro-controllers such as Kinetis familly, etc." + + define_proc { + puts $::cdl_system_header "/***** serial driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HDR_HEADER <pkgconf/io_serial_freescale_uart_hdr.h>" + puts $::cdl_system_header "/***** serial driver proc output end *****/" + } +} + +# EOF ser_freescale_uart_h.cdl
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/freescale/uart/hdr/current/include/ser_freescale_uart.h @@ -0,0 +1,143 @@ +#ifndef CYGONCE_DEVS_SERIAL_FREESCALE_UART_H +#define CYGONCE_DEVS_SERIAL_FREESCALE_UART_H +//========================================================================== +// +// ser_freescale_uart.h +// +// Freescale UART I/O definitions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Contributors: +// Date: 2011-02-05 +// Purpose: Freescale UART I/O definitions. +// Description: +// +// +//####DESCRIPTIONEND#### +//========================================================================== + +enum { + CYGHWR_DEV_FREESCALE_UART_BDH, // UART Baud Rate Register High + CYGHWR_DEV_FREESCALE_UART_BDL, // UART Baud Rate Register Low + CYGHWR_DEV_FREESCALE_UART_C1, // UART Control Register 1 + CYGHWR_DEV_FREESCALE_UART_C2, // UART Control Register 2 + CYGHWR_DEV_FREESCALE_UART_S1, // UART Status Register 1 + CYGHWR_DEV_FREESCALE_UART_S2, // UART Status Register 2 + CYGHWR_DEV_FREESCALE_UART_C3, // UART Control Register 3 + CYGHWR_DEV_FREESCALE_UART_D, // UART Data Register + CYGHWR_DEV_FREESCALE_UART_MA1, // UART Match Address Registers 1 + CYGHWR_DEV_FREESCALE_UART_MA2, // UART Match Address Registers 2 + CYGHWR_DEV_FREESCALE_UART_C4, // UART Control Register 4 + CYGHWR_DEV_FREESCALE_UART_C5, // UART Control Register 5 + CYGHWR_DEV_FREESCALE_UART_ED, // UART Extended Data Register + CYGHWR_DEV_FREESCALE_UART_MODEM, // UART Modem Register + CYGHWR_DEV_FREESCALE_UART_IR, // UART Infrared Register + CYGHWR_DEV_FREESCALE_UART_Res_0, + CYGHWR_DEV_FREESCALE_UART_PFIFO, // UART FIFO Parameters + CYGHWR_DEV_FREESCALE_UART_CFIFO, // UART FIFO Control Register + CYGHWR_DEV_FREESCALE_UART_SFIFO, // UART FIFO Status Register + CYGHWR_DEV_FREESCALE_UART_TWFIFO, // UART FIFO Transmit Watermark + CYGHWR_DEV_FREESCALE_UART_TCFIFO, // UART FIFO Transmit Count + CYGHWR_DEV_FREESCALE_UART_RWFIFO, // UART FIFO Receive Watermark + CYGHWR_DEV_FREESCALE_UART_RCFIFO, // UART FIFO Receive Count + CYGHWR_DEV_FREESCALE_UART_Res_1, + CYGHWR_DEV_FREESCALE_UART_C7816, // UART 7816 Control Register + CYGHWR_DEV_FREESCALE_UART_IE7816, // UART 7816 Interrupt Enable Register + CYGHWR_DEV_FREESCALE_UART_IS7816, // UART 7816 Interrupt Status Register + CYGHWR_DEV_FREESCALE_UART_WP7816_T0T1, // UART 7816 Wait Parameter Register + CYGHWR_DEV_FREESCALE_UART_WN7816, // UART 7816 Wait N Register + CYGHWR_DEV_FREESCALE_UART_WF7816, // UART 7816 Wait FD Register + CYGHWR_DEV_FREESCALE_UART_ET7816, // UART 7816 Error Threshold Register + CYGHWR_DEV_FREESCALE_UART_TL7816 // UART 7816 Transmit Length Register +}; + +// CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) should be provided by HAL. +// CYGHWR_IO_FREESCALE_UART_PIN(__pin) should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_RX should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_TX should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_RTS should be provided by HAL. +// CYGHWR_IO_FREESCALE_UARTn_PIN_CTS should be provided by HAL. + + +#define CYGHWR_DEV_FREESCALE_UART_C1_LOOPS (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C1_UARTSWAI (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C1_RSRC (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C1_M (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C1_WAKE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C1_ILT (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C1_PE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C1_PT (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_C2_TIE (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C2_TCIE (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C2_RIE (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C2_ILIE (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C2_TE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C2_RE (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C2_RWU (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C2_SBK (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_S1_TDRE (0x80) +#define CYGHWR_DEV_FREESCALE_UART_S1_TC (0x40) +#define CYGHWR_DEV_FREESCALE_UART_S1_RDRF (0x20) +#define CYGHWR_DEV_FREESCALE_UART_S1_IDLE (0x10) +#define CYGHWR_DEV_FREESCALE_UART_S1_OR (0x08) +#define CYGHWR_DEV_FREESCALE_UART_S1_NF (0x04) +#define CYGHWR_DEV_FREESCALE_UART_S1_FE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_S1_PF (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDIF (0x80) +#define CYGHWR_DEV_FREESCALE_UART_S2_RXEDGIF (0x40) +#define CYGHWR_DEV_FREESCALE_UART_S2_MSBF (0x20) +#define CYGHWR_DEV_FREESCALE_UART_S2_RXINV (0x10) +#define CYGHWR_DEV_FREESCALE_UART_S2_RWUID (0x08) +#define CYGHWR_DEV_FREESCALE_UART_S2_BRK13 (0x04) +#define CYGHWR_DEV_FREESCALE_UART_S2_LBKDE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_S2_RAF (0x01) + +#define CYGHWR_DEV_FREESCALE_UART_C3_R8 (0x80) +#define CYGHWR_DEV_FREESCALE_UART_C3_T8 (0x40) +#define CYGHWR_DEV_FREESCALE_UART_C3_TXDIR (0x20) +#define CYGHWR_DEV_FREESCALE_UART_C3_TXINV (0x10) +#define CYGHWR_DEV_FREESCALE_UART_C3_ORIE (0x08) +#define CYGHWR_DEV_FREESCALE_UART_C3_NEIE (0x04) +#define CYGHWR_DEV_FREESCALE_UART_C3_FEIE (0x02) +#define CYGHWR_DEV_FREESCALE_UART_C3_PEIE (0x01) + + +#endif // CYGONCE_DEVS_SERIAL_FREESCALE_UART_H