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changeset 3077:a49edf752d44

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* include/hal_intr.h: * cdl/hal_cortexm.cdl: Allow variant or platform to define their own RTC clock. Add CDL entry to select SysTick clock source. [ Bugzilla 1001090 ]
author sergeig
date Sat, 22 Jan 2011 21:00:52 +0000
parents a532b7c12094
children a1ee8818f5b4
files packages/hal/cortexm/arch/current/ChangeLog packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl packages/hal/cortexm/arch/current/include/hal_intr.h
diffstat 3 files changed, 39 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/cortexm/arch/current/ChangeLog
+++ b/packages/hal/cortexm/arch/current/ChangeLog
@@ -1,3 +1,10 @@
+2011-01-20  Christophe Coutand  <ccoutand@stmi.com>
+
+	* include/hal_intr.h:
+	* cdl/hal_cortexm.cdl:
+	Allow variant or platform to define their own RTC clock. Add
+	CDL entry to select SysTick clock source. [ Bugzilla 1001090 ]
+
 2010-12-28  Ilija Kocho <ilijak@siva.com.mk>
 
 	* include/hal_io.h: conditional VTOR setting.
--- a/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
+++ b/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
@@ -8,7 +8,7 @@
 ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
 ## -------------------------------------------                              
 ## This file is part of eCos, the Embedded Configurable Operating System.   
-## Copyright (C) 2008 Free Software Foundation, Inc.                        
+## Copyright (C) 2008, 2011 Free Software Foundation, Inc.                  
 ##
 ## eCos is free software; you can redistribute it and/or modify it under    
 ## the terms of the GNU General Public License as published by the Free     
@@ -108,6 +108,15 @@ cdl_package CYGPKG_HAL_CORTEXM {
             specification and executes the Thumb2 instruction set."
     }
 
+    cdl_option CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE {
+        display          "System tick timer clock"
+        flavor           data
+        legal_values     { "EXTERNAL" "INTERNAL" }
+        default_value    { "EXTERNAL" }
+        description      "
+             Select the Cortex-M system tick timer clock source."
+    }
+
     cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_MAX {
          display         "Maximum usable priority"
          flavor          data
--- a/packages/hal/cortexm/arch/current/include/hal_intr.h
+++ b/packages/hal/cortexm/arch/current/include/hal_intr.h
@@ -10,7 +10,7 @@
 // ####ECOSGPLCOPYRIGHTBEGIN####                                            
 // -------------------------------------------                              
 // This file is part of eCos, the Embedded Configurable Operating System.   
-// Copyright (C) 2008 Free Software Foundation, Inc.                        
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under    
 // the terms of the GNU General Public License as published by the Free     
@@ -56,6 +56,8 @@
 
 #include <cyg/hal/hal_io.h>
 
+#include <cyg/hal/var_intr.h>           // variant extensions
+
 //==========================================================================
 // Exception vectors
 //
@@ -92,7 +94,12 @@
 #define CYGNUM_HAL_INTERRUPT_SYS_TICK    0
 #define CYGNUM_HAL_INTERRUPT_EXTERNAL    1
 
+
+// Variant or platform allowed to override these definitions to use
+// a different RTC
+#ifndef CYGNUM_HAL_INTERRUPT_RTC
 #define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_SYS_TICK
+#endif
 
 //==========================================================================
 // Include variant definitions here.
@@ -321,10 +328,20 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 //==========================================================================
 // Clock control
 //
-// This uses the CPU SysTick timer.
+// This uses the CPU SysTick timer. Variant or platform allowed to override
+// these definitions
+
+#ifndef CYGHWR_HAL_CLOCK_DEFINED
 
 __externC cyg_uint32 hal_cortexm_systick_clock;
 
+// Select the clock source of the system tick timer
+#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_EXTERNAL
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_EXT
+#elif defined(CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL)
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT
+#endif
+
 #define HAL_CLOCK_INITIALIZE( __period )                                \
 {                                                                       \
     cyg_uint32 __p = __period;                                          \
@@ -333,7 +350,7 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
                      __p );                                             \
     HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR,    \
                      CYGARC_REG_SYSTICK_CSR_ENABLE      |               \
-                     CYGARC_REG_SYSTICK_CSR_CLK_EXT     );              \
+                     CYGARC_REG_SYSTICK_CSR_CLK_SRC     );              \
 }
 
 #define HAL_CLOCK_RESET( __vector, __period )                           \
@@ -354,6 +371,8 @@ typedef cyg_uint32  CYG_INTERRUPT_STATE;
 
 #define HAL_CLOCK_LATENCY( __pvalue ) HAL_CLOCK_READ( __pvalue )
 
+#endif // CYGHWR_HAL_CLOCK_DEFINED
+
 //==========================================================================
 // HAL_DELAY_US().
 //