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changeset 3243:c7cb4340f6eb

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Add: support for 32 channel eDMA, support for cached memory.
author vae
date Wed, 09 May 2012 22:07:24 +0000
parents 1057533611c4
children 139bc58bc0bd
files packages/devs/spi/freescale/dspi/current/ChangeLog packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c
diffstat 5 files changed, 34 insertions(+), 22 deletions(-) [+]
line wrap: on
line diff
--- a/packages/devs/spi/freescale/dspi/current/ChangeLog
+++ b/packages/devs/spi/freescale/dspi/current/ChangeLog
@@ -1,3 +1,11 @@
+2012-05-04  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/spi_freescale_dspi.cdl: 
+	* include/spi_freescale_dspi_buses.inl
+	* src/spi_freescale_dspi.c:
+	Add: support for 32 channel eDMA, support for cached memory.
+	[Bugzilla 1001579]
+
 2012-01-06  Ilija Kocho <ilijak@siva.com.mk>
 
 	* cdl/spi_freescale_dspi.cdl: 
--- a/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
+++ b/packages/devs/spi/freescale/dspi/current/cdl/spi_freescale_dspi.cdl
@@ -333,7 +333,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
                 cdl_component CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TX_DMA_PRI {
                     display "Transmit DMA channel priority"
                     flavor data
-                    legal_values  { 0 to (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM-1) 255 }
+                    legal_values  { 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 255 }
                     default_value 255
                     description "
                     DMA can work in either round robin or preeptve arbitration
@@ -360,9 +360,8 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
                 cdl_option CYGOPT_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_TCD_SECTION {
                     display "DMA TCD section"
                     flavor data
-                    default_value { "\".sram\"" }
-                    legal_values { "\".sram\"" "\".ram\"" }
-
+                    default_value CYGHWR_HAL_EDMA_TCD_SECTION
+ 
                     description "
                     Section in which will be DMA Transfer Control
                     Descriptors shall reside"
@@ -383,7 +382,7 @@ cdl_package CYGPKG_DEVS_SPI_FREESCALE_DS
                 cdl_component CYGNUM_DEVS_SPI_FREESCALE_DSPI[set ::spibus]_RX_DMA_PRI {
                     display "Receive DMA channel priority"
                     flavor data
-                    legal_values { 0 to (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM-1) 255 }
+                    legal_values { 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 255 }
                     default_value 255
                     description "
                     DMA can work in either round robin or preeptve arbitration
--- a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h
@@ -117,7 +117,7 @@ enum { SPI_DMA_CHAN_TX_I, SPI_DMA_CHAN_R
 typedef struct cyg_spi_freescale_dspi_bus_setup_s
 {
     cyghwr_devs_freescale_dspi_t*   dspi_p;    // Base address of SPI register block.
-    cyghwr_hal_freescale_dma_set_t* dma_set_p;       // DMA configuration block.
+    cyghwr_hal_freescale_dma_set_t* dma_set_p; // DMA configuration block.
     cyg_vector_t                    intr_num;        // DSPI interrupt vector
     cyg_priority_t                  intr_prio;       // Interrupt priority
     cyg_uint32                      mcr_opt ;        // Module Configuratyon Register options
--- a/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
+++ b/packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi_buses.inl
@@ -49,7 +49,6 @@
 //
 //=============================================================================
 
-
 #define PUSHQUE_ALIGN CYGBLD_ATTRIB_ALIGN(4)
 
 #define DSPI_DMA_BANDWIDTH FREESCALE_EDMA_CSR_BWC_0
@@ -64,7 +63,7 @@
 #define  CYGBLD_DSPI0_TCD_SECTION \
     CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI0_TCD_SECTION)
 
-extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1;
+extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0;
 
 // Pinonomy -------------------------------------------------------------------
 
@@ -106,7 +105,8 @@ static const cyg_uint32 spi0_cs_pins[] =
 static volatile
 cyg_uint32 dspi0_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI0_PUSHQUE_SIZE+4] PUSHQUE_ALIGN;
 
-static const cyghwr_hal_freescale_dma_chan_set_t dspi0_dma_chan[] = {
+static cyghwr_hal_freescale_dma_chan_set_t dspi0_dma_chan[] =
+{
     {
         .dma_src = FREESCALE_DMAMUX_SRC_SPI0_TX
         | FREESCALE_DMAMUX_CHCFG_ENBL_M,
@@ -122,8 +122,6 @@ static const cyghwr_hal_freescale_dma_ch
 };
 
 static cyghwr_hal_freescale_dma_set_t dspi0_dma_set = {
-    .edma_p = CYGHWR_IO_FREESCALE_EDMA0_P,
-    .dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P,
     .chan_p = dspi0_dma_chan,
     .chan_n = 2
 };
@@ -183,7 +181,7 @@ static const cyg_spi_freescale_dspi_bus_
                        FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI0_PCSIS)
 };
 
-cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1 = {
+cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0 = {
     .spi_bus.spi_transaction_begin    = dspi_transaction_begin,
     .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,
     .spi_bus.spi_transaction_tick     = dspi_transaction_tick,
@@ -258,9 +256,11 @@ static const cyg_uint32 spi1_cs_pins[] =
 
 #ifdef CYGINT_DEVS_SPI_DSPI1_USES_DMA
 static volatile
-cyg_uint32 dspi1_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE+4] PUSHQUE_ALIGN;
+cyg_uint32 dspi1_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI1_PUSHQUE_SIZE+4]
+           PUSHQUE_ALIGN EDMA_RAM_BUF_SECTION;
 
-static const cyghwr_hal_freescale_dma_chan_set_t dspi1_dma_chan[] = {
+static const cyghwr_hal_freescale_dma_chan_set_t dspi1_dma_chan[2] =
+{
     {
         .dma_src = FREESCALE_DMAMUX_SRC_SPI1_TX
         | FREESCALE_DMAMUX_CHCFG_ENBL_M,
@@ -276,8 +276,6 @@ static const cyghwr_hal_freescale_dma_ch
 };
 
 static cyghwr_hal_freescale_dma_set_t dspi1_dma_set = {
-    .edma_p = CYGHWR_IO_FREESCALE_EDMA0_P,
-    .dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P,
     .chan_p = dspi1_dma_chan,
     .chan_n = 2
 };
@@ -372,7 +370,7 @@ cyg_spi_freescale_dspi_bus_t cyg_spi_dsp
 #define  CYGBLD_DSPI2_TCD_SECTION \
     CYGBLD_ATTRIB_SECTION(CYGOPT_DEVS_SPI_FREESCALE_DSPI2_TCD_SECTION)
 
-extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1;
+extern cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2;
 
 // Pinonomy -------------------------------------------------------------------
 
@@ -414,7 +412,8 @@ static const cyg_uint32 spi2_cs_pins[] =
 static volatile
 cyg_uint32 dspi2_pushque[CYGNUM_DEVS_SPI_FREESCALE_DSPI2_PUSHQUE_SIZE+4] PUSHQUE_ALIGN;
 
-static const cyghwr_hal_freescale_dma_chan_set_t dspi2_dma_chan[] = {
+static const cyghwr_hal_freescale_dma_chan_set_t dspi2_dma_chan[] =
+{
     {
         .dma_src = FREESCALE_DMAMUX_SRC_SPI2_TX
         | FREESCALE_DMAMUX_CHCFG_ENBL_M,
@@ -430,8 +429,6 @@ static const cyghwr_hal_freescale_dma_ch
 };
 
 static cyghwr_hal_freescale_dma_set_t dspi2_dma_set = {
-    .edma_p = CYGHWR_IO_FREESCALE_EDMA0_P,
-    .dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P,
     .chan_p = dspi2_dma_chan,
     .chan_n = 2
 };
@@ -491,7 +488,7 @@ static const cyg_spi_freescale_dspi_bus_
                        FREESCALE_DSPI_MCR_PCSIS(CYGHWR_DEVS_SPI_FREESCALE_DSPI2_PCSIS)
 };
 
-cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1 = {
+cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2 = {
     .spi_bus.spi_transaction_begin    = dspi_transaction_begin,
     .spi_bus.spi_transaction_transfer = dspi_transaction_transfer,
     .spi_bus.spi_transaction_tick     = dspi_transaction_tick,
--- a/packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c
+++ b/packages/devs/spi/freescale/dspi/current/src/spi_freescale_dspi.c
@@ -47,11 +47,13 @@
 //
 //=============================================================================
 
+#include <pkgconf/hal.h>
 #include <string.h>
 #include <cyg/hal/hal_io.h>
 #include <cyg/hal/hal_if.h>
 #include <cyg/hal/hal_intr.h>
 #include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_cache.h>
 
 #include <cyg/infra/cyg_type.h>
 #include <cyg/infra/cyg_ass.h>
@@ -855,6 +857,12 @@ static void spi_transaction_do (cyg_spi_
                 tx_data += pushque_n;
         }
     }
+    if(dma_set_p && rx_data) {
+        // Rx buffer may be out of sync with cache.
+        DEBUG2_PRINTF("DSPI DMA: Invalidate cache\n");
+        HAL_DCACHE_INVALIDATE(rx_data, count);
+        DEBUG2_PRINTF("DSPI DMA: Cache invalidated\n");
+    }
     if(!polled)
         cyg_drv_interrupt_mask(dspi_bus->setup_p->intr_num);
 
@@ -965,7 +973,7 @@ static void dspi_transaction_end(cyg_spi
     cyg_spi_freescale_dspi_device_t* dspi_device =
           (cyg_spi_freescale_dspi_device_t*) device;
 
-    cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus->setup_p->dma_set_p;
+    const cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus->setup_p->dma_set_p;
     cyghwr_hal_freescale_edma_t *edma_p;
     cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus->setup_p->dspi_p;