Mercurial > nand-ecoscentric
changeset 2105:e7d311287dec
* Fixed data alignment problems. Cleaned up the naming of
functions to avoid name space pollution. Us the HAL macros to
access the hardware
line wrap: on
line diff
--- a/packages/devs/eth/arm/netarm/current/ChangeLog +++ b/packages/devs/eth/arm/netarm/current/ChangeLog @@ -1,3 +1,9 @@ +2005-11-17 Harald Brandl <Harald.Brandl@fh-joanneum.at> + + * Fixed data alignment problems. Cleaned up the naming of + functions to avoid name space pollution. Us the HAL macros to + access the hardware. + 2005-06-12 Harald Brandl <Harald.Brandl@fh-joanneum.at> * First import of an ethernet device driver for the NETARM
--- a/packages/devs/eth/arm/netarm/current/cdl/netarm_eth_driver.cdl +++ b/packages/devs/eth/arm/netarm/current/cdl/netarm_eth_driver.cdl @@ -10,7 +10,6 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2005 eCosCentric LTD ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -35,6 +34,8 @@ ## This exception does not invalidate any other reasons why a work based on ## this file might be covered by the GNU General Public License. ## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ ## ------------------------------------------- #####ECOSGPLCOPYRIGHTEND#### # ==================================================================== @@ -57,6 +58,7 @@ cdl_package CYGPKG_DEVS_ETH_ARM_NETARM { active_if CYGPKG_IO_ETH_DRIVERS + compile -library=libextras.a MII.c netarm_eth_drv.c eeprom.c define_proc {
--- a/packages/devs/eth/arm/netarm/current/doc/netarm_hal.patch +++ b/packages/devs/eth/arm/netarm/current/doc/netarm_hal.patch @@ -161,7 +161,7 @@ diff -Naur orig/hal/arm/netarm/current/i - diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h --- orig/hal/arm/netarm/current/include/hal_platform_setup.h 2004-11-29 17:35:46.000000000 +0100 -+++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-14 17:10:01.542675500 +0100 ++++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-15 12:20:27.760534400 +0100 @@ -19,7 +19,7 @@ // Usage: #include <cyg/hal/hal_platform_setup.h> // @@ -210,8 +210,9 @@ diff -Naur orig/hal/arm/netarm/current/i ldr r0,=0x4004a800 /* System control register */ str r0,[r1] -+#ifdef CYG_HAL_STARTUP_ROM - mov r0,#0 /* PLL config */ +- mov r0,#0 /* PLL config */ ++#ifdef CYG_HAL_STARTUP_ROM /* PLL config */ ++ mov r0,#0 +#else + ldr r0,=0x09000e1e +#endif @@ -241,7 +242,7 @@ diff -Naur orig/hal/arm/netarm/current/i /* Configure SDRAM */ - ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */ -+ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 (0xf38000b0)*/ ++ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 */ str r0,[r1,#0x24] ldr r0,=0x0000022d /* CS1 Base Address register */ @@ -371,6 +372,72 @@ diff -Naur orig/hal/arm/netarm/current/i } - - +diff -Naur orig/hal/arm/netarm/current/include/plf_mmap.h new/hal/arm/netarm/current/include/plf_mmap.h +--- orig/hal/arm/netarm/current/include/plf_mmap.h 1970-01-01 01:00:00.000000000 +0100 ++++ new/hal/arm/netarm/current/include/plf_mmap.h 2005-04-01 11:13:23.378304500 +0200 +@@ -0,0 +1,62 @@ ++#ifndef CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H ++#define CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H ++//========================================================================== ++// ++// plf_mmap.h ++// ++// Platform specific memory map support ++// ++//========================================================================== ++//####ECOSGPLCOPYRIGHTBEGIN#### ++// ------------------------------------------- ++// This file is part of eCos, the Embedded Configurable Operating System ++// Copyright (C) 2005 eCosCentric Ltd. ++// ++// eCos is free software; you can redistribute it and/or modify it under ++// the terms of the GNU General Public License as published by the Free ++// Software Foundation; either version 2 or (at your option) any later version. ++// ++// eCos is distributed in the hope that it will be useful, but WITHOUT ANY ++// WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// for more details. ++// ++// You should have received a copy of the GNU General Public License along ++// with eCos; if not, write to the Free Software Foundation, Inc., ++// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. ++// ++// As a special exception, if other files instantiate templates or use macros ++// or inline functions from this file, or you compile this file and link it ++// with other works to produce a work based on this file, this file does not ++// by itself cause the resulting work to be covered by the GNU General Public ++// License. However the source code for this file must still be made available ++// in accordance with section (3) of the GNU General Public License. ++// ++// This exception does not invalidate any other reasons why a work based on ++// this file might be covered by the GNU General Public License. ++// ++// ------------------------------------------- ++//####ECOSGPLCOPYRIGHTEND#### ++//========================================================================== ++//#####DESCRIPTIONBEGIN#### ++// ++// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) ++// Contributors: Harald Brandl ++// Date: 01.04.2005 ++// Purpose: NET+ARM memory map macro ++// Description: ++// ++//####DESCRIPTIONEND#### ++// ++//========================================================================== ++ ++ ++extern unsigned int _dataram; ++ ++ ++#define HAL_CACHED_TO_UNCACHED_ADDRESS( caddr, uaddr, type ) CYG_MACRO_START \ ++ uaddr = (type)((cyg_uint32)caddr - (cyg_uint32)(&_dataram)); \ ++CYG_MACRO_END ++ ++//--------------------------------------------------------------------------- ++#endif // CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H diff -Naur orig/hal/arm/netarm/current/src/netarm_misc.c new/hal/arm/netarm/current/src/netarm_misc.c --- orig/hal/arm/netarm/current/src/netarm_misc.c 2004-11-29 17:35:48.000000000 +0100 +++ new/hal/arm/netarm/current/src/netarm_misc.c 2005-02-22 11:57:58.296703200 +0100
--- a/packages/devs/eth/arm/netarm/current/doc/readme +++ b/packages/devs/eth/arm/netarm/current/doc/readme @@ -1,6 +1,4 @@ The HAL for the ARM NET+50 can be downloaded at ftp.mind.be -To support data and instruction caching I made some modification to -the HAL that are available as a patch to be found in this -directory. Applying this patch is optional, but should improve -performance. +To support data and instruction caching I made some modification +to the HAL that are available as patch. \ No newline at end of file
--- a/packages/devs/eth/arm/netarm/current/src/MII.c +++ b/packages/devs/eth/arm/netarm/current/src/MII.c @@ -8,7 +8,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -32,30 +32,30 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // -// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) -// Contributors: Harald Brandl -// Date: 01.08.2004 -// Purpose: PHY chip configuration +// Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) +// Contributors: Harald Brandl +// Date: 01.08.2004 +// Purpose: PHY chip configuration // Description: // //####DESCRIPTIONEND#### // //========================================================================== -#include <stdio.h> -#include <pkgconf/devs_eth_arm_netarm.h> -#include <cyg/hal/hal_diag.h> -#include <cyg/hal/hal_io.h> #include "eth_regs.h" + #define PHYS(_i_) (0x800 | _i_) -#define SysReg (unsigned int*)0xffb00004 // System Status Register +#define SysReg (unsigned *)0xffb00004 // System Status Register -/* Function: void mii_poll_busy (void) +/* Function: void cyg_netarm_mii_poll_busy (void) * * Description: * This routine is responsible for waiting for the current PHY @@ -65,14 +65,18 @@ * none */ -void mii_poll_busy(void) +static void +mii_poll_busy(void) { - /* check to see if PHY is busy with read or write */ - while (MIIIR & 1) - HAL_DELAY_US(1); + unsigned reg; + /* check to see if PHY is busy with read or write */ + do + { + HAL_READ_UINT32(MIIIR, reg); + }while (reg & 1); } -/* Function: void mii_reset (void) +/* Function: void cyg_netarm_mii_reset (void) * * Description: * @@ -82,14 +86,15 @@ void mii_poll_busy(void) * none */ -void mii_reset(void) +void +cyg_netarm_mii_reset(void) { - MIIAR = PHYS(0); // select command register - MIIWDR = 0x8000; // reset - mii_poll_busy(); + HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register + HAL_WRITE_UINT32(MIIWDR, 0x8000); // reset + mii_poll_busy(); } -/* Function: cyg_bool mii_negotiate (void) +/* Function: cyg_bool cyg_netarm_mii_negotiate (void) * * Description: * This routine is responsible for causing the external Ethernet PHY @@ -103,37 +108,40 @@ void mii_reset(void) * 1: ERROR */ -cyg_bool mii_negotiate(void) +cyg_bool +cyg_netarm_mii_negotiate(void) { - int timeout = 100000; - - MIIAR = PHYS(4); - - mii_poll_busy(); - - MIIAR = PHYS(0); - MIIWDR |= 0x1200; - - mii_poll_busy(); - - while(timeout) - { - MIIAR = PHYS(1); - MIICR = 1; - - mii_poll_busy(); - - if(0x24 == (MIIRDR & 0x24)) - return 0; - else - timeout--; - } - - return 1; + unsigned timeout = 100000, reg; + + HAL_WRITE_UINT32(MIIAR, PHYS(4)); + + mii_poll_busy(); + + HAL_WRITE_UINT32(MIIAR, PHYS(0)); + HAL_OR_UINT32(MIIWDR, 0x1200); + + mii_poll_busy(); + + while(timeout) + { + HAL_WRITE_UINT32(MIIAR, PHYS(1)); + HAL_WRITE_UINT32(MIICR, 1); + + mii_poll_busy(); + + HAL_READ_UINT32(MIIRDR, reg); + + if(0x24 == (reg & 0x24)) + return 0; + else + timeout--; + } + + return 1; } -/* Function: void mii_set_speed (cyg_bool speed, cyg_bool duplex) +/* Function: void cyg_netarm_mii_set_speed (cyg_bool speed, cyg_bool duplex) * * Description: * @@ -151,27 +159,28 @@ cyg_bool mii_negotiate(void) * none */ -void mii_set_speed(cyg_bool speed, cyg_bool duplex) +void +cyg_netarm_mii_set_speed(cyg_uint32 speed, cyg_bool duplex) { - unsigned long int timeout = 1000000; - - MIIAR = PHYS(0); // select command register - MIIWDR = (speed << 13) | (duplex << 8); // set speed and duplex - mii_poll_busy(); - - - while(timeout) - { - MIIAR = PHYS(1); // select status register - MIICR = 1; - mii_poll_busy(); - if((MIIRDR) & 0x4) - break; - timeout--; - } + unsigned timeout = 1000000, reg; + + HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register + HAL_WRITE_UINT32(MIIWDR, (speed << 13) | (duplex << 8)); // set speed and duplex + mii_poll_busy(); + + while(timeout) + { + HAL_WRITE_UINT32(MIIAR, PHYS(1)); // select status register + HAL_WRITE_UINT32(MIICR, 1); + mii_poll_busy(); + HAL_READ_UINT32(MIIRDR, reg); + if(reg & 0x4) + break; + timeout--; + } } -/* Function: cyg_bool mii_check_speed +/* Function: cyg_bool cyg_netarm_mii_check_speed * * Description: * @@ -186,15 +195,19 @@ void mii_set_speed(cyg_bool speed, cyg_b * 1: 100Mbit Speed */ -cyg_bool mii_check_speed(void) +cyg_uint32 +cyg_netarm_mii_check_speed(void) { - MIIAR = PHYS(17); - MIICR = 1; - mii_poll_busy(); - return (MIIRDR >> 14) & 1; + unsigned reg; + + HAL_WRITE_UINT32(MIIAR, PHYS(17)); + HAL_WRITE_UINT32(MIICR, 1); + mii_poll_busy(); + HAL_READ_UINT32(MIIRDR, reg); + return (reg >> 14) & 1; } -/* Function: void mii_check_duplex +/* Function: void cyg_netarm_mii_check_duplex * * Description: * @@ -209,10 +222,14 @@ cyg_bool mii_check_speed(void) * 1: Full Duplex */ -cyg_bool mii_check_duplex(void) +cyg_bool +cyg_netarm_mii_check_duplex(void) { - MIIAR = PHYS(17); - MIICR = 1; - mii_poll_busy(); - return (MIIRDR >> 9) & 1; + unsigned reg; + + HAL_WRITE_UINT32(MIIAR, PHYS(17)); + HAL_WRITE_UINT32(MIICR, 1); + mii_poll_busy(); + HAL_READ_UINT32(MIIRDR, reg); + return (reg >> 9) & 1; }
--- a/packages/devs/eth/arm/netarm/current/src/MII.h +++ b/packages/devs/eth/arm/netarm/current/src/MII.h @@ -1,5 +1,5 @@ -#ifndef _NETARM_MII_ -#define _NETARM_MII_ +#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_MII_H +#define CYGONCE_DEVS_ETH_ARM_NETARM_MII_H // ==================================================================== // // MII.h @@ -10,7 +10,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -34,23 +34,25 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +//####ECOSGPLCOPYRIGHTEND#### // ==================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) // Contributors: Harald Brandl -// Date: 01.08.2004 -// Purpose: Functions for PHY control +// Date: 01.08.2004 +// Purpose: Functions for PHY control // Description: // //####DESCRIPTIONEND#### // // ==================================================================== -void mii_reset(void); -void mii_set_speed (cyg_bool speed, cyg_bool duplex); -cyg_bool mii_check_speed(void); -cyg_bool mii_check_duplex(void); -cyg_bool mii_negotiate(void); +void cyg_netarm_mii_reset(void); +void cyg_netarm_mii_set_speed (cyg_uint32 speed, cyg_bool duplex); +cyg_uint32 cyg_netarm_mii_check_speed(void); +cyg_bool cyg_netarm_mii_check_duplex(void); +cyg_bool cyg_netarm_mii_negotiate(void); -#endif +#endif // CYGONCE_DEVS_ETH_ARM_NETARM_MII_H
--- a/packages/devs/eth/arm/netarm/current/src/eeprom.c +++ b/packages/devs/eth/arm/netarm/current/src/eeprom.c @@ -6,7 +6,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -30,175 +30,196 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +//####ECOSGPLCOPYRIGHTEND#### // ==================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) // Contributors: Harald Brandl -// Date: 10.03.2005 -// Purpose: EEPROM I/O +// Date: 10.03.2005 +// Purpose: EEPROM I/O // Description: // //####DESCRIPTIONEND#### // // ==================================================================== -#include <cyg/hal/hal_netarm.h> -#include <sys/types.h> +#include <cyg/hal/hal_modnet50.h> +#include "eth_regs.h" static void wait(int time) { - int i; - - for(i=0; i < time; i++); + int i; + + for(i=0; i < time; i++); } +/* send i2c stop condition */ static void i2cStop(void) { - *PORTC |= 0x00c00000; - *PORTC &= ~0x000000c0; // SDA = 0, SLK = 0 - wait(5); - *PORTC |= 0x00000040; // SLK = 1 - wait(5); - *PORTC |= 0x00000080; // SDA = 1 + HAL_OR_UINT32(PORTC, 0x00c00000); + HAL_AND_UINT32(PORTC, ~0x000000c0); // SDA = 0, SLK = 0 + wait(5); + HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1 + wait(5); + HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1 } +/* send i2c start condition */ static void i2cStart(void) { - *PORTC |= 0x00c000c0; // SDA = 1, SLK = 1 - wait(5); - *PORTC &= ~0x00000080; // SDA = 0 - wait(5); - *PORTC &= ~0x00000040; // SLK = 0 + HAL_OR_UINT32(PORTC, 0x00c000c0); // SDA = 1, SLK = 1 + wait(5); + HAL_AND_UINT32(PORTC, ~0x00000080); // SDA = 0 + wait(5); + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 } static void i2cPutByte(char byte) { - int i, bit; - - *PORTC |= 0x00c00000; - - for(i=7; i >= 0; i--) - { - bit = (byte >> i) & 1; - *PORTC = (*PORTC & ~0x80) | (bit << 7); // SDA = data - *PORTC |= 0x00000040; // SLK = 1 - wait(5); - *PORTC &= ~0x00000040; // SLK = 0 - wait(5); - } - *PORTC |= 0x00000080; // SDA = 1 + int i, bit, reg; + + HAL_OR_UINT32(PORTC, 0x00c00000); + + for(i=7; i >= 0; i--) + { + bit = (byte >> i) & 1; + HAL_READ_UINT32(PORTC, reg); + HAL_WRITE_UINT32(PORTC, (reg & ~0x80) | (bit << 7)); // SDA = data + HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1 + wait(5); + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 + wait(5); + } + HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1 } static char i2cGetByte(void) { - int i; - char byte = 0; - - *PORTC &= ~0x00800000; - for(i=7; i >= 0; i--) - { - *PORTC |= 0x00000040; // SLK = 1 - byte |= ((*PORTC & 0x80) >> 7) << i; // data = SDA - wait(5); - *PORTC &= ~0x00000040; // SLK = 0 - wait(5); - } - *PORTC |= 0x00800080; // SDA = 1 - return byte; + int i, reg; + char byte = 0; + + HAL_AND_UINT32(PORTC, ~0x00800000); + for(i=7; i >= 0; i--) + { + HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1 + HAL_READ_UINT32(PORTC, reg); + byte |= ((reg & 0x80) >> 7) << i; // data = SDA + wait(5); + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 + wait(5); + } + HAL_OR_UINT32(PORTC, 0x00800080); // SDA = 1 + return byte; } +/* acknowledge received bytes */ static void i2cGiveAck(void) { - *PORTC |= 0x00c00000; - *PORTC &= ~0x00000080; // SDA = 0 - wait(5); - *PORTC |= 0x00000040; // SLK = 1 - wait(5); - *PORTC &= ~0x00000040; // SLK = 0 - wait(5); - *PORTC |= 0x00000080; // SDA = 1 - wait(5); + HAL_OR_UINT32(PORTC, 0x00c00000); + HAL_AND_UINT32(PORTC, ~0x00000080); // SDA = 0 + wait(5); + HAL_OR_UINT32(PORTC, 0x00000040); // SLK = 1 + wait(5); + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 + wait(5); + HAL_OR_UINT32(PORTC, 0x00000080); // SDA = 1 + wait(5); } +/* wait for acknowledge from slaves */ static void i2cGetAck(void) { - *PORTC &= ~0x00800000; // SDA in - *PORTC |= 0x00400040; // SLK = 1 - while(*PORTC & 0x80); // wait for SDA = 1 - *PORTC &= ~0x00000040; // SLK = 0 + unsigned reg; + + HAL_AND_UINT32(PORTC, ~0x00800000); // SDA in + HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1 + do + { + HAL_READ_UINT32(PORTC, reg); + }while(reg & 0x80); // wait for SDA = 1 + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 } -void initI2C(void) +void cyg_netarm_initI2C(void) { - *PORTC &= ~0xc0000000; // mode GPIO - i2cStop(); + HAL_AND_UINT32(PORTC, ~0xc0000000); // mode GPIO + i2cStop(); } -void eepromPollAck(int deviceAddr) +/* wait until eeprom's internal write cycle has finished */ +void cyg_netarm_eepromPollAck(int deviceAddr) { - deviceAddr <<= 1; - - *PORTC |= 0x00400040; // SLK = 1 - while(1) - { - i2cStart(); - i2cPutByte(deviceAddr); - *PORTC &= ~0x00800000; // SDA in - *PORTC |= 0x00400040; // SLK = 1 - if((*PORTC & 0x80) == 0) - { - *PORTC &= ~0x00000040; // SLK = 0 - break; - } - *PORTC &= ~0x00000040; // SLK = 0 - } + unsigned reg; + + deviceAddr <<= 1; + + HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1 + while(1) + { + i2cStart(); + i2cPutByte(deviceAddr); + HAL_AND_UINT32(PORTC, ~0x00800000); // SDA in + HAL_OR_UINT32(PORTC, 0x00400040); // SLK = 1 + HAL_READ_UINT32(PORTC, reg); + if((reg & 0x80) == 0) + { + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 + break; + } + HAL_AND_UINT32(PORTC, ~0x00000040); // SLK = 0 + } } -void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes) +/* reads numBytes from eeprom starting at readAddr into buf */ +void cyg_netarm_eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes) { - int i; - - deviceAddr <<= 1; - i2cStart(); - i2cPutByte(deviceAddr); - i2cGetAck(); - i2cPutByte(readAddr >> 8); - i2cGetAck(); - i2cPutByte(readAddr & 0xff); - i2cGetAck(); - i2cStart(); - i2cPutByte(deviceAddr | 1); // set read flag - i2cGetAck(); - - for(i=0;i<numBytes;i++) - { - buf[i] = i2cGetByte(); - if(i < numBytes - 1) - i2cGiveAck(); - } - - i2cStop(); + int i; + + deviceAddr <<= 1; + i2cStart(); + i2cPutByte(deviceAddr); + i2cGetAck(); + i2cPutByte(readAddr >> 8); + i2cGetAck(); + i2cPutByte(readAddr & 0xff); + i2cGetAck(); + i2cStart(); + i2cPutByte(deviceAddr | 1); // set read flag + i2cGetAck(); + + for(i=0;i<numBytes;i++) + { + buf[i] = i2cGetByte(); + if(i < numBytes - 1) + i2cGiveAck(); + } + + i2cStop(); } -void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes) +/* writes up to a page of 32 bytes from buf into eeprom; +max. number of bytes depends on the offset within a page, indexed by the +lower 5 bits of writeAddr and equals 32 - offset */ +void cyg_netarm_eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes) { - int i; - - deviceAddr <<= 1; - i2cStart(); - i2cPutByte(deviceAddr); - i2cGetAck(); - i2cPutByte(writeAddr >> 8); - i2cGetAck(); - i2cPutByte(writeAddr & 0xff); - i2cGetAck(); - - for(i=0; i<numBytes; i++) - { - i2cPutByte(buf[i]); - i2cGetAck(); - } - - i2cStop(); + int i; + + deviceAddr <<= 1; + i2cStart(); + i2cPutByte(deviceAddr); + i2cGetAck(); + i2cPutByte(writeAddr >> 8); + i2cGetAck(); + i2cPutByte(writeAddr & 0xff); + i2cGetAck(); + + for(i=0; i<numBytes; i++) + { + i2cPutByte(buf[i]); + i2cGetAck(); + } + + i2cStop(); }
--- a/packages/devs/eth/arm/netarm/current/src/eeprom.h +++ b/packages/devs/eth/arm/netarm/current/src/eeprom.h @@ -1,5 +1,5 @@ -#ifndef _NETARM_EEPROM__ -#define _NETARM_EEPROM__ +#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H +#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H // ==================================================================== // @@ -9,7 +9,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -33,26 +33,28 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +//####ECOSGPLCOPYRIGHTEND#### // ==================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) // Contributors: Harald Brandl -// Date: 10.03.2005 -// Purpose: EEPROM interface +// Date: 10.03.2005 +// Purpose: EEPROM interface // Description: // //####DESCRIPTIONEND#### // // ==================================================================== + /* a block of max. 32 bytes can be written at once */ -void eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes); +void cyg_netarm_eepromWrite(int deviceAddr, int writeAddr, char *buf, int numBytes); /* reads out as many bytes as desired */ -void eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes); -/* blocks until the internal write cycle, initiated after eepromWrite, - completes */ -void eepromPollAck(int deviceAddr); -void initI2C(void); +void cyg_netarm_eepromRead(int deviceAddr, int readAddr, char *buf, int numBytes); +/* blocks until the internal write cycle, initiated after eepromWrite, completes */ +void cyg_netarm_eepromPollAck(int deviceAddr); +void cyg_netarm_initI2C(void); -#endif +#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_EEPROM_H
--- a/packages/devs/eth/arm/netarm/current/src/eth_regs.h +++ b/packages/devs/eth/arm/netarm/current/src/eth_regs.h @@ -1,5 +1,6 @@ -#ifndef _NETARM_ethregs_ -#define _NETARM_ethregs_ +#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H +#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H + // ==================================================================== // // eth_regs.h @@ -10,7 +11,7 @@ //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -34,6 +35,8 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +//####ECOSGPLCOPYRIGHTEND#### // ==================================================================== //#####DESCRIPTIONBEGIN#### // @@ -47,74 +50,98 @@ // // ==================================================================== +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> + + +#ifndef HAL_OR_UINT32 +#define HAL_OR_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + cyg_uint32 _i_; \ + HAL_READ_UINT32( _register_, _i_ ); \ + _i_ |= _value_; \ + HAL_WRITE_UINT32( _register_, _i_ ); \ + CYG_MACRO_END +#endif + +#ifndef HAL_AND_UINT32 +#define HAL_AND_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + cyg_uint32 _i_; \ + HAL_READ_UINT32( _register_, _i_ ); \ + _i_ &= _value_; \ + HAL_WRITE_UINT32( _register_, _i_ ); \ + CYG_MACRO_END +#endif + // Ethernet -#define EthGenCR *(volatile unsigned *)0xff800000 -#define EthGenSR *(volatile unsigned *)0xff800004 -#define EthFIFODR *(volatile unsigned *)0xff800008 -#define EthFIFODRkickoff *(volatile unsigned *)0xff80000c -#define EthTxSR *(volatile unsigned *)0xff800010 -#define EthRxSR *(volatile unsigned *)0xff800014 -#define MACCR *(volatile unsigned *)0xff800400 -#define MACTR *(volatile unsigned *)0xff800404 -#define PCSCR *(volatile unsigned *)0xff800408 -#define PCSTR *(volatile unsigned *)0xff80040c -#define STLCR *(volatile unsigned *)0xff800410 -#define STLTR *(volatile unsigned *)0xff800414 -#define BtBIPGGapTimerR *(volatile unsigned *)0xff800440 -#define NonBtBIPGGapTimerR *(volatile unsigned *)0xff800444 -#define CollWinR *(volatile unsigned *)0xff800448 -#define TxPNCR *(volatile unsigned *)0xff800460 -#define TxBCR *(volatile unsigned *)0xff800464 -#define ReTxBCR *(volatile unsigned *)0xff800468 -#define TxRNG *(volatile unsigned *)0xff80046c -#define TxMRN *(volatile unsigned *)0xff800470 -#define TxCDec *(volatile unsigned *)0xff800474 -#define TOTxC *(volatile unsigned *)0xff800478 -#define RxBC *(volatile unsigned *)0xff800480 -#define RxCDec *(volatile unsigned *)0xff800484 -#define TORxC *(volatile unsigned *)0xff800488 -#define LnFC *(volatile unsigned *)0xff8004c0 -#define JC10M *(volatile unsigned *)0xff800500 -#define LoCC10M *(volatile unsigned *)0xff800504 -#define MIICR *(volatile unsigned *)0xff800540 -#define MIIAR *(volatile unsigned *)0xff800544 -#define MIIWDR *(volatile unsigned *)0xff800548 -#define MIIRDR *(volatile unsigned *)0xff80054c -#define MIIIR *(volatile unsigned *)0xff800550 -#define CRCEC *(volatile unsigned *)0xff800580 -#define AEC *(volatile unsigned *)0xff800584 -#define CEC *(volatile unsigned *)0xff800588 -#define LFC *(volatile unsigned *)0xff80058c -#define SFC *(volatile unsigned *)0xff800590 -#define LCC *(volatile unsigned *)0xff800594 -#define EDC *(volatile unsigned *)0xff800598 -#define MCC *(volatile unsigned *)0xff80059c -#define SAFR *(volatile unsigned *)0xff8005c0 -#define SAR1 *(volatile unsigned *)0xff8005c4 -#define SAR2 *(volatile unsigned *)0xff8005c8 -#define SAR3 *(volatile unsigned *)0xff8005cc -#define SAMHT1 *(volatile unsigned *)0xff8005d0 -#define SAMHT2 *(volatile unsigned *)0xff8005d4 -#define SAMHT3 *(volatile unsigned *)0xff8005d8 -#define SAMHT4 *(volatile unsigned *)0xff8005dc +#define EthGenCR (unsigned *)0xff800000 +#define EthGenSR (unsigned *)0xff800004 +#define EthFIFODR (unsigned *)0xff800008 +#define EthFIFODRkickoff (unsigned *)0xff80000c +#define EthTxSR (unsigned *)0xff800010 +#define EthRxSR (unsigned *)0xff800014 +#define MACCR (unsigned *)0xff800400 +#define MACTR (unsigned *)0xff800404 +#define PCSCR (unsigned *)0xff800408 +#define PCSTR (unsigned *)0xff80040c +#define STLCR (unsigned *)0xff800410 +#define STLTR (unsigned *)0xff800414 +#define BtBIPGGapTimerR (unsigned *)0xff800440 +#define NonBtBIPGGapTimerR (unsigned *)0xff800444 +#define CollWinR (unsigned *)0xff800448 +#define TxPNCR (unsigned *)0xff800460 +#define TxBCR (unsigned *)0xff800464 +#define ReTxBCR (unsigned *)0xff800468 +#define TxRNG (unsigned *)0xff80046c +#define TxMRN (unsigned *)0xff800470 +#define TxCDec (unsigned *)0xff800474 +#define TOTxC (unsigned *)0xff800478 +#define RxBC (unsigned *)0xff800480 +#define RxCDec (unsigned *)0xff800484 +#define TORxC (unsigned *)0xff800488 +#define LnFC (unsigned *)0xff8004c0 +#define JC10M (unsigned *)0xff800500 +#define LoCC10M (unsigned *)0xff800504 +#define MIICR (unsigned *)0xff800540 +#define MIIAR (unsigned *)0xff800544 +#define MIIWDR (unsigned *)0xff800548 +#define MIIRDR (unsigned *)0xff80054c +#define MIIIR (unsigned *)0xff800550 +#define CRCEC (unsigned *)0xff800580 +#define AEC (unsigned *)0xff800584 +#define CEC (unsigned *)0xff800588 +#define LFC (unsigned *)0xff80058c +#define SFC (unsigned *)0xff800590 +#define LCC (unsigned *)0xff800594 +#define EDC (unsigned *)0xff800598 +#define MCC (unsigned *)0xff80059c +#define SAFR (unsigned *)0xff8005c0 +#define SAR1 (unsigned *)0xff8005c4 +#define SAR2 (unsigned *)0xff8005c8 +#define SAR3 (unsigned *)0xff8005cc +#define SAMHT1 (unsigned *)0xff8005d0 +#define SAMHT2 (unsigned *)0xff8005d4 +#define SAMHT3 (unsigned *)0xff8005d8 +#define SAMHT4 (unsigned *)0xff8005dc // DMA -#define DMA1A_BDP *(volatile unsigned *)0xff900000 -#define DMA1A_CR *(volatile unsigned *)0xff900010 -#define DMA1A_SR *(volatile unsigned *)0xff900014 -#define DMA1B_BDP *(volatile unsigned *)0xff900020 -#define DMA1B_CR *(volatile unsigned *)0xff900030 -#define DMA1B_SR *(volatile unsigned *)0xff900034 -#define DMA1C_BDP *(volatile unsigned *)0xff900040 -#define DMA1C_CR *(volatile unsigned *)0xff900050 -#define DMA1C_SR *(volatile unsigned *)0xff900054 -#define DMA1D_BDP *(volatile unsigned *)0xff900060 -#define DMA1D_CR *(volatile unsigned *)0xff900070 -#define DMA1D_SR *(volatile unsigned *)0xff900074 -#define DMA2_BDP *(volatile unsigned *)0xff900080 -#define DMA2_CR *(volatile unsigned *)0xff900090 -#define DMA2_SR *(volatile unsigned *)0xff900094 +#define DMA1A_BDP (unsigned *)0xff900000 +#define DMA1A_CR (unsigned *)0xff900010 +#define DMA1A_SR (unsigned *)0xff900014 +#define DMA1B_BDP (unsigned *)0xff900020 +#define DMA1B_CR (unsigned *)0xff900030 +#define DMA1B_SR (unsigned *)0xff900034 +#define DMA1C_BDP (unsigned *)0xff900040 +#define DMA1C_CR (unsigned *)0xff900050 +#define DMA1C_SR (unsigned *)0xff900054 +#define DMA1D_BDP (unsigned *)0xff900060 +#define DMA1D_CR (unsigned *)0xff900070 +#define DMA1D_SR (unsigned *)0xff900074 +#define DMA2_BDP (unsigned *)0xff900080 +#define DMA2_CR (unsigned *)0xff900090 +#define DMA2_SR (unsigned *)0xff900094 -#endif +#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_REGS_H
--- a/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.c +++ b/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.c @@ -7,8 +7,8 @@ //========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// This file is part of eCos, the Embedded Configurable Operating System +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -32,6 +32,9 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // @@ -54,20 +57,12 @@ #include <pkgconf/devs_eth_arm_netarm.h> #include <cyg/hal/hal_platform_ints.h> +#include <cyg/hal/plf_mmap.h> #include "eth_regs.h" #include "MII.h" #include "netarm_eth_drv.h" #include "eeprom.h" -#include <cyg/hal/hal_io.h> - -// FIXME: The HAL should provide this -#define CYGNUM_HAL_INTERRUPT_DMA2 31 -#define CYGNUM_HAL_INTERRUPT_DMA1 32 - -// FIXME: The HAL should provide this and it should handle more than -// RAM addresses -#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr ) (unsigned char *)vaddr - 0x8000000 #define BufferSizeA 128 #define BufferSizeB 512 @@ -77,33 +72,37 @@ #define NumB 8 #define NumC 8 -#define EEPROM_MAC 0 // location of MAC address inside eeprom +#define EEPROM_MAC 0 // location of MAC address inside eeprom + static cyg_mutex_t Key_Mutex; static private_data_t driver_private; -static volatile unsigned char RxBufferA[NumA][BufferSizeA]; -static volatile unsigned char RxBufferB[NumB][BufferSizeB]; -static volatile unsigned char RxBufferC[NumC][BufferSizeC]; +static unsigned char RxBufferA[NumA][BufferSizeA] __attribute__ ((aligned (4))); +static unsigned char RxBufferB[NumB][BufferSizeB] __attribute__ ((aligned (4))); +static unsigned char RxBufferC[NumC][BufferSizeC] __attribute__ ((aligned (4))); + +static unsigned char TxBuffer[1518] __attribute__ ((aligned (4))); -static volatile unsigned char TxBuffer[1500]; -static volatile unsigned char TxHeader[14]; +static BDP_t RxBDP_A[NumA]; +static BDP_t RxBDP_B[NumB]; +static BDP_t RxBDP_C[NumC]; -static volatile BDP_t RxBDP_A[NumA]; -static volatile BDP_t RxBDP_B[NumB]; -static volatile BDP_t RxBDP_C[NumC]; - -static volatile BDP_t TxBDP[2]; +static BDP_t TxBDP; // relocation pointer for data accessed by DMA to enable caching -static volatile unsigned char *pRxBufferA, *pRxBufferB, *pRxBufferC; -static volatile unsigned char *pTxHeader, *pTxBuffer; -static volatile BDP_t *pRxBDP_A, *pRxBDP_B, *pRxBDP_C; -static volatile BDP_t *pTxBDP; +static unsigned char *pRxBufferA = (unsigned char *)RxBufferA, + *pRxBufferB = (unsigned char *)RxBufferB, + *pRxBufferC = (unsigned char *)RxBufferC; +static unsigned char *pTxBuffer = TxBuffer; + +static BDP_t *pRxBDP_A = RxBDP_A, *pRxBDP_B = RxBDP_B, *pRxBDP_C = RxBDP_C; +static BDP_t *pTxBDP = &TxBDP; + ETH_DRV_SC(netarm_sc, - (void *)&driver_private, // driver specific data - "eth0", // Name for this interface + (void *)&driver_private, // driver specific data + "eth0", // name for this interface netarm_start, netarm_stop, netarm_control, @@ -114,585 +113,581 @@ ETH_DRV_SC(netarm_sc, netarm_poll, netarm_int_vector); + NETDEVTAB_ENTRY(netarm_netdev, "ETH_DRV", netarm_init, &netarm_sc); + +#ifdef __thumb__ + #define fastcopy memcpy +#else static void fastcopy(void *buf, void *data, unsigned long len) { - asm volatile( - - "STMDB SP!, {R11};" - - "TST R1, #2;" // test if aligned - "LDRNEH R3, [R1], #2;" - "STRNEH R3, [R0], #2;" - "SUBNE R2, R2, #2;" - "TST R1, #1;" - "LDRNEB R3, [R1], #1;" - "STRNEB R3, [R0], #1;" - "SUBNE R2, R2, #1;" - - ".START:" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "CMP R2, #44;" - "BLT .LASTBYTES;" - "LDMIA R1!, {R3 - R12, R14};" - "STMIA R0!, {R3 - R12, R14};" - "SUB R2, R2, #44;" - - "BGE .START;" - - - ".LASTBYTES:" - - "AND R14, R2, #0xfffffffc;" - "LDR PC, [PC, R14];" - "NOP;" - - ".SWITCH:" - ".word .CASE0;" - ".word .CASE1;" - ".word .CASE2;" - ".word .CASE3;" - ".word .CASE4;" - ".word .CASE5;" - ".word .CASE6;" - ".word .CASE7;" - ".word .CASE8;" - ".word .CASE9;" - ".word .CASE10;" - - ".CASE0:" - "B .END;" - - ".CASE1:" - "LDR R3, [R1]!;" - "STR R3, [R0]!;" - "B .END;" - - ".CASE2:" - "LDMIA R1!, {R3, R4};" - "STMIA R0!, {R3, R4};" - "B .END;" - - ".CASE3:" - "LDMIA R1!, {R3 - R5};" - "STMIA R0!, {R3 - R5};" - "B .END;" - - ".CASE4:" - "LDMIA R1!, {R3 - R6};" - "STMIA R0!, {R3 - R6};" - "B .END;" - - ".CASE5:" - "LDMIA R1!, {R3 - R7};" - "STMIA R0!, {R3 - R7};" - "B .END;" - - ".CASE6:" - "LDMIA R1!, {R3 - R8};" - "STMIA R0!, {R3 - R8};" - "B .END;" - - ".CASE7:" - "LDMIA R1!, {R3 - R9};" - "STMIA R0!, {R3 - R9};" - "B .END;" - - ".CASE8:" - "LDMIA R1!, {R3 - R10};" - "STMIA R0!, {R3 - R10};" - "B .END;" - - ".CASE9:" - "LDMIA R1!, {R3 - R11};" - "STMIA R0!, {R3 - R11};" - "B .END;" - - ".CASE10:" - "LDMIA R1!, {R3 - R12};" - "STMIA R0!, {R3 - R12};" - - ".END:" - "TST R2, #2;" - "LDRNEH R3, [R1], #2;" - "STRNEH R3, [R0], #2;" - "TST R2, #1;" - "LDRNEB R3, [R1], #1;" - "STRNEB R3, [R0], #1;" - - "LDMIA SP!, {R11};" - - : - : "r" (buf), "r" (data), "r" (len) - : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14" - ); + asm volatile( + + "STMDB SP!, {R11};" + + "TST R1, #2;" // test if aligned + "LDRNEH R3, [R1], #2;" + "STRNEH R3, [R0], #2;" + "SUBNE R2, R2, #2;" + "TST R1, #1;" + "LDRNEB R3, [R1], #1;" + "STRNEB R3, [R0], #1;" + "SUBNE R2, R2, #1;" + + ".START%=:" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "CMP R2, #44;" + "BLT .LASTBYTES%=;" + "LDMIA R1!, {R3 - R12, R14};" + "STMIA R0!, {R3 - R12, R14};" + "SUB R2, R2, #44;" + + "BGE .START%=;" + + + ".LASTBYTES%=:" + + "AND R14, R2, #0xfffffffc;" + "LDR PC, [PC, R14];" + "NOP;" + + ".SWITCH%=:" + ".word .CASE0%=;" + ".word .CASE1%=;" + ".word .CASE2%=;" + ".word .CASE3%=;" + ".word .CASE4%=;" + ".word .CASE5%=;" + ".word .CASE6%=;" + ".word .CASE7%=;" + ".word .CASE8%=;" + ".word .CASE9%=;" + ".word .CASE10%=;" + + ".CASE0%=:" + "B .END%=;" + + ".CASE1%=:" + "LDMIA R1!, {R3};" + "STMIA R0!, {R3};" + "B .END%=;" + + ".CASE2%=:" + "LDMIA R1!, {R3, R4};" + "STMIA R0!, {R3, R4};" + "B .END%=;" + + ".CASE3%=:" + "LDMIA R1!, {R3 - R5};" + "STMIA R0!, {R3 - R5};" + "B .END%=;" + + ".CASE4%=:" + "LDMIA R1!, {R3 - R6};" + "STMIA R0!, {R3 - R6};" + "B .END%=;" + + ".CASE5%=:" + "LDMIA R1!, {R3 - R7};" + "STMIA R0!, {R3 - R7};" + "B .END%=;" + + ".CASE6%=:" + "LDMIA R1!, {R3 - R8};" + "STMIA R0!, {R3 - R8};" + "B .END%=;" + + ".CASE7%=:" + "LDMIA R1!, {R3 - R9};" + "STMIA R0!, {R3 - R9};" + "B .END%=;" + + ".CASE8%=:" + "LDMIA R1!, {R3 - R10};" + "STMIA R0!, {R3 - R10};" + "B .END%=;" + + ".CASE9%=:" + "LDMIA R1!, {R3 - R11};" + "STMIA R0!, {R3 - R11};" + "B .END%=;" + + ".CASE10%=:" + "LDMIA R1!, {R3 - R12};" + "STMIA R0!, {R3 - R12};" + + ".END%=:" + "TST R2, #2;" + "LDRNEH R3, [R1], #2;" + "STRNEH R3, [R0], #2;" + "TST R2, #1;" + "LDRNEB R3, [R1], #1;" + "STRNEB R3, [R0], #1;" + + "LDMIA SP!, {R11};" + + : + : "r" (buf), "r" (data), "r" (len) + : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14" + ); } +#endif static bool KeyBufferFull(private_data_t *pd) { - int tmp = 0; - - cyg_drv_mutex_lock(&Key_Mutex); - - if((pd->key_head + 1) % MaxKeys == pd->key_tail) - { - tmp = 1; - } - - cyg_drv_mutex_unlock(&Key_Mutex); - - return tmp; + int tmp = 0; + + cyg_drv_mutex_lock(&Key_Mutex); + + if((pd->key_head + 1) % MaxKeys == pd->key_tail) + { + tmp = 1; + } + + cyg_drv_mutex_unlock(&Key_Mutex); + + return tmp; } + static void AddKey(unsigned long key, private_data_t *pd) { - - cyg_drv_mutex_lock(&Key_Mutex); - - pd->KeyBuffer[pd->key_head] = key; - pd->key_head = (pd->key_head + 1) % MaxKeys; - - cyg_drv_mutex_unlock(&Key_Mutex); + + cyg_drv_mutex_lock(&Key_Mutex); + + pd->KeyBuffer[pd->key_head] = key; + pd->key_head = (pd->key_head + 1) % MaxKeys; + + cyg_drv_mutex_unlock(&Key_Mutex); } static unsigned GetKey(private_data_t *pd) { - unsigned key = 0; - - cyg_drv_mutex_lock(&Key_Mutex); - - if(pd->key_tail != pd->key_head) - { - key = pd->KeyBuffer[pd->key_tail]; - pd->key_tail = (pd->key_tail + 1) % MaxKeys; - } - - cyg_drv_mutex_unlock(&Key_Mutex); - - return key; + unsigned key = 0; + + cyg_drv_mutex_lock(&Key_Mutex); + + if(pd->key_tail != pd->key_head) + { + key = pd->KeyBuffer[pd->key_tail]; + pd->key_tail = (pd->key_tail + 1) % MaxKeys; + } + + cyg_drv_mutex_unlock(&Key_Mutex); + + return key; } + static cyg_uint32 dma_rx_isr(cyg_vector_t vector, cyg_addrword_t data) { - - // block this interrupt until the dsr completes - cyg_drv_interrupt_mask(vector); - - // tell ecos to allow further interrupt processing - cyg_drv_interrupt_acknowledge(vector); - - return CYG_ISR_CALL_DSR; // call the dsr + + // block this interrupt until the dsr completes + cyg_drv_interrupt_mask(vector); + + // tell ecos to allow further interrupt processing + cyg_drv_interrupt_acknowledge(vector); + + return CYG_ISR_CALL_DSR; // call the dsr } static void dma_rx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { - - eth_drv_dsr( vector, count, data ); - - DMA1A_SR = 0x80000000; // acknowledge and mask interrupts - DMA1B_SR = 0x80000000; - DMA1C_SR = 0x80000000; - - cyg_drv_interrupt_unmask(vector); + + eth_drv_dsr( vector, count, data ); + + HAL_WRITE_UINT32(DMA1A_SR, 0x80000000); // acknowledge and mask interrupts + HAL_WRITE_UINT32(DMA1B_SR, 0x80000000); + HAL_WRITE_UINT32(DMA1C_SR, 0x80000000); + + cyg_drv_interrupt_unmask(vector); } static cyg_uint32 dma_tx_isr(cyg_vector_t vector, cyg_addrword_t data) { - - // block this interrupt until the dsr completes - cyg_drv_interrupt_mask(vector); - - // tell ecos to allow further interrupt processing - cyg_drv_interrupt_acknowledge(vector); - - return CYG_ISR_CALL_DSR; // invoke the dsr + + // block this interrupt until the dsr completes + cyg_drv_interrupt_mask(vector); + + // tell ecos to allow further interrupt processing + cyg_drv_interrupt_acknowledge(vector); + + return CYG_ISR_CALL_DSR; // invoke the dsr } static void dma_tx_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { - - eth_drv_dsr( vector, count, data ); - - DMA2_SR |= 0x80000000; // acknowledge interrupt - - cyg_drv_interrupt_unmask(vector); + + eth_drv_dsr( vector, count, data ); + + HAL_OR_UINT32(DMA2_SR, 0x80000000); // acknowledge interrupt + + cyg_drv_interrupt_unmask(vector); } static void -SetupDMA(void) +setupDMA(void) { - int i; - - pRxBufferA = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferA); - pRxBufferB = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferB); - pRxBufferC = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(RxBufferC); - - pTxBuffer = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxBuffer); - pTxHeader = (unsigned char *)HAL_VIRT_TO_PHYS_ADDRESS(TxHeader); - - pRxBDP_A = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_A); - pRxBDP_B = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_B); - pRxBDP_C = (BDP_t *)HAL_VIRT_TO_PHYS_ADDRESS(RxBDP_C); - - pTxBDP = (BDP_t *)((unsigned char *)TxBDP); - - *SYSCON |= 0x40; // reset DMA module - - for(i = 0; i < NumA; i++) - { - pRxBDP_A[i].lo = ((unsigned)(pRxBufferA+i*BufferSizeA)) & 0x3fffffff; - pRxBDP_A[i].hi = BufferSizeA; - } - - pRxBDP_A[i - 1].lo |= 0x80000000; // set W bit - - for(i = 0; i < NumB; i++) - { - pRxBDP_B[i].lo = ((unsigned)(pRxBufferB+i*BufferSizeB)) & 0x3fffffff; - pRxBDP_B[i].hi = BufferSizeB; - } - - pRxBDP_B[i - 1].lo |= 0x80000000; - - for(i = 0; i < NumC; i++) - { - pRxBDP_C[i].lo = ((unsigned)(pRxBufferC+i*BufferSizeC)) & 0x3fffffff; - pRxBDP_C[i].hi = BufferSizeC; - } - - pRxBDP_C[i - 1].lo |= 0x80000000; - - *SYSCON &= ~0x40; - - DMA1A_BDP = (unsigned)pRxBDP_A; - DMA1A_CR = 0x82000000; //burst transfer - DMA1A_SR = 0xa00000; - - DMA1B_BDP = (unsigned)pRxBDP_B; - DMA1B_CR = 0x82000000; //burst transfer - DMA1B_SR = 0xa00000; - - DMA1C_BDP = (unsigned)pRxBDP_C; - DMA1C_CR = 0x82000000; //burst transfer - DMA1C_SR = 0xa00000; - - - pTxBDP[0].lo = ((unsigned)pTxHeader) & 0x3fffffff; - pTxBDP[1].lo = ((unsigned)pTxBuffer) & 0x3fffffff; - pTxBDP[1].lo |= 0xa0000000; // set W and L bit - - DMA2_BDP = (unsigned)pTxBDP; - DMA2_CR = 0x86000000; //burst transfer - DMA2_SR = 0x800000; - + int i; + + /* map DMA shared data to non-cached ram */ +#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferA, pRxBufferA, unsigned char *); + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferB, pRxBufferB, unsigned char *); + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBufferC, pRxBufferC, unsigned char *); + + HAL_CACHED_TO_UNCACHED_ADDRESS(TxBuffer, pTxBuffer, unsigned char *); + + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_A, pRxBDP_A, BDP_t *); + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_B, pRxBDP_B, BDP_t *); + HAL_CACHED_TO_UNCACHED_ADDRESS(RxBDP_C, pRxBDP_C, BDP_t *); + + HAL_CACHED_TO_UNCACHED_ADDRESS(TxBDP, pTxBDP, BDP_t * ); +#endif + + HAL_OR_UINT32(SYSCON, 0x40); // reset DMA module + + for(i = 0; i < NumA; i++) + { + pRxBDP_A[i].lo = ((unsigned)(pRxBufferA + i*BufferSizeA)) & 0x3fffffff; + pRxBDP_A[i].hi = BufferSizeA; + } + + pRxBDP_A[i - 1].lo |= 0x80000000; // set W bit + + for(i = 0; i < NumB; i++) + { + pRxBDP_B[i].lo = ((unsigned)(pRxBufferB + i*BufferSizeB)) & 0x3fffffff; + pRxBDP_B[i].hi = BufferSizeB; + } + + pRxBDP_B[i - 1].lo |= 0x80000000; + + for(i = 0; i < NumC; i++) + { + pRxBDP_C[i].lo = ((unsigned)(pRxBufferC + i*BufferSizeC)) & 0x3fffffff; + pRxBDP_C[i].hi = BufferSizeC; + } + + pRxBDP_C[i - 1].lo |= 0x80000000; + + HAL_AND_UINT32(SYSCON, ~0x40); + + HAL_WRITE_UINT32(DMA1A_BDP, (unsigned)pRxBDP_A); + HAL_WRITE_UINT32(DMA1A_CR, 0x82000000); //burst transfer + HAL_WRITE_UINT32(DMA1A_SR, 0xa00000); + + HAL_WRITE_UINT32(DMA1B_BDP, (unsigned)pRxBDP_B); + HAL_WRITE_UINT32(DMA1B_CR, 0x82000000); //burst transfer + HAL_WRITE_UINT32(DMA1B_SR, 0xa00000); + + HAL_WRITE_UINT32(DMA1C_BDP, (unsigned)pRxBDP_C); + HAL_WRITE_UINT32(DMA1C_CR, 0x82000000); //burst transfer + HAL_WRITE_UINT32(DMA1C_SR, 0xa00000); + + + pTxBDP->lo = ((unsigned)pTxBuffer) & 0x3fffffff; + pTxBDP->lo |= 0xa0000000; // set W and L bit + + HAL_WRITE_UINT32(DMA2_BDP, (unsigned)pTxBDP); + HAL_WRITE_UINT32(DMA2_CR, 0x86000000); //burst transfer + HAL_WRITE_UINT32(DMA2_SR, 0x800000); } + static bool netarm_init(struct cyg_netdevtab_entry *tab) { - struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; - cyg_bool duplex; - static cyg_interrupt dma_rx_int_object, dma_tx_int_object; - static cyg_handle_t dma_rx_int_handle, dma_tx_int_handle; - + struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; + cyg_bool duplex; + static cyg_interrupt dma_rx_int_object, dma_tx_int_object; + static cyg_handle_t dma_rx_int_handle, dma_tx_int_handle; + #ifdef CYGSEM_DEVS_ETH_ARM_NETARM_ETH0_SET_ESA - - unsigned char esa[6] = CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA; + + unsigned char esa[6] = CYGDAT_DEVS_ETH_ARM_NETARM_ETH0_ESA; #else - unsigned char esa[6]; - - initI2C(); - eepromRead(0x50, EEPROM_MAC, esa, 6); + unsigned char esa[6]; + + cyg_netarm_initI2C(); + cyg_netarm_eepromRead(0x50, EEPROM_MAC, esa, 6); #endif - - // setup dma receiver - SetupDMA(); - - mii_reset(); - mii_negotiate(); // initialize PHY - duplex = mii_check_duplex(); - - // Ethernet Controller Initializatition - - MACCR = (0x1c | (duplex << 1)); // auto CRC, late collision retry - STLCR = 0x3; // insert MAC source address - // into ethernet frame - BtBIPGGapTimerR = 0x14; // standard values - NonBtBIPGGapTimerR = ((0x9 << 7) | 0x11); // standard values - CollWinR = ((0x37 << 8) | 0xf); // standard values - SAFR = 0x1; // broadcast mode - EthGenCR = (0x40400400 | (duplex << 16)); // dma mode, full duplex, - // enable pNA mode(needed - // for alignment) - - cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA1, // Interrupt Vector - 0, // Interrupt Priority - (cyg_addrword_t)&netarm_sc, // Reference - // to Driver - // Instance - dma_rx_isr, - dma_rx_dsr, - &dma_rx_int_handle, - &dma_rx_int_object); - - cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA2, // Interrupt Vector - 0, // Interrupt Priority - (cyg_addrword_t)&netarm_sc, // Reference - // to Driver - // Instance - dma_tx_isr, - dma_tx_dsr, - &dma_tx_int_handle, - &dma_tx_int_object); - - cyg_drv_interrupt_attach(dma_rx_int_handle); - cyg_drv_interrupt_attach(dma_tx_int_handle); - - cyg_mutex_init(&Key_Mutex); - - sc->funs->eth_drv->init(sc, esa); - - return true; + + // setup dma receiver + setupDMA(); + + cyg_netarm_mii_reset(); + cyg_netarm_mii_negotiate(); // initialize PHY + duplex = cyg_netarm_mii_check_duplex(); + + // Ethernet Controller Initializatition + + // auto CRC, late collision retry + HAL_WRITE_UINT32(MACCR, 0x1c | (duplex << 1)); + // insert MAC source address into ethernet frame + HAL_WRITE_UINT32(STLCR, 0x3); + HAL_WRITE_UINT32(BtBIPGGapTimerR, 0x14); // standard values + HAL_WRITE_UINT32(NonBtBIPGGapTimerR, (0x9 << 7) | 0x11);// standard values + HAL_WRITE_UINT32(CollWinR, (0x37 << 8) | 0xf); // standard values + HAL_WRITE_UINT32(SAFR, 0x1); // broadcast mode + // dma mode, full duplex, enable pNA mode(needed for alignment) + HAL_WRITE_UINT32(EthGenCR, 0x40400400 | (duplex << 16)); + + cyg_drv_interrupt_create( + CYGNUM_HAL_INTERRUPT_DMA1, // Interrupt Vector + 0, // Interrupt Priority + (cyg_addrword_t)&netarm_sc, // Reference to Driver Instance + dma_rx_isr, + dma_rx_dsr, + &dma_rx_int_handle, + &dma_rx_int_object); + + cyg_drv_interrupt_create( + CYGNUM_HAL_INTERRUPT_DMA2, // Interrupt Vector + 0, // Interrupt Priority + (cyg_addrword_t)&netarm_sc, // Reference to Driver Instance + dma_tx_isr, + dma_tx_dsr, + &dma_tx_int_handle, + &dma_tx_int_object); + + cyg_drv_interrupt_attach(dma_rx_int_handle); + + cyg_drv_interrupt_attach(dma_tx_int_handle); + + cyg_mutex_init(&Key_Mutex); + + sc->funs->eth_drv->init(sc, esa); + + return true; } + static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) { - int i, len; - private_data_t *pd = (private_data_t *)(sc->driver_private); - unsigned char *data, *buf = pd->RxBuffer; - - for (i = 0; i < sg_len; i++) { - data = (unsigned char *)(sg_list[i].buf); - len = sg_list[i].len; - if (len) - { - if(i == 1) - { - buf += 2; - } - - fastcopy(data, buf, len); - buf += len; - } - } + int i, len; + private_data_t *pd = (private_data_t *)(sc->driver_private); + unsigned char *data, *buf = pd->RxBuffer; + + for (i = 0; i < sg_len; i++) { + data = (unsigned char *)(sg_list[i].buf); + len = sg_list[i].len; + if(len) + { + if(i == 1) + { + buf += 2; + } + + fastcopy(data, buf, len); + buf += len; + } + } } + static void netarm_deliver(struct eth_drv_sc *sc) { - static int a = 0, b = 0, c = 0; - unsigned long key; - private_data_t *pd = (private_data_t *)(sc->driver_private); - - while((key = GetKey(pd))) - { - sc->funs->eth_drv->tx_done(sc, key, 0); - } - - while(pRxBDP_A[a].hi & 0x8000) - { - pd->RxBuffer = (unsigned char *)(pRxBDP_A[a].lo & 0x1FFFFFFF); - HAL_REORDER_BARRIER(); - sc->funs->eth_drv->recv(sc, pRxBDP_A[a].hi & 0x7FFF); - HAL_REORDER_BARRIER(); - pRxBDP_A[a].hi = BufferSizeA; - HAL_REORDER_BARRIER(); - a = (a + 1) % NumA; - } - - while(pRxBDP_B[b].hi & 0x8000) - { - pd->RxBuffer = (unsigned char *)(pRxBDP_B[b].lo & 0x1FFFFFFF); - HAL_REORDER_BARRIER(); - sc->funs->eth_drv->recv(sc, pRxBDP_B[b].hi & 0x7FFF); - HAL_REORDER_BARRIER(); - pRxBDP_B[b].hi = BufferSizeB; - HAL_REORDER_BARRIER(); - b = (b + 1) % NumB; - } - - while(pRxBDP_C[c].hi & 0x8000) - { - pd->RxBuffer = (unsigned char *)(pRxBDP_C[c].lo & 0x1FFFFFFF); - HAL_REORDER_BARRIER(); - sc->funs->eth_drv->recv(sc, pRxBDP_C[c].hi & 0x7FFF); - HAL_REORDER_BARRIER(); - pRxBDP_C[c].hi = BufferSizeC; - HAL_REORDER_BARRIER(); - c = (c + 1) % NumC; - } - - if((DMA1A_SR & 0x20000000) || (DMA1B_SR & 0x20000000) || (DMA1C_SR & 0x20000000)) - { - EthGenCR &= ~0xc0000000; // reset Rx FIFO - EthGenCR |= 0xc0000000; - } - - DMA1A_SR = 0x20a00000; - DMA1B_SR = 0x20a00000; - DMA1C_SR = 0x20a00000; + static int a = 0, b = 0, c = 0; + unsigned key, rega, regb, regc; + private_data_t *pd = (private_data_t *)(sc->driver_private); + + + while((key = GetKey(pd))) + { + sc->funs->eth_drv->tx_done(sc, key, 0); + } + + while(pRxBDP_A[a].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_A[a].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_A[a].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_A[a].hi = BufferSizeA; + HAL_REORDER_BARRIER(); + a = (a + 1) % NumA; + } + + while(pRxBDP_B[b].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_B[b].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_B[b].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_B[b].hi = BufferSizeB; + HAL_REORDER_BARRIER(); + b = (b + 1) % NumB; + } + + while(pRxBDP_C[c].hi & 0x8000) + { + pd->RxBuffer = (unsigned char *)(pRxBDP_C[c].lo & 0x1FFFFFFF); + HAL_REORDER_BARRIER(); + sc->funs->eth_drv->recv(sc, pRxBDP_C[c].hi & 0x7FFF); + HAL_REORDER_BARRIER(); + pRxBDP_C[c].hi = BufferSizeC; + HAL_REORDER_BARRIER(); + c = (c + 1) % NumC; + } + + HAL_READ_UINT32(DMA1A_SR, rega); + HAL_READ_UINT32(DMA1B_SR, regb); + HAL_READ_UINT32(DMA1C_SR, regc); + + if((rega & 0x20000000) || (regb & 0x20000000) || (regc & 0x20000000)) + { + HAL_AND_UINT32(EthGenCR, ~0xc0000000); // reset Rx FIFO + HAL_OR_UINT32(EthGenCR, 0xc0000000); + } + + HAL_WRITE_UINT32(DMA1A_SR, 0x20a00000); + HAL_WRITE_UINT32(DMA1B_SR, 0x20a00000); + HAL_WRITE_UINT32(DMA1C_SR, 0x20a00000); } + static int netarm_can_send(struct eth_drv_sc *sc) { - private_data_t *pd = (private_data_t *)(sc->driver_private); - - if((pTxBDP[0].hi & 0x8000) || (pTxBDP[1].hi & 0x8000) || KeyBufferFull(pd)) - return 0; - - return 1; + private_data_t *pd = (private_data_t *)(sc->driver_private); + + if((pTxBDP->hi & 0x8000) || KeyBufferFull(pd)) + return 0; + + return 1; } static void netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, - int sg_len, int total_len, unsigned long key) + int sg_len, int total_len, unsigned long key) { - private_data_t *pd = (private_data_t *)(sc->driver_private); - int i, len; - unsigned char *data; - volatile char *buf = pTxBuffer; - - AddKey(key, pd); - - // Put data into buffer - for (i = 0; i < sg_len; i++) { - data = (unsigned char *)sg_list[i].buf; - len = sg_list[i].len; - - if(i == 0) - { - if((unsigned long)data & 0x3) - { - memcpy((unsigned char*)pTxHeader, data, 0xe); - } - else - { - fastcopy((unsigned char *)pTxHeader, data, 0xe); - } - - len -= 0xe; - data += 0xe; - } - - if (len) - { - fastcopy((unsigned char *)buf, data, len); - buf += len; - } - } - - cyg_drv_dsr_lock(); - pTxBDP[0].hi = 0x800e; - HAL_REORDER_BARRIER(); - pTxBDP[1].hi = (total_len - 0xe) | 0x8000; - HAL_REORDER_BARRIER(); - DMA2_SR |= 0xf0000000; - cyg_drv_dsr_unlock(); + private_data_t *pd = (private_data_t *)(sc->driver_private); + int i, len; + unsigned char *data, *buf = pTxBuffer; + + AddKey(key, pd); + + // Put data into buffer + for(i = 0; i < sg_len; i++) { + data = (unsigned char *)sg_list[i].buf; + len = sg_list[i].len; + + if(len) + { + if(((unsigned)buf & 0x3) != ((unsigned)data & 0x3)) + { + memcpy(buf, data, len); + } + else + { + fastcopy(buf, data, len); + } + + buf += len; + } + } + +cyg_drv_dsr_lock(); + pTxBDP->hi = total_len | 0x8000; +HAL_REORDER_BARRIER(); + HAL_OR_UINT32(DMA2_SR, 0xf0000000); +cyg_drv_dsr_unlock(); } + static void netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) { - SetMAC(enaddr); // set MAC address - HAL_REORDER_BARRIER(); - EthGenCR |= 0x80800000; // enable Rx und Tx FIFO - HAL_REORDER_BARRIER(); - cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA1); - cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA2); + setMAC(enaddr); // set MAC address +HAL_REORDER_BARRIER(); + HAL_OR_UINT32(EthGenCR, 0x80800000); // enable Rx und Tx FIFO +HAL_REORDER_BARRIER(); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA1); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_DMA2); } static void netarm_stop(struct eth_drv_sc *sc) { - EthGenCR &= 0x7f7fffff; - HAL_REORDER_BARRIER(); - cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA1); - cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA2); + HAL_AND_UINT32(EthGenCR, 0x7f7fffff); +HAL_REORDER_BARRIER(); + cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA1); + cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_DMA2); } static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, int len) { - switch (key) - { - case ETH_DRV_SET_MAC_ADDRESS: - return 0; - break; - case ETH_DRV_SET_MC_LIST: - case ETH_DRV_SET_MC_ALL: - return 0; - default: - return 1; - break; - } + return -1; } static void @@ -703,13 +698,13 @@ netarm_poll(struct eth_drv_sc *sc) static int netarm_int_vector(struct eth_drv_sc *sc) { - return CYGNUM_HAL_INTERRUPT_DMA1; + return CYGNUM_HAL_INTERRUPT_DMA1; } static void -SetMAC(unsigned char *esa) +setMAC(unsigned char *esa) { - SAR1 = (esa[1] << 8) | esa[0]; // set MAC address - SAR2 = (esa[3] << 8) | esa[2]; - SAR3 = (esa[5] << 8) | esa[4]; + HAL_WRITE_UINT32(SAR1, (esa[1] << 8) | esa[0]); // set MAC address + HAL_WRITE_UINT32(SAR2, (esa[3] << 8) | esa[2]); + HAL_WRITE_UINT32(SAR3, (esa[5] << 8) | esa[4]); }
--- a/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.h +++ b/packages/devs/eth/arm/netarm/current/src/netarm_eth_drv.h @@ -1,18 +1,19 @@ -#ifndef NETARM_ETH_DRV_H -#define NETARM_ETH_DRV_H +#ifndef CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H +#define CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H -//==================================================================== +// ==================================================================== // // netarm_eth_drv.h // // Device I/O - Description of NET+ARM ethernet hardware functions -// and data structures +// and data structures // // ==================================================================== + //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2005 eCosCentric LTD +// Copyright (C) 2005 eCosCentric Ltd. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -36,13 +37,15 @@ // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. +// +//####ECOSGPLCOPYRIGHTEND#### // ==================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at) // Contributors: Harald Brandl -// Date: 01.08.2004 -// Purpose: Internal interfaces and data structures +// Date: 01.08.2004 +// Purpose: Internal interfaces and data structures // Description: // //####DESCRIPTIONEND#### @@ -53,34 +56,31 @@ typedef struct { - unsigned char *RxBuffer; - unsigned short key_head, key_tail; - unsigned KeyBuffer[MaxKeys]; + unsigned char *RxBuffer; + unsigned short key_head, key_tail; + unsigned KeyBuffer[MaxKeys]; }private_data_t; typedef struct { - unsigned lo; - unsigned hi; + unsigned lo; + unsigned hi; }BDP_t; static bool netarm_init(struct cyg_netdevtab_entry *tab); -static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, - int sg_len); +static void netarm_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len); static void netarm_deliver(struct eth_drv_sc *sc); -static int netarm_can_send(struct eth_drv_sc *sc); -static void netarm_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, - int sg_len, int total_len, unsigned long key); +static int netarm_can_send(struct eth_drv_sc *sc); +static void netarm_send( + struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total_len, unsigned long key); static void netarm_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags); static void netarm_stop(struct eth_drv_sc *sc); -static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, - int len); +static int netarm_control(struct eth_drv_sc *sc, unsigned long key, void *data, int len); static void netarm_poll(struct eth_drv_sc *sc); -static int netarm_int_vector(struct eth_drv_sc *sc); +static int netarm_int_vector(struct eth_drv_sc *sc); -static void SetMAC(unsigned char *esa); +static void setMAC(unsigned char *esa); -#endif //NETARM__ETH_DRV_H - +#endif // CYGONCE_DEVS_ETH_ARM_NETARM_ETH_DR_H