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annotate packages/hal/arm/edb7xxx/current/src/edb7xxx_misc.c @ 66:bf00f99aec69 ecos-sw-2000-02-02

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Merge from eCos master repository on 2000-02-02-19:16:44-GMT
author jlarmour
date Wed, 02 Feb 2000 19:57:02 +0000
parents c38311975d4f
children 435cced73e2f
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1 //==========================================================================
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2 //
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3 // edb7xxx_misc.c
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4 //
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5 // HAL misc board support code for ARM EDB7XXX-1
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-02-20
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37 // Purpose: HAL board support
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38 // Description: Implementations of HAL board interfaces
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/system.h>
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46 #include CYGBLD_HAL_PLATFORM_H
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47
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48 #include <cyg/infra/cyg_type.h> // base types
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49 #include <cyg/infra/cyg_trac.h> // tracing macros
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50 #include <cyg/infra/cyg_ass.h> // assertion macros
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51
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52 #include <cyg/hal/hal_io.h> // IO macros
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53 #include <cyg/hal/hal_arch.h> // Register state info
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54 #include <cyg/hal/hal_diag.h>
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55 #include <cyg/hal/hal_intr.h> // Interrupt names
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56 #include <cyg/hal/hal_cache.h>
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57 #include <cyg/hal/hal_edb7xxx.h> // Hardware definitions
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58
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59 // #define CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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60 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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61 #include <cyg/hal/hal_intr.h> // HAL interrupt macros
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62 #include <cyg/hal/drv_api.h> // HAL ISR support
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63 static cyg_interrupt batlow_interrupt;
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64 static cyg_handle_t batlow_interrupt_handle;
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65 #endif
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66
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67 #if (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 18432)
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68 #define CPU_CLOCK 0
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69 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 36864)
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70 #define CPU_CLOCK 1
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71 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 49152)
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72 #define CPU_CLOCK 2
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73 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 73728)
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74 #define CPU_CLOCK 3
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75 #else
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76 #err Invalid CPU clock frequency
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77 #endif
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78
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79 static cyg_uint32 _period;
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80
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81 // Use Timer/Counter #2 for system clock
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82
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83 void hal_clock_initialize(cyg_uint32 period)
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84 {
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85 volatile cyg_uint32 *syscon1 = (volatile cyg_uint32 *)SYSCON1;
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86 volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D;
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87 // Set timer to 512KHz, prescale mode
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88 *syscon1 = (*syscon1 & ~(SYSCON1_TC2M|SYSCON1_TC2S)) | SYSCON1_TC2S | SYSCON1_TC2M;
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89 // Initialize counter
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90 *tc2d = period;
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91 _period = period;
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92 }
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93
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94 // This routine is called during a clock interrupt.
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95
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96 static void __inline__
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97 enable_FIQ(void)
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98 {
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99 asm volatile ("mrs r0,cpsr;"
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100 "bic r0,r0,#0x40;"
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101 "msr cpsr,r0");
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102 }
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103
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104 #ifdef CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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105 #define DRAM_START 0x00000000
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106 #define DRAM_END 0x01000000
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107 #define DRAM_ROW_SIZE 0x00000400
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108 #define DRAM_REFRESH (((DRAM_END-DRAM_START)/DRAM_ROW_SIZE)+99)/100
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109
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110 static void
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111 do_DRAM_refresh(void)
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112 {
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113 static cyg_uint32 *row_ptr;
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114 volatile cyg_uint32 val;
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115 int i;
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116 for (i = 0; i < DRAM_REFRESH; i++) {
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117 val = *row_ptr;
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118 row_ptr += DRAM_ROW_SIZE / sizeof(*row_ptr);
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119 if (row_ptr >= (cyg_uint32 *)DRAM_END) row_ptr = (cyg_uint32 *)DRAM_START;
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120 }
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121 }
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122 #endif // CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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123
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124 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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125 {
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126 volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D;
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127 if (period != _period) {
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128 *tc2d = period;
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129 _period = period;
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130 }
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131 enable_FIQ(); // Should be safe here
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132 #ifdef CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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133 do_DRAM_refresh();
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134 #else
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135 // Temporary fix for DRAM starvation problem
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136 if (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK > 37000) {
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137 int i;
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138 for (i = 0; i < (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK*2)/24; i++) ; // approx 300 us
54
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139 }
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140 #endif
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141 }
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142
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143 // Read the current value of the clock, returning the number of hardware "ticks"
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144 // that have occurred (i.e. how far away the current value is from the start)
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145
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146 void hal_clock_read(cyg_uint32 *pvalue)
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147 {
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148 volatile cyg_int32 *tc2d = (volatile cyg_int32 *)TC2D;
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149 static cyg_int32 clock_val;
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150 clock_val = *tc2d & 0x0000FFFF; // Register has only 16 bits
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151 if (clock_val & 0x00008000) clock_val |= 0xFFFF8000; // Extend sign bit
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152 *pvalue = (cyg_uint32)(_period - clock_val); // 'clock_val' counts down and wraps
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153 }
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154
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155 // These tables map the various [soft] interrupt numbers onto the hardware
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156
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157 static cyg_uint32 hal_interrupt_bitmap[] = {
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158 0, // CYGNUM_HAL_INTERRUPT_unused 0
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159 INTSR1_EXTFIQ, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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160 INTSR1_BLINT, // CYGNUM_HAL_INTERRUPT_BLINT 2
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161 INTSR1_WEINT, // CYGNUM_HAL_INTERRUPT_WEINT 3
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162 INTSR1_MCINT, // CYGNUM_HAL_INTERRUPT_MCINT 4
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163 INTSR1_CSINT, // CYGNUM_HAL_INTERRUPT_CSINT 5
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164 INTSR1_EINT1, // CYGNUM_HAL_INTERRUPT_EINT1 6
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165 INTSR1_EINT2, // CYGNUM_HAL_INTERRUPT_EINT2 7
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166 INTSR1_EINT3, // CYGNUM_HAL_INTERRUPT_EINT3 8
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167 INTSR1_TC1OI, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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168 INTSR1_TC2OI, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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169 INTSR1_RTCMI, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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170 INTSR1_TINT, // CYGNUM_HAL_INTERRUPT_TINT 12
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171 INTSR1_UTXINT1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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172 INTSR1_URXINT1, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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173 INTSR1_UMSINT, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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174 INTSR1_SSEOTI, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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175 INTSR2_KBDINT, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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176 INTSR2_SS2RX, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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177 INTSR2_SS2TX, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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178 INTSR2_UTXINT2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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179 INTSR2_URXINT2, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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180 #if defined(__EDB7211)
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181 INTSR3_MCPINT // CYGNUM_HAL_INTERRUPT_MCPINT 22
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182 #endif
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183 };
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184
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185 static cyg_uint32 hal_interrupt_mask_regmap[] = {
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186 0, // CYGNUM_HAL_INTERRUPT_unused 0
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187 INTMR1, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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188 INTMR1, // CYGNUM_HAL_INTERRUPT_BLINT 2
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189 INTMR1, // CYGNUM_HAL_INTERRUPT_WEINT 3
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190 INTMR1, // CYGNUM_HAL_INTERRUPT_MCINT 4
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191 INTMR1, // CYGNUM_HAL_INTERRUPT_CSINT 5
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192 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT1 6
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193 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT2 7
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194 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT3 8
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195 INTMR1, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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196 INTMR1, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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197 INTMR1, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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198 INTMR1, // CYGNUM_HAL_INTERRUPT_TINT 12
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199 INTMR1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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200 INTMR1, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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201 INTMR1, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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202 INTMR1, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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203 INTMR2, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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204 INTMR2, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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205 INTMR2, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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206 INTMR2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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207 INTMR2, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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208 #if defined(__EDB7211)
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209 INTMR3, // CYGNUM_HAL_INTERRUPT_MCPINT 22
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210 #endif
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211 };
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212
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213 static cyg_uint32 hal_interrupt_clear_map[] = {
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214 0, // CYGNUM_HAL_INTERRUPT_unused 0
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215 0, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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216 BLEOI, // CYGNUM_HAL_INTERRUPT_BLINT 2
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217 TEOI, // CYGNUM_HAL_INTERRUPT_WEINT 3
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218 MCEOI, // CYGNUM_HAL_INTERRUPT_MCINT 4
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219 COEOI, // CYGNUM_HAL_INTERRUPT_CSINT 5
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220 0, // CYGNUM_HAL_INTERRUPT_EINT1 6
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221 0, // CYGNUM_HAL_INTERRUPT_EINT2 7
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222 0, // CYGNUM_HAL_INTERRUPT_EINT3 8
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223 TC1EOI, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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224 TC2EOI, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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225 RTCEOI, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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226 TEOI, // CYGNUM_HAL_INTERRUPT_TINT 12
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227 0, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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228 0, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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229 UMSEOI, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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230 0, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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231 KBDEOI, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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232 0, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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233 0, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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234 0, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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235 0, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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236 #if defined(__EDB7211)
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237 0, // CYGNUM_HAL_INTERRUPT_MCPINT 22
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238 #endif
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239 };
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240
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241 static struct regmap {
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242 int first_int, last_int;
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243 cyg_uint32 stat_reg, mask_reg;
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244 } hal_interrupt_status_regmap[] = {
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245 { CYGNUM_HAL_INTERRUPT_EXTFIQ, CYGNUM_HAL_INTERRUPT_SSEOTI, INTSR1, INTMR1},
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246 { CYGNUM_HAL_INTERRUPT_KBDINT, CYGNUM_HAL_INTERRUPT_URXINT2, INTSR2, INTMR2},
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247 #if defined(__EDB7211)
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248 { CYGNUM_HAL_INTERRUPT_MCPINT, CYGNUM_HAL_INTERRUPT_MCPINT, INTSR3, INTMR3},
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249 #endif
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250 { 0, 0, 0}
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251 };
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252
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253 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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254 // This ISR is called when the battery low interrupt occurs
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255 int
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256 cyg_hal_batlow_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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257 {
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258 diag_printf("Battery low\n");
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259 cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_BLINT);
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260 // Presumably, one would leave this masked until the battery changed
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261 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_BLINT);
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262 return 0; // No need to run DSR
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263 }
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264 #endif
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265
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266 //
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267 // Early stage hardware initialization
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268 // Some initialization has already been done before we get here. For now
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269 // just set up the interrupt environment.
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270
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271 void hal_hardware_init(void)
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272 {
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273 volatile cyg_uint32 *icr;
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274 int vector;
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275 // Clear and initialize instruction cache
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276 HAL_ICACHE_INVALIDATE_ALL();
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277 HAL_ICACHE_ENABLE();
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278 // Any hardware/platform initialization that needs to be done.
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279 *(volatile cyg_uint32 *)INTMR1 = 0;
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280 *(volatile cyg_uint32 *)INTMR2 = 0;
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281 #if !defined(__CL7111)
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282 *(volatile cyg_uint32 *)INTMR3 = 0;
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283 *(volatile cyg_uint8 *)SYSCON3 = SYSCON3_CLKCTL(CPU_CLOCK);
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284 #endif
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285 #if 0
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286 diag_printf("IMR1: %04x, IMR2: %04x\n",
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287 *(volatile cyg_uint32 *)INTMR1,
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288 *(volatile cyg_uint32 *)INTMR2);
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289 diag_printf("Memcfg1: %08x, Memcfg2: %08x, DRAM refresh: %08x\n",
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290 *(volatile cyg_uint32 *)MEMCFG1,
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291 *(volatile cyg_uint32 *)MEMCFG2,
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292 *(volatile cyg_uint8 *)DRFPR);
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293 #endif
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294 // Reset all interrupt masks (disable all interrupt sources)
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295 for (vector = CYGNUM_HAL_ISR_MIN; vector < CYGNUM_HAL_ISR_COUNT; vector++) {
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296 icr = (volatile cyg_uint32 *)hal_interrupt_clear_map[vector];
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297 if (icr) *icr = 0; // Just a write clears the latch
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298 }
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299 // Turn on the DIAG LED to let the world know the board is alive
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300 *(volatile unsigned char *)LEDFLSH = LEDFLSH_ENABLE|LEDFLSH_DUTY(16)|LEDFLSH_PERIOD(1);
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301 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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302 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_BLINT,
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303 99, // Priority - what goes here?
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304 0, // Data item passed to interrupt handler
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305 cyg_hal_batlow_isr,
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306 0,
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307 &batlow_interrupt_handle,
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308 &batlow_interrupt);
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309 cyg_drv_interrupt_attach(batlow_interrupt_handle);
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310 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_BLINT);
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311 #endif
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312 }
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313
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314 //
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315 // This routine is called to respond to a hardware interrupt (IRQ). It
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316 // should interrogate the hardware and return the IRQ vector number.
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317
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318 // This code is a little convoluted to keep it general while still avoiding
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319 // reading the hardware a lot, since the interrupt status is split across
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320 // three separate registers.
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321
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322 int hal_spurious_ints;
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323
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324 int hal_IRQ_handler(void)
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325 {
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326 struct regmap *map = hal_interrupt_status_regmap;
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327 cyg_uint32 stat;
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328 int vector;
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329 while (map->first_int) {
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330 stat = *(volatile cyg_uint32 *)map->stat_reg & *(volatile cyg_uint32 *)map->mask_reg;
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331 for (vector = map->first_int; vector <= map->last_int; vector++) {
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332 if (stat & hal_interrupt_bitmap[vector]) return vector;
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333 }
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334 map++; // Next interrupt status register
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335 }
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336 hal_spurious_ints++;
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337 return CYGNUM_HAL_INTERRUPT_unused; // This shouldn't happen!
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338 }
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339
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340 //
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341 // Interrupt control
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342 //
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343
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344 void hal_interrupt_mask(int vector)
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345 {
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346 volatile cyg_uint32 *imr;
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347 imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector];
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348 *imr &= ~hal_interrupt_bitmap[vector];
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349 }
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350
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351 void hal_interrupt_unmask(int vector)
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352 {
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353 volatile cyg_uint32 *imr;
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354 imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector];
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355 *imr |= hal_interrupt_bitmap[vector];
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356 }
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357
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358 void hal_interrupt_acknowledge(int vector)
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359 {
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360 // Some interrupt sources have a register for this.
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361 volatile cyg_uint8 *icr;
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362 icr = (volatile cyg_uint8 *)hal_interrupt_clear_map[vector];
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363 if (icr) {
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364 *icr = 0; // Any data clears interrupt
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365 }
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366 }
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367
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368 void hal_interrupt_configure(int vector, int level, int up)
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369 {
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370 // No interrupts are configurable on this hardware
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371 }
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372
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373 void hal_interrupt_set_level(int vector, int level)
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374 {
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375 // No interrupts are configurable on this hardware
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376 }
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377
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378 /*------------------------------------------------------------------------*/
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379 // EOF hal_misc.c