Mercurial > ecos-v3_0-branch
annotate packages/hal/arm/arch/current/src/vectors.S @ 16:4f2df4ab82c8 ecos-sw-1999-06-18
Merge from eCos master repository on 1999-06-18-15:25:04-BST
| author | jlarmour |
|---|---|
| date | Fri, 18 Jun 1999 07:59:09 +0000 |
| parents | 01ce82f3e11a |
| children | 5f5102441818 |
| rev | line source |
|---|---|
| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 // ####COPYRIGHTEND#### | |
| 29 // #======================================================================== | |
| 30 // ######DESCRIPTIONBEGIN#### | |
| 31 // # | |
| 32 // # Author(s): nickg, gthomas | |
| 33 // # Contributors: nickg, gthomas | |
| 34 // # Date: 1999-02-20 | |
| 35 // # Purpose: ARM exception vectors | |
| 36 // # Description: This file defines the code placed into the exception | |
| 37 // # vectors. It also contains the first level default VSRs | |
| 38 // # that save and restore state for both exceptions and | |
| 39 // # interrupts. | |
| 40 // # | |
| 41 // #####DESCRIPTIONEND#### | |
| 42 // # | |
| 43 // #======================================================================== | |
| 44 | |
| 45 #include <pkgconf/hal.h> | |
| 46 #include <pkgconf/hal_arm.h> | |
| 47 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 48 #include <pkgconf/kernel.h> | |
| 49 #else | |
| 50 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
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51 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 52 #endif |
| 53 #include <cyg/hal/hal_platform_setup.h> | |
| 54 | |
| 55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 56 // The CDL should enforce this | |
| 57 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 58 #endif | |
| 59 | |
| 60 #include "arm.inc" | |
| 61 | |
| 62 #define FUNC_START(name) \ | |
| 63 .globl _name; \ | |
| 64 _name: | |
| 65 | |
| 66 #define PTR(name) \ | |
| 67 .##name: .word name | |
| 68 | |
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69 #ifdef CYGHWR_HAL_ARM_HAS_MMU |
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70 #define UNMAPPED(x) ((x)-__exception_handlers) |
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71 #else |
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72 #define UNMAPPED(x) (x) |
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73 #endif |
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74 |
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75 #define UNMAPPED_PTR(name) \ |
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76 .##name: .word UNMAPPED(name) |
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77 |
| 2 | 78 |
| 79 .file "vectors.S" | |
| 80 | |
| 81 | |
| 82 //========================================================================== | |
| 83 // Hardware exception vectors. | |
| 84 // This entire section will be copied to location 0x0000 at startup time. | |
| 85 // | |
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86 .code 32 |
| 2 | 87 .section ".vectors","ax" |
| 88 .global __exception_handlers | |
| 89 __exception_handlers: | |
| 90 ldr pc,.reset_vector // 0x00 | |
| 91 ldr pc,.undefined_instruction // 0x04 | |
| 92 ldr pc,.software_interrupt // 0x08 start && software int | |
| 93 ldr pc,.abort_prefetch // 0x0C | |
| 94 ldr pc,.abort_data // 0x10 | |
| 95 .word 0 // unused | |
| 96 ldr pc,.IRQ // 0x18 | |
| 97 ldr pc,.FIQ // 0x1C | |
| 98 | |
| 99 // The layout of these pointers should match the vector table above since | |
| 100 // they are copied in pairs. | |
| 101 .global vectors | |
| 102 vectors: | |
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103 UNMAPPED_PTR(reset_vector) |
| 2 | 104 PTR(undefined_instruction) |
| 105 PTR(software_interrupt) | |
| 106 PTR(abort_prefetch) | |
| 107 PTR(abort_data) | |
| 108 .word 0 | |
| 109 PTR(IRQ) | |
| 110 PTR(FIQ) | |
| 111 PTR(start) | |
| 112 | |
| 113 .text | |
| 114 // Startup code which will get the machine into supervisor mode | |
| 115 .global reset_vector | |
| 116 .type reset_vector,function | |
| 117 reset_vector: | |
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118 |
| 2 | 119 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 120 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 121 mrs r7,cpsr // move back to IRQ mode | |
| 122 and r7,r7,#CPSR_MODE_BITS | |
| 123 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 124 beq start | |
| 125 #endif | |
| 126 | |
| 127 PLATFORM_SETUP1 // Early stage platform initialization | |
| 128 // see <cyg/hal/hal_platform_setup.h> | |
| 129 | |
| 130 mov r0,#0 // move vectors | |
| 131 ldr r1,.__exception_handlers | |
| 132 ldr r2,[r1,#0x04] // undefined instruction | |
| 133 str r2,[r0,#0x04] | |
| 134 ldr r2,[r1,#0x24] | |
| 135 str r2,[r0,#0x24] | |
| 136 ldr r2,[r1,#0x08] // software interrupt | |
| 137 str r2,[r0,#0x08] | |
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138 #if defined(CYG_HAL_STARTUP_RAM) |
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139 // Ugly hack to get into supervisor mode |
| 2 | 140 ldr r2,[r1,#0x40] |
| 141 str r2,[r0,#0x28] | |
| 142 swi // switch to supervisor mode | |
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143 #endif |
| 2 | 144 |
| 145 // ========================================================================= | |
| 146 // Real startup code. We jump here from the reset vector to set up the world. | |
| 147 .globl start | |
| 148 start: | |
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149 |
| 2 | 150 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 151 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 152 // If we get restarted, hang here to avoid corrupting memory | |
| 153 ldr r0,.init_flag | |
| 154 ldr r1,[r0] | |
| 155 1: cmp r1,#0 | |
| 156 bne 1b | |
| 157 ldr r1,init_done | |
| 158 str r1,[r0] | |
| 159 #endif | |
| 160 | |
| 161 // Reset software interrupt pointer | |
| 162 mov r0,#0 // move vectors | |
| 163 ldr r1,.__exception_handlers | |
| 164 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 165 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 166 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 167 beq 10f | |
| 168 #endif | |
| 169 ldr r2,[r1,#0x28] // software interrupt | |
| 170 str r2,[r0,#0x28] | |
| 171 10: | |
| 172 ldr r2,[r1,#0x18] // IRQ | |
| 173 str r2,[r0,#0x18] | |
| 174 ldr r2,[r1,#0x38] | |
| 175 str r2,[r0,#0x38] | |
| 176 ldr r2,[r1,#0x1C] // FIQ | |
| 177 str r2,[r0,#0x1C] | |
| 178 ldr r2,[r1,#0x3C] | |
| 179 str r2,[r0,#0x3C] | |
| 180 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 181 str r2,[r0,#0x0C] | |
| 182 ldr r2,[r1,#0x2C] | |
| 183 str r2,[r0,#0x2C] | |
| 184 ldr r2,[r1,#0x10] // abort (data) | |
| 185 str r2,[r0,#0x10] | |
| 186 ldr r2,[r1,#0x30] | |
| 187 str r2,[r0,#0x30] | |
| 188 | |
| 189 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) | |
| 190 // Relocate [copy] data from ROM to RAM | |
| 191 ldr r3,.__rom_data_start | |
| 192 ldr r4,.__ram_data_start | |
| 193 ldr r5,.__ram_data_end | |
| 194 cmp r4,r5 // jump if no data to move | |
| 195 beq 2f | |
| 196 sub r3,r3,#4 // loop adjustments | |
| 197 sub r4,r4,#4 | |
| 198 1: ldr r0,[r3,#4]! // copy info | |
| 199 str r0,[r4,#4]! | |
| 200 cmp r4,r5 | |
| 201 bne 1b | |
| 202 2: | |
| 203 #endif | |
| 204 | |
| 205 // initialize interrupt/exception environments | |
| 206 ldr sp,.__startup_stack | |
| 207 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 208 msr cpsr,r0 | |
| 209 ldr sp,.__exception_stack | |
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210 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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211 msr cpsr,r0 |
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212 ldr sp,.__exception_stack |
| 2 | 213 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 214 msr cpsr,r0 | |
| 215 ldr sp,.__exception_stack | |
| 216 | |
| 217 // initialize CPSR (machine state register) | |
| 218 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 219 msr cpsr,r0 | |
| 220 | |
| 221 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 222 msr spsr,r0 | |
| 223 | |
| 224 // initialize stack | |
| 225 ldr sp,.__startup_stack | |
| 226 | |
| 227 // clear BSS | |
| 228 ldr r1,.__bss_start | |
| 229 ldr r2,.__bss_end | |
| 230 mov r0,#0 | |
| 231 cmp r1,r2 | |
| 232 beq 2f | |
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233 1: str r0,[r1],#4 |
| 2 | 234 cmp r1,r2 |
| 235 bne 1b | |
| 236 2: | |
| 237 | |
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238 |
| 2 | 239 // Call platform specific hardware initialization |
| 240 bl hal_hardware_init | |
| 241 | |
| 242 // Run through static constructors | |
| 243 bl cyg_hal_invoke_constructors | |
| 244 | |
| 245 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 246 bl initialize_stub | |
| 247 #endif | |
| 248 | |
| 249 // This starts up the eCos kernel | |
| 250 bl cyg_start | |
| 251 _start_hang: | |
| 252 b _start_hang | |
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253 .code 32 |
| 2 | 254 |
| 255 init_done: | |
| 256 .long 0xDEADB00B | |
| 257 | |
| 258 // | |
| 259 // Exception handlers | |
| 260 // Assmumption: get here from a Supervisor context [mode] | |
| 261 // | |
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262 .code 32 |
| 2 | 263 undefined_instruction: |
| 264 ldr sp,.__undef_exception_stack // get good stack | |
| 265 sub lr,lr,#4 // PC at time of interrupt | |
| 266 stmfd sp!,{r0,fp,ip,lr} | |
| 267 mrs r0,spsr | |
| 268 stmfd sp!,{r0} | |
| 269 mov ip,sp // save SP which will vanish with | |
| 270 // mode switch | |
| 271 mrs r0,cpsr // switch to Supervisor Mode | |
| 272 bic r0,r0,#CPSR_MODE_BITS | |
| 273 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 274 msr cpsr,r0 // sp,lr are now old values | |
| 275 mov fp,sp | |
| 276 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 277 ldr sp,.__GDB_stack | |
| 278 cmp fp,sp // already on GDB stack? | |
| 279 bhi 10f | |
| 280 ldr r0,.__GDB_stack_base | |
| 281 cmp fp,r0 | |
| 282 bls 10f // no - switch to GDB stack | |
| 283 // (already in sp) | |
| 284 mov sp,fp // yes - no switch | |
| 285 10: | |
| 286 #endif | |
| 287 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 288 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 289 ldmfd ip,{r0-r4} // saved registers | |
| 290 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 291 str r1,[sp,#armreg_r0] // saved R0 | |
| 292 str r2,[sp,#armreg_fp] // saved FP | |
| 293 str r3,[sp,#armreg_ip] // saved IP | |
| 294 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 295 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 296 add r0,ip,#ARMREG_SIZE | |
| 297 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 298 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 299 mov r0,sp | |
| 300 bl undefined_instruction | |
| 301 #endif | |
| 302 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 303 b call_exception_handler | |
| 304 | |
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305 .code 32 |
| 2 | 306 software_interrupt: |
| 307 ldr sp,.__startup_stack // get good stack | |
| 308 sub lr,lr,#4 // PC at time of interrupt | |
| 309 stmfd sp!,{r0,ip,lr} | |
| 310 mrs r0,spsr | |
| 311 stmfd sp!,{r0} | |
| 312 mov ip,sp // save SP which will vanish with | |
| 313 // mode switch | |
| 314 mrs r0,cpsr // switch to Supervisor Mode | |
| 315 bic r0,r0,#CPSR_MODE_BITS | |
| 316 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 317 msr cpsr,r0 // sp,lr are now old values | |
| 318 mov ip,sp | |
| 319 ldr sp,.__startup_stack // get good stack | |
| 320 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 321 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 322 ldmfd ip,{r0-r3} // saved registers | |
| 323 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 324 str r1,[sp,#armreg_r0] // saved R0 | |
| 325 str r2,[sp,#armreg_ip] // saved IP | |
| 326 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 327 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 328 add r0,ip,#ARMREG_SIZE | |
| 329 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 330 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 331 mov r0,sp | |
| 332 bl software_interrupt | |
| 333 #endif | |
| 334 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 335 b call_exception_handler | |
| 336 | |
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337 .code 32 |
| 2 | 338 abort_prefetch: |
| 339 ldr sp,.__undef_exception_stack // get good stack | |
| 340 sub lr,lr,#4 // PC at time of interrupt | |
| 341 stmfd sp!,{r0,fp,ip,lr} | |
| 342 mrs r0,spsr | |
| 343 stmfd sp!,{r0} | |
| 344 mov ip,sp // save SP which will vanish with | |
| 345 // mode switch | |
| 346 mrs r0,cpsr // switch to Supervisor Mode | |
| 347 bic r0,r0,#CPSR_MODE_BITS | |
| 348 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 349 msr cpsr,r0 // sp,lr are now old values | |
| 350 mov fp,sp | |
| 351 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 352 ldr sp,.__GDB_stack | |
| 353 cmp fp,sp // already on GDB stack? | |
| 354 bhi 10f | |
| 355 ldr r0,.__GDB_stack_base | |
| 356 cmp fp,r0 | |
| 357 bls 10f // no - switch to GDB stack | |
| 358 // (already in sp) | |
| 359 mov sp,fp // yes - no switch | |
| 360 10: | |
| 361 #endif | |
| 362 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 363 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 364 ldmfd ip,{r0-r4} // saved registers | |
| 365 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 366 str r1,[sp,#armreg_r0] // saved R0 | |
| 367 str r2,[sp,#armreg_fp] // saved FP | |
| 368 str r3,[sp,#armreg_ip] // saved IP | |
| 369 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 370 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 371 add r0,ip,#ARMREG_SIZE | |
| 372 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 373 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 374 mov r0,sp | |
| 375 bl abort_prefetch | |
| 376 #endif | |
| 377 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 378 b call_exception_handler | |
| 379 | |
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380 .code 32 |
| 2 | 381 abort_data: |
| 382 ldr sp,.__undef_exception_stack // get good stack | |
| 383 sub lr,lr,#4 // PC at time of interrupt | |
| 384 stmfd sp!,{r0,fp,ip,lr} | |
| 385 mrs r0,spsr | |
| 386 stmfd sp!,{r0} | |
| 387 mov ip,sp // save SP which will vanish with | |
| 388 // mode switch | |
| 389 mrs r0,cpsr // switch to Supervisor Mode | |
| 390 bic r0,r0,#CPSR_MODE_BITS | |
| 391 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 392 msr cpsr,r0 // sp,lr are now old values | |
| 393 mov fp,sp | |
| 394 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 395 ldr sp,.__GDB_stack | |
| 396 cmp fp,sp // already on GDB stack? | |
| 397 bhi 10f | |
| 398 ldr r0,.__GDB_stack_base | |
| 399 cmp fp,r0 | |
| 400 bls 10f // no - switch to GDB stack | |
| 401 // (already in sp) | |
| 402 mov sp,fp // yes - no switch | |
| 403 10: | |
| 404 #endif | |
| 405 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 406 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 407 ldmfd ip,{r0-r4} // saved registers | |
| 408 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 409 str r1,[sp,#armreg_r0] // saved R0 | |
| 410 str r2,[sp,#armreg_fp] // saved FP | |
| 411 str r3,[sp,#armreg_ip] // saved IP | |
| 412 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 413 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 414 add r0,ip,#ARMREG_SIZE | |
| 415 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 416 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 417 mov r0,sp | |
| 418 bl abort_data | |
| 419 #endif | |
| 420 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 421 b call_exception_handler | |
| 422 | |
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423 .code 32 |
| 2 | 424 FIQ: |
| 425 ldr sp,.__startup_stack // get good stack | |
| 426 sub lr,lr,#4 // PC at time of interrupt | |
| 427 stmfd sp!,{r0,ip,lr} | |
| 428 mrs r0,spsr | |
| 429 stmfd sp!,{r0} | |
| 430 mov ip,sp // save SP which will vanish with | |
| 431 // mode switch | |
| 432 mrs r0,cpsr // switch to Supervisor Mode | |
| 433 bic r0,r0,#CPSR_MODE_BITS | |
| 434 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 435 msr cpsr,r0 // sp,lr are now old values | |
| 436 mov ip,sp | |
| 437 ldr sp,.__startup_stack // get good stack | |
| 438 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 439 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 440 ldmfd ip,{r0-r3} // saved registers | |
| 441 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 442 str r1,[sp,#armreg_r0] // saved R0 | |
| 443 str r2,[sp,#armreg_ip] // saved IP | |
| 444 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 445 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 446 add r0,ip,#ARMREG_SIZE | |
| 447 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 448 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 449 mov r0,sp | |
| 450 bl FIQ | |
| 451 #endif | |
| 452 mov v1,#CYGNUM_HAL_EXCEPTION_FIQ | |
| 453 b call_exception_handler | |
| 454 | |
| 455 // | |
| 456 // Dispatch an exception handler. | |
| 457 | |
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458 .code 32 |
| 2 | 459 call_exception_handler: |
| 460 str v1,[sp,#armreg_vector] | |
| 461 mov r0,sp | |
| 462 bl exception_handler | |
| 463 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 464 mov r0,sp | |
| 465 bl exception_handler_returned | |
| 466 #endif | |
| 467 | |
| 468 // Restore [interrupted] context | |
| 469 mov ip,sp // get stack pointer | |
| 470 | |
| 471 ldr lr,[ip,#armreg_lr] | |
| 472 ldr sp,[sp,#armreg_sp] | |
| 473 | |
| 474 mrs r0,cpsr // move back to IRQ mode | |
| 475 bic r0,r0,#CPSR_MODE_BITS | |
| 476 orr r0,r0,#CPSR_IRQ_MODE | |
| 477 msr cpsr,r0 | |
| 478 | |
| 479 mov sp,ip | |
| 480 ldr lr,[sp,#armreg_pc] | |
| 481 ldr r0,[sp,#armreg_cpsr] | |
| 482 ldr ip,[sp,#armreg_ip] | |
| 483 msr spsr,r0 | |
| 484 ldmfd sp,{r0-r10,fp} | |
| 485 | |
| 486 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 487 | |
| 488 // Handle device interrupts | |
| 489 // This is slightly more complicated than the other exception handlers because | |
| 490 // it needs to interface with the kernel (if present). | |
| 491 | |
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492 .code 32 |
| 2 | 493 IRQ: |
| 494 // Note: I use this exception stack while saving the context because | |
| 495 // the current SP does not seem to be always valid in this CPU mode. | |
| 496 ldr sp,.__exception_stack // get good stack | |
| 497 sub lr,lr,#4 // PC at time of interrupt | |
| 498 stmfd sp!,{r0,fp,ip,lr} | |
| 499 mrs r0,spsr | |
| 500 stmfd sp!,{r0} | |
| 501 mov ip,sp // save SP which will vanish with | |
| 502 // mode switch | |
| 503 mrs r0,cpsr // switch to Supervisor Mode | |
| 504 bic r0,r0,#CPSR_MODE_BITS | |
| 505 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 506 msr cpsr,r0 // sp,lr are now old values | |
| 507 mov fp,sp // save old SP | |
| 508 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 509 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 510 ldmfd ip,{r0-r4} // saved registers | |
| 511 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 512 str r1,[sp,#armreg_r0] // saved R0 | |
| 513 str r2,[sp,#armreg_fp] // saved FP | |
| 514 str r3,[sp,#armreg_ip] // saved IP | |
| 515 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 516 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 517 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 518 mov v6,sp // Save pointer to register frame | |
| 519 | |
| 520 // mov r0,sp | |
| 521 // bl _show_frame_in | |
| 522 | |
| 523 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 524 // Switch to interrupt stack | |
| 525 ldr r2,.irq_level // current number of nested interrupts | |
| 526 ldr r0,[r2] | |
| 527 add r1,r0,#1 | |
| 528 str r1,[r2] // if was zero, switch stacks | |
| 529 cmp r0,#0 | |
| 530 moveq r1,sp // save old stack pointer | |
| 531 ldreq sp,.__interrupt_stack | |
| 532 stmeqfd sp!,{r1} | |
| 533 10: | |
| 534 #endif | |
| 535 | |
| 536 // The entire CPU state is now stashed on the stack, | |
| 537 // increment the scheduler lock and handle the interrupt | |
| 538 | |
| 539 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 540 .extern cyg_scheduler_sched_lock | |
| 541 ldr r3,.cyg_scheduler_sched_lock | |
| 542 ldr r4,[r3] | |
| 543 add r4,r4,#1 | |
| 544 str r4,[r3] | |
| 545 #endif | |
| 546 | |
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547 // TEMP |
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548 mov r0,v6 |
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549 // TEMP |
| 2 | 550 bl hal_IRQ_handler // determine interrupt source |
| 551 mov v1,r0 // returned vector # | |
| 552 | |
| 553 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 554 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 555 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 556 mov r1,v1 // arg1 = vector | |
| 557 mov r2,#0 // arg2 = 0 | |
| 558 bl cyg_instrument // call instrument function | |
| 559 #endif | |
| 560 | |
| 561 mov r0,v1 // vector # | |
| 562 ldr r1,.hal_interrupt_data | |
| 563 ldr r1,[r1,v1,lsl #2] // handler data | |
| 564 ldr r2,.hal_interrupt_handlers | |
| 565 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
| 566 mov r2,v6 // register frame | |
| 567 | |
| 568 mov lr,pc // invoke handler (call indirect | |
| 569 mov pc,v3 // thru v3) | |
| 570 | |
| 571 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 572 // If we are returning from the last nested interrupt, move back | |
| 573 // to the thread stack. interrupt_end() must be called on the | |
| 574 // thread stack since it potentially causes a context switch. | |
| 575 ldr r2,.irq_level | |
| 576 ldr r3,[r2] | |
| 577 subs r1,r3,#1 | |
| 578 str r1,[r2] | |
| 579 ldreq sp,[sp] // This should be the saved stack pointer | |
| 580 #endif | |
| 581 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 582 // The return value from the handler (in r0) will indicate whether a | |
| 583 // DSR is to be posted. Pass this together with a pointer to the | |
| 584 // interrupt object we have just used to the interrupt tidy up routine. | |
| 585 | |
| 586 ldr r1,.hal_interrupt_objects | |
| 587 ldr r1,[r1,v1,lsl #2] | |
| 588 bl interrupt_end // post any bottom layer handler | |
| 589 // threads and call scheduler | |
| 590 #endif | |
| 591 | |
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592 |
| 2 | 593 // mov r0,sp |
| 594 // bl show_frame_out | |
| 595 | |
| 596 mov ip,sp // get stack pointer | |
| 597 | |
| 598 ldr lr,[ip,#armreg_lr] | |
| 599 ldr sp,[sp,#armreg_sp] | |
| 600 | |
| 601 mrs r0,cpsr // move back to IRQ mode | |
| 602 bic r0,r0,#CPSR_MODE_BITS | |
| 603 orr r0,r0,#CPSR_IRQ_MODE | |
| 604 msr cpsr,r0 | |
| 605 | |
| 606 mov sp,ip | |
| 607 ldr lr,[sp,#armreg_pc] | |
| 608 ldr r0,[sp,#armreg_cpsr] | |
| 609 ldr ip,[sp,#armreg_ip] | |
| 610 msr spsr,r0 | |
| 611 ldmfd sp,{r0-r10,fp} | |
| 612 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 613 | |
| 614 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 615 // Execute pending DSRs the interrupt stack | |
| 616 // Note: this can only be called from code running on a thread stack | |
| 617 .global hal_interrupt_stack_call_pending_DSRs | |
| 618 hal_interrupt_stack_call_pending_DSRs: | |
| 619 stmfd sp!,{r4,r5,lr} | |
| 620 // Disable interrupts | |
| 621 mrs r4,cpsr // disable IRQ's | |
| 622 orr r2,r4,#CPSR_IRQ_DISABLE | |
| 623 bic r5,r4,#CPSR_IRQ_DISABLE | |
| 624 msr cpsr,r2 | |
| 625 // Switch to interrupt stack | |
| 626 mov r3,sp // save old stack pointer | |
| 627 ldr sp,.__interrupt_stack | |
| 628 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 629 ldr r2,.irq_level // current number of nested interrupts | |
| 630 ldr r3,[r2] | |
| 631 add r3,r3,#1 // bump nesting level | |
| 632 str r3,[r2] | |
| 633 msr cpsr,r5 // enable interrupts | |
| 634 | |
| 635 bl cyg_interrupt_call_pending_DSRs | |
| 636 | |
| 637 // Disable interrupts | |
| 638 mrs r1,cpsr // disable IRQ's | |
| 639 orr r2,r1,#CPSR_IRQ_DISABLE | |
| 640 msr cpsr,r2 | |
| 641 | |
| 642 // Move back to the thread stack. | |
| 643 ldr r2,.irq_level | |
| 644 ldr r3,[r2] | |
| 645 sub r3,r3,#1 // decrement nesting level | |
| 646 str r3,[r2] | |
| 647 ldr sp,[sp] // This should be the saved stack pointer | |
| 648 msr cpsr,r4 // restore interrupts to original state | |
| 649 | |
| 650 ldmfd sp!,{r4,r5,pc} // return | |
| 651 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
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652 |
| 2 | 653 |
| 654 // Dummy functions | |
| 655 | |
| 656 .global __gccmain | |
| 657 __gccmain: | |
| 658 mov pc,lr | |
| 659 | |
| 660 .global _psr | |
| 661 _psr: | |
| 662 mrs r0,cpsr | |
| 663 mov pc,lr | |
| 664 | |
| 665 .global _sp | |
| 666 _sp: | |
| 667 mov r0,sp | |
| 668 mov pc,lr | |
| 669 | |
| 670 | |
| 671 // | |
| 672 // Pointers to various objects. | |
| 673 // | |
| 674 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 675 PTR(__GDB_stack_base) | |
| 676 PTR(__GDB_stack) | |
| 677 #endif | |
| 678 PTR(__startup_stack) | |
| 679 PTR(__exception_stack) | |
| 680 PTR(__undef_exception_stack) | |
| 681 PTR(__bss_start) | |
| 682 PTR(__bss_end) | |
| 683 PTR(_end) | |
| 684 PTR(__rom_data_start) | |
| 685 PTR(__ram_data_start) | |
| 686 PTR(__ram_data_end) | |
| 687 PTR(hal_interrupt_handlers) | |
| 688 PTR(hal_interrupt_data) | |
| 689 PTR(hal_interrupt_objects) | |
| 690 PTR(__exception_handlers) | |
| 691 PTR(init_flag) | |
| 692 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 693 PTR(cyg_scheduler_sched_lock) | |
| 694 #endif | |
| 695 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 696 PTR(irq_level) | |
| 697 PTR(__interrupt_stack) | |
| 698 #endif | |
| 699 | |
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700 // |
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701 // Identification - useful to find out when a system was configured |
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702 _eCos_id: |
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703 .asciz "eCos v1.2.1: " __DATE__ |
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704 |
| 2 | 705 |
| 706 // ------------------------------------------------------------------------- | |
| 707 // Interrupt vector tables. | |
| 708 // These tables contain the isr, data and object pointers used to deliver | |
| 709 // interrupts to user code. | |
| 710 | |
| 711 .data | |
| 712 | |
| 713 init_flag: | |
| 714 .long 0 | |
| 715 | |
| 716 .extern hal_default_isr | |
| 717 | |
| 718 .globl hal_vsr_table | |
| 719 hal_vsr_table: | |
| 720 .rept CYGNUM_HAL_VSR_COUNT | |
| 721 .long 0 // hal_default_isr | |
| 722 .endr | |
| 723 | |
| 724 .globl hal_interrupt_handlers | |
| 725 hal_interrupt_handlers: | |
| 726 .rept CYGNUM_HAL_ISR_COUNT | |
| 727 .long hal_default_isr | |
| 728 .endr | |
| 729 | |
| 730 .globl hal_interrupt_data | |
| 731 hal_interrupt_data: | |
| 732 .rept CYGNUM_HAL_ISR_COUNT | |
| 733 .long 0 | |
| 734 .endr | |
| 735 | |
| 736 .globl hal_interrupt_objects | |
| 737 hal_interrupt_objects: | |
| 738 .rept CYGNUM_HAL_ISR_COUNT | |
| 739 .long 0 | |
| 740 .endr | |
| 741 | |
| 742 // ------------------------------------------------------------------------- | |
| 743 // Temporary interrupt stack | |
| 744 | |
| 745 .section ".bss" | |
| 746 | |
| 747 // Small stacks, only used for saving information between CPU modes | |
| 748 __exception_stack_base: | |
| 749 .rept 32 | |
| 750 .long 0 | |
| 751 .endr | |
| 752 __exception_stack: | |
| 753 .rept 32 | |
| 754 .long 0 | |
| 755 .endr | |
| 756 __undef_exception_stack: | |
| 757 | |
| 758 // Runtime stack used during all interrupt processing | |
| 759 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 760 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 761 #endif | |
| 762 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 763 .balign 16 | |
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764 .global cyg_interrupt_stack_base |
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765 cyg_interrupt_stack_base: |
| 2 | 766 __interrupt_stack_base: |
| 767 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 768 .byte 0 | |
| 769 .endr | |
| 770 .balign 16 | |
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771 .global cyg_interrupt_stack |
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772 cyg_interrupt_stack: |
| 2 | 773 __interrupt_stack: |
| 774 irq_level: | |
| 775 .long 0 | |
| 776 #endif | |
| 777 | |
| 778 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 779 .balign 16 | |
| 780 __GDB_stack_base: | |
| 781 .rept 0x400 | |
| 782 .byte 0 | |
| 783 .endr | |
| 784 __GDB_stack: | |
| 785 #endif | |
| 786 .balign 16 | |
| 787 __startup_stack_base: | |
| 788 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 789 .rept 512 | |
| 790 #else | |
| 791 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 792 #endif | |
| 793 .byte 0 | |
| 794 .endr | |
| 795 .balign 16 | |
| 796 __startup_stack: | |
| 797 | |
| 798 // -------------------------------------------------------------------------- | |
| 799 // end of vectors.S |